Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16593729	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

170707978

1

T1

10000

T2

196606

T4

3247

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	92367840	1			T1	5064		T2	65536		T4	32495
values[0x0]	45816932	1			T1	2491		T2	65646		T4	10380
values[0x1]	49116935	1			T1	2445		T2	65424		T4	22444

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8448755	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

178852952

1

T1

10000

T2

196606

T4

29907

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	592509	1			T1	21		T4	267		T5	5012
valid_sources[0x01]	576349	1			T1	42		T4	285		T5	5045
valid_sources[0x02]	601898	1			T1	46		T4	282		T5	5414
valid_sources[0x03]	1887213	1			T1	37		T4	232		T5	5371
valid_sources[0x04]	586329	1			T1	36		T4	239		T5	5247
valid_sources[0x05]	566613	1			T1	42		T4	307		T5	4983
valid_sources[0x06]	575902	1			T1	34		T4	333		T5	5186
valid_sources[0x07]	579183	1			T1	39		T4	287		T5	5408
valid_sources[0x08]	568414	1			T1	29		T4	284		T5	5473
valid_sources[0x09]	619417	1			T1	52		T4	289		T5	5700
valid_sources[0x0a]	569597	1			T1	55		T4	220		T5	5429
valid_sources[0x0b]	580928	1			T1	48		T4	282		T5	5554
valid_sources[0x0c]	566788	1			T1	50		T4	228		T5	5097
valid_sources[0x0d]	586876	1			T1	35		T4	290		T5	5527
valid_sources[0x0e]	624971	1			T1	42		T4	178		T5	5661
valid_sources[0x0f]	646334	1			T1	40		T4	249		T5	5415
valid_sources[0x10]	568530	1			T1	46		T4	232		T5	5178
valid_sources[0x11]	602089	1			T1	41		T4	278		T5	5152
valid_sources[0x12]	620824	1			T1	49		T4	258		T5	5386
valid_sources[0x13]	577181	1			T1	45		T4	250		T5	5546
valid_sources[0x14]	3444043	1			T1	26		T4	229		T5	5580
valid_sources[0x15]	719165	1			T1	40		T4	273		T5	5133
valid_sources[0x16]	572091	1			T1	17		T4	173		T5	5478
valid_sources[0x17]	568286	1			T1	30		T4	190		T5	5921
valid_sources[0x18]	634879	1			T1	38		T4	250		T5	5621
valid_sources[0x19]	595167	1			T1	50		T4	260		T5	5911
valid_sources[0x1a]	588001	1			T1	61		T4	264		T5	5329
valid_sources[0x1b]	633642	1			T1	45		T4	213		T5	5395
valid_sources[0x1c]	598373	1			T1	35		T4	266		T5	5531
valid_sources[0x1d]	623625	1			T1	18		T4	248		T5	5331
valid_sources[0x1e]	582384	1			T1	36		T4	332		T5	5345
valid_sources[0x1f]	586443	1			T1	39		T4	305		T5	5805
valid_sources[0x20]	608381	1			T1	58		T4	271		T5	5270
valid_sources[0x21]	567899	1			T1	32		T4	290		T5	5270
valid_sources[0x22]	604778	1			T1	39		T4	215		T5	5422
valid_sources[0x23]	565123	1			T1	46		T4	283		T5	5526
valid_sources[0x24]	603211	1			T1	85		T4	276		T5	5262
valid_sources[0x25]	627531	1			T1	23		T4	276		T5	5466
valid_sources[0x26]	1706770	1			T1	42		T4	297		T5	5744
valid_sources[0x27]	2198945	1			T1	48		T4	252		T5	5348
valid_sources[0x28]	1995357	1			T1	21		T4	274		T5	5489
valid_sources[0x29]	566553	1			T1	44		T4	265		T5	5271
valid_sources[0x2a]	1119995	1			T1	27		T4	232		T5	5496
valid_sources[0x2b]	585863	1			T1	51		T4	289		T5	5039
valid_sources[0x2c]	615503	1			T1	34		T4	239		T5	5206
valid_sources[0x2d]	578940	1			T1	34		T4	261		T5	5418
valid_sources[0x2e]	590383	1			T1	30		T4	239		T5	5517
valid_sources[0x2f]	565963	1			T1	29		T4	291		T5	5556
valid_sources[0x30]	595355	1			T1	43		T4	283		T5	5222
valid_sources[0x31]	587809	1			T1	58		T4	208		T5	5759
valid_sources[0x32]	601047	1			T1	29		T4	232		T5	5089
valid_sources[0x33]	570561	1			T1	28		T4	213		T5	5314
valid_sources[0x34]	677087	1			T1	32		T4	346		T5	5628
valid_sources[0x35]	611790	1			T1	60		T4	218		T5	5427
valid_sources[0x36]	594588	1			T1	58		T4	200		T5	5460
valid_sources[0x37]	579437	1			T1	35		T4	219		T5	5725
valid_sources[0x38]	674280	1			T1	31		T4	191		T5	5279
valid_sources[0x39]	566935	1			T1	38		T4	214		T5	5271
valid_sources[0x3a]	601229	1			T1	55		T4	247		T5	5341
valid_sources[0x3b]	570703	1			T1	35		T4	275		T5	5585
valid_sources[0x3c]	2651810	1			T1	46		T4	293		T5	5674
valid_sources[0x3d]	569503	1			T1	29		T4	243		T5	5910
valid_sources[0x3e]	591426	1			T1	45		T4	299		T5	5040
valid_sources[0x3f]	639816	1			T1	35		T4	213		T5	5462
valid_sources[0x40]	602955	1			T1	36		T4	227		T5	5346
valid_sources[0x41]	577444	1			T1	25		T4	243		T5	5463
valid_sources[0x42]	645146	1			T1	44		T4	361		T5	5512
valid_sources[0x43]	2134594	1			T1	34		T4	261		T5	5652
valid_sources[0x44]	599915	1			T1	29		T4	254		T5	5173
valid_sources[0x45]	570265	1			T1	49		T4	363		T5	5205
valid_sources[0x46]	567143	1			T1	38		T4	315		T5	5392
valid_sources[0x47]	627739	1			T1	37		T4	293		T5	5645
valid_sources[0x48]	652631	1			T1	19		T4	221		T5	5477
valid_sources[0x49]	591174	1			T1	20		T4	253		T5	5682
valid_sources[0x4a]	571119	1			T1	41		T4	248		T5	5154
valid_sources[0x4b]	638555	1			T1	46		T4	272		T5	5708
valid_sources[0x4c]	601327	1			T1	15		T4	288		T5	5690
valid_sources[0x4d]	1371511	1			T1	32		T4	220		T5	5419
valid_sources[0x4e]	583486	1			T1	42		T4	223		T5	5490
valid_sources[0x4f]	636971	1			T1	42		T4	287		T5	5351
valid_sources[0x50]	638800	1			T1	37		T4	286		T5	5491
valid_sources[0x51]	618474	1			T1	71		T4	164		T5	5212
valid_sources[0x52]	622745	1			T1	53		T4	194		T5	5557
valid_sources[0x53]	623505	1			T1	38		T4	209		T5	5517
valid_sources[0x54]	585217	1			T1	50		T4	264		T5	5693
valid_sources[0x55]	626838	1			T1	31		T4	257		T5	5254
valid_sources[0x56]	603702	1			T1	49		T4	239		T5	5701
valid_sources[0x57]	599450	1			T1	29		T4	257		T5	5620
valid_sources[0x58]	620883	1			T1	29		T4	257		T5	5343
valid_sources[0x59]	591435	1			T1	39		T4	307		T5	5483
valid_sources[0x5a]	595209	1			T1	56		T4	272		T5	5362
valid_sources[0x5b]	568034	1			T1	25		T4	230		T5	5391
valid_sources[0x5c]	569890	1			T1	41		T4	217		T5	5583
valid_sources[0x5d]	610616	1			T1	42		T4	248		T5	5888
valid_sources[0x5e]	630282	1			T1	49		T4	287		T5	5485
valid_sources[0x5f]	568364	1			T1	48		T4	309		T5	5192
valid_sources[0x60]	651024	1			T1	52		T4	265		T5	5728
valid_sources[0x61]	659498	1			T1	64		T4	253		T5	5267
valid_sources[0x62]	640525	1			T1	36		T4	246		T5	5285
valid_sources[0x63]	612006	1			T1	26		T4	263		T5	5525
valid_sources[0x64]	594541	1			T1	27		T4	278		T5	5454
valid_sources[0x65]	570741	1			T1	50		T4	248		T5	5261
valid_sources[0x66]	571342	1			T1	50		T4	228		T5	4883
valid_sources[0x67]	573187	1			T1	73		T4	262		T5	5346
valid_sources[0x68]	603704	1			T1	28		T4	255		T5	5842
valid_sources[0x69]	584768	1			T1	38		T4	278		T5	5549
valid_sources[0x6a]	574038	1			T1	25		T4	265		T5	5560
valid_sources[0x6b]	618101	1			T1	39		T4	248		T5	5590
valid_sources[0x6c]	627276	1			T1	61		T4	274		T5	5895
valid_sources[0x6d]	645379	1			T1	43		T4	218		T5	5531
valid_sources[0x6e]	594548	1			T1	44		T4	252		T5	5000
valid_sources[0x6f]	594706	1			T1	48		T4	281		T5	5561
valid_sources[0x70]	566073	1			T1	18		T4	271		T5	5252
valid_sources[0x71]	566464	1			T1	18		T4	217		T5	5341
valid_sources[0x72]	611645	1			T1	47		T4	297		T5	5548
valid_sources[0x73]	674114	1			T1	44		T4	288		T5	5428
valid_sources[0x74]	568729	1			T1	36		T4	266		T5	5878
valid_sources[0x75]	560176	1			T1	52		T4	236		T5	5082
valid_sources[0x76]	592483	1			T1	33		T4	300		T5	5445
valid_sources[0x77]	575065	1			T1	25		T4	272		T5	5575
valid_sources[0x78]	626185	1			T1	17		T4	276		T5	5082
valid_sources[0x79]	569274	1			T1	38		T4	297		T5	5505
valid_sources[0x7a]	582852	1			T1	26		T4	231		T5	5450
valid_sources[0x7b]	676530	1			T1	57		T4	324		T5	5890
valid_sources[0x7c]	584910	1			T1	36		T4	235		T5	5275
valid_sources[0x7d]	571435	1			T1	38		T4	228		T5	5086
valid_sources[0x7e]	620403	1			T1	64		T4	207		T5	5381
valid_sources[0x7f]	646765	1			T1	26		T4	211		T5	4904
valid_sources[0x80]	575546	1			T1	34		T4	170		T5	5435

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

84023351

1

T1

5064

T2

65536

T4

269

values[0x0]

all_enables

biggest_size

43341068

1

T1

2491

T2

65646

T4

1491

values[0x1]

all_enables

biggest_size

43343559

1

T1

2445

T2

65424

T4

1487

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45310	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

148575

1

T1

1

T2

98

T3

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	52800	1			T5	28		T6	52		T7	13
values[0x0]	67915	1			T1	2		T2	192		T3	4
values[0x1]	73170	1			T2	216		T3	1		T8	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35216	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

158669

1

T1

1

T2

139

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	579	1			T1	1		T2	1		T14	1
valid_sources[0x01]	737	1			T17	6		T18	7		T155	2
valid_sources[0x02]	699	1			T2	1		T9	2		T17	4
valid_sources[0x03]	710	1			T6	8		T17	4		T61	2
valid_sources[0x04]	1059	1			T34	1		T17	16		T51	2
valid_sources[0x05]	639	1			T2	1		T34	1		T17	12
valid_sources[0x06]	942	1			T2	2		T6	6		T17	5
valid_sources[0x07]	756	1			T2	1		T34	2		T47	1
valid_sources[0x08]	749	1			T2	1		T7	1		T34	1
valid_sources[0x09]	730	1			T2	3		T9	2		T34	1
valid_sources[0x0a]	593	1			T7	1		T37	2		T17	10
valid_sources[0x0b]	840	1			T2	4		T17	2		T18	1
valid_sources[0x0c]	1025	1			T34	1		T35	1		T17	10
valid_sources[0x0d]	1070	1			T2	1		T6	3		T17	3
valid_sources[0x0e]	922	1			T2	1		T34	3		T17	17
valid_sources[0x0f]	737	1			T2	2		T34	1		T17	19
valid_sources[0x10]	651	1			T6	1		T34	2		T17	11
valid_sources[0x11]	621	1			T2	2		T17	17		T18	8
valid_sources[0x12]	667	1			T2	1		T34	2		T14	1
valid_sources[0x13]	652	1			T7	2		T14	2		T17	7
valid_sources[0x14]	700	1			T17	16		T16	1		T18	2
valid_sources[0x15]	630	1			T9	1		T14	3		T17	5
valid_sources[0x16]	678	1			T2	2		T14	2		T17	13
valid_sources[0x17]	1687	1			T2	2		T17	6		T18	3
valid_sources[0x18]	640	1			T2	4		T34	1		T17	6
valid_sources[0x19]	739	1			T2	1		T34	1		T17	13
valid_sources[0x1a]	646	1			T2	2		T14	1		T17	6
valid_sources[0x1b]	749	1			T2	1		T34	1		T17	2
valid_sources[0x1c]	615	1			T2	5		T34	2		T14	3
valid_sources[0x1d]	786	1			T2	1		T9	1		T34	2
valid_sources[0x1e]	641	1			T2	3		T34	2		T17	4
valid_sources[0x1f]	674	1			T2	2		T34	1		T14	1
valid_sources[0x20]	855	1			T2	3		T34	2		T14	1
valid_sources[0x21]	720	1			T2	1		T14	1		T17	13
valid_sources[0x22]	817	1			T2	1		T34	3		T17	12
valid_sources[0x23]	932	1			T2	2		T34	1		T38	1
valid_sources[0x24]	739	1			T2	1		T14	2		T17	20
valid_sources[0x25]	705	1			T2	1		T34	1		T38	2
valid_sources[0x26]	663	1			T1	1		T2	3		T7	3
valid_sources[0x27]	666	1			T2	3		T17	17		T70	1
valid_sources[0x28]	915	1			T2	3		T34	4		T17	2
valid_sources[0x29]	835	1			T2	2		T34	4		T17	1
valid_sources[0x2a]	602	1			T2	3		T9	1		T34	2
valid_sources[0x2b]	1018	1			T2	2		T14	1		T17	3
valid_sources[0x2c]	774	1			T2	4		T35	1		T60	1
valid_sources[0x2d]	718	1			T34	1		T38	1		T17	2
valid_sources[0x2e]	710	1			T2	1		T3	1		T34	1
valid_sources[0x2f]	548	1			T2	4		T14	1		T17	7
valid_sources[0x30]	876	1			T2	1		T9	1		T7	2
valid_sources[0x31]	851	1			T2	2		T34	2		T17	2
valid_sources[0x32]	620	1			T2	1		T7	1		T34	1
valid_sources[0x33]	738	1			T2	2		T7	2		T14	1
valid_sources[0x34]	598	1			T2	1		T17	7		T18	1
valid_sources[0x35]	698	1			T2	1		T17	10		T50	2
valid_sources[0x36]	832	1			T2	3		T34	2		T17	1
valid_sources[0x37]	690	1			T2	3		T34	3		T17	4
valid_sources[0x38]	893	1			T2	2		T34	1		T14	2
valid_sources[0x39]	620	1			T2	2		T14	1		T17	4
valid_sources[0x3a]	650	1			T2	1		T3	3		T14	1
valid_sources[0x3b]	942	1			T17	13		T70	1		T18	3
valid_sources[0x3c]	694	1			T2	1		T9	1		T6	1
valid_sources[0x3d]	596	1			T9	1		T34	2		T17	2
valid_sources[0x3e]	905	1			T2	3		T17	15		T18	5
valid_sources[0x3f]	892	1			T2	1		T14	4		T17	1
valid_sources[0x40]	766	1			T2	2		T14	1		T17	6
valid_sources[0x41]	798	1			T17	10		T64	4		T18	4
valid_sources[0x42]	668	1			T2	2		T34	1		T14	2
valid_sources[0x43]	800	1			T2	3		T17	5		T18	6
valid_sources[0x44]	772	1			T2	3		T34	2		T17	6
valid_sources[0x45]	1524	1			T17	2		T18	6		T156	1
valid_sources[0x46]	702	1			T2	1		T9	1		T34	2
valid_sources[0x47]	890	1			T34	1		T17	12		T18	4
valid_sources[0x48]	740	1			T2	1		T17	13		T18	5
valid_sources[0x49]	581	1			T2	1		T17	10		T18	10
valid_sources[0x4a]	846	1			T14	2		T17	1		T18	1
valid_sources[0x4b]	637	1			T2	1		T34	2		T48	1
valid_sources[0x4c]	775	1			T2	2		T14	1		T17	11
valid_sources[0x4d]	818	1			T2	1		T34	1		T14	2
valid_sources[0x4e]	667	1			T2	4		T6	19		T34	1
valid_sources[0x4f]	810	1			T2	2		T34	3		T17	13
valid_sources[0x50]	753	1			T2	1		T17	10		T18	8
valid_sources[0x51]	685	1			T2	3		T38	1		T17	14
valid_sources[0x52]	769	1			T2	1		T14	1		T17	8
valid_sources[0x53]	635	1			T2	1		T17	2		T18	1
valid_sources[0x54]	912	1			T3	1		T34	2		T17	5
valid_sources[0x55]	596	1			T2	1		T34	1		T17	7
valid_sources[0x56]	891	1			T2	1		T14	1		T17	4
valid_sources[0x57]	846	1			T2	1		T34	4		T17	16
valid_sources[0x58]	657	1			T2	1		T6	3		T34	3
valid_sources[0x59]	768	1			T14	2		T17	11		T18	5
valid_sources[0x5a]	626	1			T7	1		T71	14		T92	1
valid_sources[0x5b]	835	1			T2	2		T17	12		T50	1
valid_sources[0x5c]	840	1			T2	1		T34	1		T14	2
valid_sources[0x5d]	791	1			T2	1		T17	14		T20	4
valid_sources[0x5e]	564	1			T34	3		T17	6		T50	1
valid_sources[0x5f]	683	1			T2	2		T34	2		T17	3
valid_sources[0x60]	616	1			T7	1		T34	1		T17	9
valid_sources[0x61]	863	1			T38	1		T17	4		T70	1
valid_sources[0x62]	658	1			T2	1		T6	8		T34	1
valid_sources[0x63]	760	1			T17	8		T50	1		T18	4
valid_sources[0x64]	592	1			T2	1		T14	1		T17	15
valid_sources[0x65]	808	1			T2	1		T14	1		T17	4
valid_sources[0x66]	682	1			T7	1		T14	1		T17	1
valid_sources[0x67]	597	1			T2	3		T34	1		T14	1
valid_sources[0x68]	646	1			T38	1		T17	6		T18	3
valid_sources[0x69]	695	1			T9	1		T38	1		T17	3
valid_sources[0x6a]	877	1			T2	1		T17	2		T18	5
valid_sources[0x6b]	619	1			T2	1		T17	4		T18	5
valid_sources[0x6c]	614	1			T34	1		T17	2		T18	2
valid_sources[0x6d]	875	1			T2	2		T17	7		T50	1
valid_sources[0x6e]	640	1			T7	2		T17	11		T18	9
valid_sources[0x6f]	797	1			T2	3		T6	9		T34	1
valid_sources[0x70]	696	1			T2	2		T14	1		T17	13
valid_sources[0x71]	695	1			T2	2		T34	2		T38	1
valid_sources[0x72]	657	1			T2	1		T9	1		T34	1
valid_sources[0x73]	719	1			T2	2		T34	2		T14	3
valid_sources[0x74]	699	1			T2	1		T17	15		T18	3
valid_sources[0x75]	712	1			T2	3		T34	1		T17	8
valid_sources[0x76]	728	1			T2	2		T34	2		T17	11
valid_sources[0x77]	651	1			T2	1		T34	1		T17	19
valid_sources[0x78]	651	1			T2	4		T7	2		T34	1
valid_sources[0x79]	707	1			T2	4		T17	10		T16	3
valid_sources[0x7a]	652	1			T14	1		T17	9		T40	1
valid_sources[0x7b]	596	1			T2	3		T34	1		T17	8
valid_sources[0x7c]	644	1			T2	1		T34	1		T17	13
valid_sources[0x7d]	657	1			T2	1		T6	2		T17	12
valid_sources[0x7e]	969	1			T2	2		T17	21		T18	7
valid_sources[0x7f]	675	1			T2	1		T9	2		T34	1
valid_sources[0x80]	718	1			T2	2		T6	6		T34	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

39830

1

T5

12

T6

24

T7

7

values[0x0]

all_enables

biggest_size

55806

1

T1

1

T2

63

T3

3

values[0x1]

all_enables

biggest_size

52939

1

T2

35

T8

2

T5

3