Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16490477

1

T4

62072

T5

596

T6

24156

full_word

167631850

1

T1

10000

T2

196606

T4

3247

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	184122017	1			T1	10000		T2	196606		T4	65319
auto[TlIntgErrCmd]	110	1			T67	12		T68	9		T69	10
auto[TlIntgErrData]	102	1			T67	3		T68	5		T69	6
auto[TlIntgErrBoth]	98	1			T67	5		T68	6		T69	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

89096392

1

T1

5064

T2

65536

T4

32495

auto[1]

95025935

1

T1

4936

T2

131070

T4

32824

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8084206	1			T4	32226		T5	305		T6	9959
auto[TlIntgErrNone]	partial	auto[1]	8405980	1			T4	29846		T5	291		T6	14197
auto[TlIntgErrNone]	full_word	auto[0]	81012048	1			T1	5064		T2	65536		T4	269
auto[TlIntgErrNone]	full_word	auto[1]	86619783	1			T1	4936		T2	131070		T4	2978
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T67	4		T68	6		T69	5
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T67	7		T68	3		T69	5
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T67	1		T128	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T132	1		T133	1		T135	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T67	3		T68	4		T69	3
auto[TlIntgErrData]	partial	auto[1]	45	1			T68	1		T69	3		T130	4
auto[TlIntgErrData]	full_word	auto[0]	2	1			T132	1		T136	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T131	1		T137	1		T138	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1			T132	3		T127	2		T128	2
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T67	5		T68	5		T69	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T69	1		T132	1		T139	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T68	1		T69	2		T140	1