Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	709485	1			T4	1736		T6	7288		T14	409
auto[1]	11609853	1			T1	5064		T4	4937		T5	1
auto[2]	512434	1			T4	1182		T6	4613		T14	270
auto[3]	11298944	1			T1	4935		T4	4435		T5	5

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	15189129	1			T1	9999		T4	9		T5	4
auto[1]	2283451	1			T4	154		T6	1380		T7	38
auto[2]	2319673	1			T4	685		T5	1		T6	1210
auto[3]	4338463	1			T4	11442		T5	1		T6	163

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10229868

1

T1

9998

T4

12289

T5

6

auto[1]

13900848

1

T1

1

T4

1

T37

95683

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	289465	1			T6	6039		T14	336		T39	1
auto[0]	auto[0]	auto[1]	30392	1			T4	11		T6	581		T14	30
auto[0]	auto[0]	auto[2]	30552	1			T4	6		T6	607		T14	39
auto[0]	auto[0]	auto[3]	44394	1			T4	1718		T6	61		T14	4
auto[0]	auto[1]	auto[0]	3809366	1			T1	5064		T4	1		T5	1
auto[0]	auto[1]	auto[1]	389233	1			T4	32		T6	403		T7	21
auto[0]	auto[1]	auto[2]	405771	1			T4	279		T6	70		T7	18
auto[0]	auto[1]	auto[3]	305431	1			T4	4625		T6	41		T7	3
auto[0]	auto[2]	auto[0]	186662	1			T6	3906		T20	737		T16	20
auto[0]	auto[2]	auto[1]	20767	1			T6	376		T20	75		T16	5
auto[0]	auto[2]	auto[2]	23556	1			T4	5		T6	300		T14	246
auto[0]	auto[2]	auto[3]	31246	1			T4	1177		T6	31		T14	24
auto[0]	auto[3]	auto[0]	3613308	1			T1	4934		T4	8		T5	3
auto[0]	auto[3]	auto[1]	383033	1			T4	111		T6	20		T7	17
auto[0]	auto[3]	auto[2]	389915	1			T4	395		T5	1		T6	233
auto[0]	auto[3]	auto[3]	276777	1			T4	3921		T5	1		T6	30
auto[1]	auto[0]	auto[0]	10435	1			T48	136		T145	1		T147	2
auto[1]	auto[0]	auto[1]	46587	1			T48	518		T149	892		T150	1153
auto[1]	auto[0]	auto[2]	46572	1			T48	559		T149	895		T150	1211
auto[1]	auto[0]	auto[3]	211088	1			T4	1		T48	2488		T99	1
auto[1]	auto[1]	auto[0]	3638682	1			T37	39660		T48	249		T81	3372
auto[1]	auto[1]	auto[1]	699684	1			T37	3935		T48	1796		T81	13646
auto[1]	auto[1]	auto[2]	693942	1			T37	4004		T48	995		T81	14837
auto[1]	auto[1]	auto[3]	1667744	1			T37	383		T48	8346		T81	61399
auto[1]	auto[2]	auto[0]	7414	1			T82	1		T149	135		T151	1
auto[1]	auto[2]	auto[1]	33331	1			T149	526		T152	1		T153	3215
auto[1]	auto[2]	auto[2]	37791	1			T48	486		T149	937		T150	952
auto[1]	auto[2]	auto[3]	171667	1			T48	2245		T149	4427		T154	1
auto[1]	auto[3]	auto[0]	3633797	1			T1	1		T37	39436		T48	106
auto[1]	auto[3]	auto[1]	680424	1			T37	3943		T38	1		T48	431
auto[1]	auto[3]	auto[2]	691574	1			T37	3911		T48	1816		T81	13606
auto[1]	auto[3]	auto[3]	1630116	1			T37	411		T48	8152		T81	61241