Unified Coverage Report :: Module :: prim_ram_1p_scr

Module : prim_ram_1p_scr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.53	98.11	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_ram_1p_scr	99.53	98.11	100.00			100.00	100.00

---

Module Instance : tb.dut.u_prim_ram_1p_scr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.53	98.11	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.85	99.26	100.00	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_addr_scr.u_prim_subst_perm	100.00	100.00
gen_diffuse_data[0].u_prim_subst_perm_dec	100.00	100.00
gen_diffuse_data[0].u_prim_subst_perm_enc	100.00	100.00
gen_par_scr[0].u_prim_prince	100.00			100.00
u_addr_collision_flop	100.00	100.00				100.00
u_addr_match_buf	100.00	100.00
u_intg_error	100.00	100.00
u_prim_ram_1p_adv	100.00	100.00				100.00	100.00
u_read_en_buf	100.00	100.00
u_rvalid_flop	100.00	100.00				100.00
u_write_en_d_buf	100.00	100.00
u_write_en_flop	100.00	100.00				100.00
u_write_pending_flop	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_ram_1p_scr

	Line No.	Total	Covered	Percent
TOTAL		53	52	98.11
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	190	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	198	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	361	1	1	100.00
CONT_ASSIGN	370	1	1	100.00
ALWAYS	376	10	9	90.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	448	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
ALWAYS	452	18	18	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv' or '../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
133	1	1
135	1	1
136	1	1
145	1	1
154	1	1
163	1	1
171	1	1
182	1	1
186	1	1
190	1	1
194	1	1
198	1	1
206	1	1
211	1	1
232	1	1
245	1	1
274	1	1
280	1	1
306	1	1
336	1	1
361	1	1
370	1	1
376	1	1
377	1	1
379	1	1
380	1	1
383	1	1
384	1	1
385	1	1
386	1	1
388	0	1
394	1	1
			MISSING_ELSE
404	1	1
448	1	1
449	1	1
452	1	1
453	1	1
454	1	1
455	1	1
456	1	1
457	1	1
458	1	1
459	1	1
461	1	1
463	1	1
464	1	1
			MISSING_ELSE
466	1	1
467	1	1
468	1	1
469	1	1
470	1	1
			MISSING_ELSE
472	1	1
473	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_ram_1p_scr

	Total	Covered	Percent
Conditions	11	11	100.00
Logical	11	11	100.00
Non-Logical	0	0
Event	0	0

 LINE       133
 EXPRESSION (req_i & key_valid_i)
             --1--   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T2,T4

 LINE       163
 EXPRESSION ((addr_scr == waddr_scr_q) ? MuBi4True : MuBi4False)
             ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       163
 SUB-EXPRESSION (addr_scr == waddr_scr_q)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       361
 EXPRESSION (macro_write ? MuBi4False : (rw_collision ? MuBi4True : write_pending_q))
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       361
 SUB-EXPRESSION (rw_collision ? MuBi4True : write_pending_q)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

---

Branch Coverage for Module : prim_ram_1p_scr

	Line No.	Total	Covered	Percent
Branches		15	15	100.00
TERNARY	163	2	2	100.00
TERNARY	361	3	3	100.00
IF	379	3	3	100.00
IF	452	7	7	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv' or '../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	163	((addr_scr == waddr_scr_q)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	361	(macro_write) ? 
-2-:	361	(rw_collision) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	379	if (((!intg_error_r_q) && prim_mubi_pkg::mubi4_test_true_loose(rvalid_q)))
-2-:	383	if (prim_mubi_pkg::mubi4_test_true_loose(addr_collision_q))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T37,T38,T48
1	0	Covered	T1,T2,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	452	if ((!rst_ni))
-2-:	463	if (read_en_b)
-3-:	466	if (write_en_b)
-4-:	472	if (rw_collision)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T4
0	0	-	-	Covered	T1,T2,T3
0	-	1	-	Covered	T1,T2,T4
0	-	0	-	Covered	T1,T2,T3
0	-	-	1	Covered	T1,T4,T5
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_ram_1p_scr

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DepthPow2Check_A	901	901	0	0
DiffWidthMinimum_A	901	901	0	0
DiffWidthWithParity_A	901	901	0	0

DepthPow2Check_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	901	901	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

DiffWidthMinimum_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	901	901	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

DiffWidthWithParity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	901	901	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0