Unified Coverage Report :: Module :: sram_ctrl_regs_reg_top

Module : sram_ctrl_regs_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.58	100.00	98.31			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl_regs_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_regs	99.58	100.00	98.31			100.00	100.00

---

Module Instance : tb.dut.u_reg_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.58	100.00	98.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.03	98.43	96.44	100.00		95.28	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_ctrl0_qe	100.00	100.00				100.00
u_ctrl_init	100.00	100.00	100.00			100.00
u_ctrl_regwen	100.00	100.00	100.00			100.00
u_ctrl_renew_scr_key	100.00	100.00	100.00			100.00
u_exec	100.00	100.00	100.00			100.00
u_exec_regwen	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_readback	100.00	100.00	100.00			100.00
u_readback_regwen	66.30	88.89	50.00			60.00
u_reg_if	99.69	100.00	98.75			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_scr_key_rotated	100.00	100.00	100.00			100.00
u_status_bus_integ_error	100.00	100.00	100.00			100.00
u_status_escalated	100.00	100.00	100.00			100.00
u_status_init_done	100.00	100.00	100.00			100.00
u_status_init_error	100.00	100.00	100.00			100.00
u_status_readback_error	62.59	77.78	50.00			60.00
u_status_scr_key_seed_valid	100.00	100.00	100.00			100.00
u_status_scr_key_valid	100.00	100.00	100.00			100.00
u_status_sram_alert	62.59	77.78	50.00			60.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sram_ctrl_regs_reg_top

	Line No.	Total	Covered	Percent
TOTAL		76	76	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	613	1	1	100.00
ALWAYS	644	10	10	100.00
CONT_ASSIGN	656	1	1	100.00
ALWAYS	660	1	1	100.00
CONT_ASSIGN	673	1	1	100.00
CONT_ASSIGN	675	1	1	100.00
CONT_ASSIGN	676	1	1	100.00
CONT_ASSIGN	678	1	1	100.00
CONT_ASSIGN	679	1	1	100.00
CONT_ASSIGN	681	1	1	100.00
CONT_ASSIGN	682	1	1	100.00
CONT_ASSIGN	684	1	1	100.00
CONT_ASSIGN	685	1	1	100.00
CONT_ASSIGN	687	1	1	100.00
CONT_ASSIGN	689	1	1	100.00
CONT_ASSIGN	690	1	1	100.00
CONT_ASSIGN	692	1	1	100.00
CONT_ASSIGN	693	1	1	100.00
CONT_ASSIGN	695	1	1	100.00
CONT_ASSIGN	696	1	1	100.00
CONT_ASSIGN	698	1	1	100.00
ALWAYS	702	10	10	100.00
ALWAYS	716	19	19	100.00
CONT_ASSIGN	773	0	0
CONT_ASSIGN	781	1	1	100.00
CONT_ASSIGN	782	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl_regs_reg_top.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl_regs_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
77	1	1
89	1	1
90	1	1
118	1	1
119	1	1
160	1	1
174	1	1
426	1	1
496	1	1
523	1	1
551	1	1
613	1	1
644	1	1
645	1	1
646	1	1
647	1	1
648	1	1
649	1	1
650	1	1
651	1	1
652	1	1
653	1	1
656	1	1
660	1	1
673	1	1
675	1	1
676	1	1
678	1	1
679	1	1
681	1	1
682	1	1
684	1	1
685	1	1
687	1	1
689	1	1
690	1	1
692	1	1
693	1	1
695	1	1
696	1	1
698	1	1
702	1	1
703	1	1
704	1	1
705	1	1
706	1	1
707	1	1
708	1	1
709	1	1
710	1	1
711	1	1
716	1	1
717	1	1
719	1	1
723	1	1
724	1	1
725	1	1
726	1	1
727	1	1
728	1	1
729	1	1
730	1	1
734	1	1
738	1	1
742	1	1
746	1	1
747	1	1
751	1	1
755	1	1
759	1	1
773		unreachable
781	1	1
782	1	1

---

Cond Coverage for Module : sram_ctrl_regs_reg_top

	Total	Covered	Percent
Conditions	118	116	98.31
Logical	118	116	98.31
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T17,T18,T19
1	1	Covered	T1,T2,T3

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T67,T68,T69

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T11,T12,T13
0	1	0	Covered	T67,T68,T69
1	0	0	Covered	T11,T12,T13

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T67,T68,T69
0	1	0	Covered	T17,T18,T19
1	0	0	Covered	T17,T18,T19

 LINE       426
 EXPRESSION (exec_we & exec_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T14,T70
1	1	Covered	T6,T14,T20

 LINE       496
 EXPRESSION (ctrl_we & ctrl_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T14,T15
1	1	Covered	T1,T4,T5

 LINE       613
 EXPRESSION (readback_we & readback_regwen_qs)
             -----1-----   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

 LINE       645
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_ALERT_TEST_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T8,T5

 LINE       646
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_STATUS_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       647
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_EXEC_REGWEN_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       648
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_EXEC_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       649
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_CTRL_REGWEN_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       650
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_CTRL_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       651
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_SCR_KEY_ROTATED_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T14

 LINE       652
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_READBACK_REGWEN_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T14

 LINE       653
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_READBACK_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       656
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       656
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7

 LINE       660
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T18,T19

 LINE       660
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))))

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
0	0	0	0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	0	0	0	1	Covered	T5,T7,T14
0	0	0	0	0	0	0	1	0	Covered	T5,T7,T14
0	0	0	0	0	0	1	0	0	Covered	T5,T7,T14
0	0	0	0	0	1	0	0	0	Covered	T5,T6,T7
0	0	0	0	1	0	0	0	0	Covered	T5,T7,T14
0	0	0	1	0	0	0	0	0	Covered	T4,T5,T7
0	0	1	0	0	0	0	0	0	Covered	T5,T7,T14
0	1	0	0	0	0	0	0	0	Covered	T5,T6,T7
1	0	0	0	0	0	0	0	0	Covered	T7,T14,T71

 LINE       660
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T3,T8,T5
1	1	Covered	T7,T14,T71

 LINE       660
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       660
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T7,T14

 LINE       660
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T14
1	1	Covered	T4,T5,T7

 LINE       660
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T14
1	1	Covered	T5,T7,T14

 LINE       660
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T4,T5
1	1	Covered	T5,T6,T7

 LINE       660
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T7,T14
1	1	Covered	T5,T7,T14

 LINE       660
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T7,T14
1	1	Covered	T5,T7,T14

 LINE       660
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T3,T8
1	1	Covered	T5,T7,T14

 LINE       673
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T8,T5
1	1	0	Covered	T17,T18,T19
1	1	1	Covered	T3,T8,T9

 LINE       676
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T17,T18,T19
1	1	1	Covered	T6,T14,T15

 LINE       679
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T17,T18,T19
1	1	1	Covered	T6,T14,T20

 LINE       682
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T17,T18,T19
1	1	1	Covered	T6,T14,T15

 LINE       685
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T8
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T17,T18,T19
1	1	1	Covered	T1,T4,T5

 LINE       690
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T7,T14
1	1	0	Covered	T17,T18,T19
1	1	1	Covered	T67,T72,T73

 LINE       693
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T7,T14
1	1	0	Covered	T17,T18,T19
1	1	1	Not Covered

 LINE       696
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T8
1	0	1	Covered	T2,T3,T8
1	1	0	Covered	T17,T18,T19
1	1	1	Covered	T2,T3,T8

---

Branch Coverage for Module : sram_ctrl_regs_reg_top

	Line No.	Total	Covered	Percent
Branches		15	15	100.00
TERNARY	656	2	2	100.00
IF	68	3	3	100.00
CASE	717	10	10	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl_regs_reg_top.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl_regs_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	656	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	717	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : sram_ctrl_regs_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	1240483693	61715	0	0
reAfterRv	1240483693	61715	0	0
rePulse	1240483693	19964	0	0
wePulse	1240483693	41751	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240483693	61715	0	0
T1	76247	2	0	0
T2	206797	408	0	0
T3	964	5	0	0
T4	440556	3	0	0
T5	106220	74	0	0
T6	458379	169	0	0
T7	559930	28	0	0
T8	771	21	0	0
T9	948	21	0	0
T10	34752	1	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240483693	61715	0	0
T1	76247	2	0	0
T2	206797	408	0	0
T3	964	5	0	0
T4	440556	3	0	0
T5	106220	74	0	0
T6	458379	169	0	0
T7	559930	28	0	0
T8	771	21	0	0
T9	948	21	0	0
T10	34752	1	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240483693	19964	0	0
T5	106220	28	0	0
T6	458379	52	0	0
T7	559930	13	0	0
T9	948	0	0	0
T10	34752	0	0	0
T14	151183	10	0	0
T15	0	3	0	0
T16	0	31	0	0
T17	0	81	0	0
T18	0	47	0	0
T34	103391	0	0	0
T35	67500	0	0	0
T36	73397	0	0	0
T49	958	0	0	0
T70	0	3	0	0
T74	0	25	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240483693	41751	0	0
T1	76247	2	0	0
T2	206797	408	0	0
T3	964	5	0	0
T4	440556	3	0	0
T5	106220	46	0	0
T6	458379	117	0	0
T7	559930	15	0	0
T8	771	21	0	0
T9	948	21	0	0
T10	34752	1	0	0