Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1240483693	217673	0	0
ctrl_regwen_rd_A	1240483693	5274	0	0
exec_rd_A	1240483693	4734	0	0
exec_regwen_rd_A	1240483693	5300	0	0
readback_rd_A	1240483693	3240	0	0
readback_regwen_rd_A	1240483693	3079	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240483693	217673	0	0
T16	941391	0	0	0
T17	52899	2623	0	0
T18	0	1616	0	0
T19	0	2127	0	0
T20	240374	0	0	0
T21	34692	0	0	0
T40	749712	0	0	0
T42	294678	0	0	0
T53	0	2627	0	0
T60	130350	0	0	0
T61	502908	0	0	0
T62	399796	0	0	0
T75	0	2973	0	0
T76	0	1741	0	0
T77	0	2419	0	0
T78	0	2372	0	0
T79	0	2111	0	0
T80	0	2689	0	0
T81	631065	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240483693	5274	0	0
T16	941391	0	0	0
T17	52899	234	0	0
T19	0	192	0	0
T20	240374	0	0	0
T21	34692	0	0	0
T25	0	240	0	0
T40	749712	0	0	0
T42	294678	0	0	0
T53	0	280	0	0
T60	130350	0	0	0
T61	502908	0	0	0
T62	399796	0	0	0
T75	0	87	0	0
T80	0	236	0	0
T81	631065	0	0	0
T123	0	69	0	0
T124	0	403	0	0
T125	0	434	0	0
T126	0	139	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240483693	4734	0	0
T16	941391	0	0	0
T17	52899	249	0	0
T19	0	236	0	0
T20	240374	0	0	0
T21	34692	0	0	0
T25	0	172	0	0
T40	749712	0	0	0
T42	294678	0	0	0
T53	0	232	0	0
T60	130350	0	0	0
T61	502908	0	0	0
T62	399796	0	0	0
T75	0	63	0	0
T80	0	149	0	0
T81	631065	0	0	0
T123	0	54	0	0
T124	0	316	0	0
T125	0	401	0	0
T126	0	76	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240483693	5300	0	0
T16	941391	0	0	0
T17	52899	248	0	0
T19	0	157	0	0
T20	240374	0	0	0
T21	34692	0	0	0
T25	0	174	0	0
T40	749712	0	0	0
T42	294678	0	0	0
T53	0	284	0	0
T60	130350	0	0	0
T61	502908	0	0	0
T62	399796	0	0	0
T75	0	97	0	0
T80	0	217	0	0
T81	631065	0	0	0
T123	0	54	0	0
T124	0	445	0	0
T125	0	452	0	0
T126	0	122	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240483693	3240	0	0
T16	941391	0	0	0
T17	52899	195	0	0
T19	0	186	0	0
T20	240374	0	0	0
T21	34692	0	0	0
T25	0	145	0	0
T40	749712	0	0	0
T42	294678	0	0	0
T53	0	183	0	0
T60	130350	0	0	0
T61	502908	0	0	0
T62	399796	0	0	0
T75	0	100	0	0
T80	0	163	0	0
T81	631065	0	0	0
T123	0	23	0	0
T124	0	338	0	0
T125	0	498	0	0
T126	0	86	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240483693	3079	0	0
T16	941391	0	0	0
T17	52899	235	0	0
T19	0	106	0	0
T20	240374	0	0	0
T21	34692	0	0	0
T25	0	151	0	0
T40	749712	0	0	0
T42	294678	0	0	0
T53	0	258	0	0
T60	130350	0	0	0
T61	502908	0	0	0
T62	399796	0	0	0
T75	0	68	0	0
T80	0	148	0	0
T81	631065	0	0	0
T123	0	40	0	0
T124	0	302	0	0
T125	0	386	0	0
T126	0	64	0	0