Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16776308	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

166005935

1

T1

146056

T4

121525

T5

9139

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	90065388	1			T1	80767		T4	66911		T5	4991
values[0x0]	44684862	1			T1	38861		T4	32046		T5	2392
values[0x1]	48031993	1			T1	41124		T4	34866		T5	2640

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8545730	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

174236513

1

T1

153393

T4

127722

T5

9587

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	592817	1			T1	733		T4	549		T5	38
valid_sources[0x01]	576563	1			T1	650		T4	506		T5	38
valid_sources[0x02]	1879324	1			T1	607		T4	540		T5	50
valid_sources[0x03]	620526	1			T1	627		T4	580		T5	26
valid_sources[0x04]	656493	1			T1	569		T4	532		T5	34
valid_sources[0x05]	591140	1			T1	529		T4	546		T5	64
valid_sources[0x06]	658558	1			T1	554		T4	569		T5	35
valid_sources[0x07]	609573	1			T1	675		T4	579		T5	41
valid_sources[0x08]	635679	1			T1	719		T4	608		T5	28
valid_sources[0x09]	593496	1			T1	574		T4	574		T5	7
valid_sources[0x0a]	2878897	1			T1	548		T4	539		T5	59
valid_sources[0x0b]	762800	1			T1	598		T4	491		T5	18
valid_sources[0x0c]	600713	1			T1	727		T4	489		T5	21
valid_sources[0x0d]	842533	1			T1	562		T4	530		T5	37
valid_sources[0x0e]	639787	1			T1	654		T4	506		T5	49
valid_sources[0x0f]	576155	1			T1	503		T4	598		T5	26
valid_sources[0x10]	622295	1			T1	673		T4	541		T5	20
valid_sources[0x11]	600892	1			T1	616		T4	540		T5	48
valid_sources[0x12]	606104	1			T1	498		T4	500		T5	28
valid_sources[0x13]	582837	1			T1	532		T4	527		T5	31
valid_sources[0x14]	568445	1			T1	677		T4	491		T5	17
valid_sources[0x15]	2176664	1			T1	597		T4	514		T5	48
valid_sources[0x16]	656876	1			T1	645		T4	570		T5	38
valid_sources[0x17]	823510	1			T1	532		T4	525		T5	45
valid_sources[0x18]	580876	1			T1	581		T4	537		T5	28
valid_sources[0x19]	705769	1			T1	630		T4	542		T5	22
valid_sources[0x1a]	595866	1			T1	651		T4	582		T5	58
valid_sources[0x1b]	578018	1			T1	580		T4	534		T5	21
valid_sources[0x1c]	577974	1			T1	578		T4	529		T5	34
valid_sources[0x1d]	603425	1			T1	682		T4	474		T5	39
valid_sources[0x1e]	581972	1			T1	642		T4	496		T5	27
valid_sources[0x1f]	648823	1			T1	552		T4	539		T5	95
valid_sources[0x20]	597969	1			T1	646		T4	534		T5	33
valid_sources[0x21]	579107	1			T1	600		T4	512		T5	41
valid_sources[0x22]	574831	1			T1	688		T4	494		T5	33
valid_sources[0x23]	574976	1			T1	605		T4	520		T5	50
valid_sources[0x24]	594465	1			T1	592		T4	466		T5	38
valid_sources[0x25]	1864423	1			T1	621		T4	514		T5	36
valid_sources[0x26]	578348	1			T1	605		T4	529		T5	45
valid_sources[0x27]	1965027	1			T1	607		T4	504		T5	22
valid_sources[0x28]	2388495	1			T1	496		T4	513		T5	58
valid_sources[0x29]	593385	1			T1	702		T4	479		T5	33
valid_sources[0x2a]	577963	1			T1	557		T4	531		T5	42
valid_sources[0x2b]	588737	1			T1	656		T4	576		T5	31
valid_sources[0x2c]	580907	1			T1	615		T4	536		T5	52
valid_sources[0x2d]	596712	1			T1	624		T4	502		T5	50
valid_sources[0x2e]	646935	1			T1	608		T4	575		T5	56
valid_sources[0x2f]	608541	1			T1	550		T4	527		T5	94
valid_sources[0x30]	616554	1			T1	667		T4	539		T5	28
valid_sources[0x31]	582340	1			T1	640		T4	522		T5	28
valid_sources[0x32]	668025	1			T1	614		T4	545		T5	103
valid_sources[0x33]	621935	1			T1	599		T4	508		T5	30
valid_sources[0x34]	603222	1			T1	676		T4	517		T5	29
valid_sources[0x35]	580737	1			T1	652		T4	493		T5	44
valid_sources[0x36]	594505	1			T1	599		T4	581		T5	65
valid_sources[0x37]	1311747	1			T1	662		T4	556		T5	50
valid_sources[0x38]	583621	1			T1	617		T4	535		T5	27
valid_sources[0x39]	605014	1			T1	586		T4	522		T5	28
valid_sources[0x3a]	607157	1			T1	666		T4	523		T5	93
valid_sources[0x3b]	986739	1			T1	662		T4	441		T5	30
valid_sources[0x3c]	2490991	1			T1	683		T4	546		T5	61
valid_sources[0x3d]	580618	1			T1	491		T4	554		T5	21
valid_sources[0x3e]	778291	1			T1	625		T4	494		T5	20
valid_sources[0x3f]	591082	1			T1	573		T4	516		T5	40
valid_sources[0x40]	603917	1			T1	731		T4	563		T5	18
valid_sources[0x41]	1318854	1			T1	683		T4	530		T5	18
valid_sources[0x42]	574143	1			T1	694		T4	541		T5	38
valid_sources[0x43]	613648	1			T1	552		T4	543		T5	65
valid_sources[0x44]	585673	1			T1	564		T4	541		T5	16
valid_sources[0x45]	607502	1			T1	748		T4	480		T5	22
valid_sources[0x46]	608462	1			T1	716		T4	530		T5	21
valid_sources[0x47]	2177783	1			T1	555		T4	512		T5	21
valid_sources[0x48]	601505	1			T1	620		T4	500		T5	23
valid_sources[0x49]	613558	1			T1	660		T4	505		T5	40
valid_sources[0x4a]	1414042	1			T1	573		T4	517		T5	45
valid_sources[0x4b]	627770	1			T1	597		T4	530		T5	30
valid_sources[0x4c]	613259	1			T1	536		T4	486		T5	29
valid_sources[0x4d]	664939	1			T1	704		T4	516		T5	67
valid_sources[0x4e]	690336	1			T1	578		T4	552		T5	61
valid_sources[0x4f]	621573	1			T1	652		T4	526		T5	27
valid_sources[0x50]	626023	1			T1	564		T4	540		T5	47
valid_sources[0x51]	588088	1			T1	641		T4	576		T5	43
valid_sources[0x52]	588000	1			T1	628		T4	538		T5	19
valid_sources[0x53]	606519	1			T1	608		T4	477		T5	23
valid_sources[0x54]	676052	1			T1	734		T4	548		T5	71
valid_sources[0x55]	585311	1			T1	510		T4	557		T5	38
valid_sources[0x56]	605590	1			T1	651		T4	475		T5	50
valid_sources[0x57]	623027	1			T1	732		T4	493		T5	33
valid_sources[0x58]	713148	1			T1	630		T4	554		T5	37
valid_sources[0x59]	655653	1			T1	654		T4	518		T5	32
valid_sources[0x5a]	597568	1			T1	695		T4	578		T5	32
valid_sources[0x5b]	1879345	1			T1	640		T4	568		T5	14
valid_sources[0x5c]	626776	1			T1	639		T4	521		T5	46
valid_sources[0x5d]	630406	1			T1	692		T4	563		T5	44
valid_sources[0x5e]	594050	1			T1	593		T4	534		T5	22
valid_sources[0x5f]	582973	1			T1	717		T4	528		T5	39
valid_sources[0x60]	585912	1			T1	687		T4	569		T5	49
valid_sources[0x61]	572406	1			T1	571		T4	532		T5	50
valid_sources[0x62]	615599	1			T1	614		T4	565		T5	36
valid_sources[0x63]	582682	1			T1	598		T4	577		T5	36
valid_sources[0x64]	620209	1			T1	619		T4	565		T5	41
valid_sources[0x65]	603437	1			T1	650		T4	555		T5	30
valid_sources[0x66]	573240	1			T1	653		T4	522		T5	22
valid_sources[0x67]	638931	1			T1	668		T4	543		T5	44
valid_sources[0x68]	619032	1			T1	655		T4	505		T5	51
valid_sources[0x69]	577358	1			T1	738		T4	552		T5	58
valid_sources[0x6a]	585475	1			T1	701		T4	522		T5	55
valid_sources[0x6b]	621856	1			T1	770		T4	513		T5	14
valid_sources[0x6c]	606515	1			T1	654		T4	477		T5	44
valid_sources[0x6d]	600138	1			T1	592		T4	493		T5	44
valid_sources[0x6e]	581440	1			T1	697		T4	533		T5	38
valid_sources[0x6f]	694213	1			T1	604		T4	461		T5	32
valid_sources[0x70]	749449	1			T1	616		T4	564		T5	32
valid_sources[0x71]	667767	1			T1	652		T4	535		T5	20
valid_sources[0x72]	585984	1			T1	610		T4	521		T5	40
valid_sources[0x73]	608045	1			T1	562		T4	523		T5	26
valid_sources[0x74]	593349	1			T1	662		T4	466		T5	31
valid_sources[0x75]	582295	1			T1	590		T4	545		T5	55
valid_sources[0x76]	589195	1			T1	594		T4	523		T5	33
valid_sources[0x77]	590902	1			T1	719		T4	498		T5	22
valid_sources[0x78]	613893	1			T1	580		T4	555		T5	44
valid_sources[0x79]	648140	1			T1	647		T4	536		T5	12
valid_sources[0x7a]	620688	1			T1	632		T4	511		T5	38
valid_sources[0x7b]	688651	1			T1	515		T4	546		T5	63
valid_sources[0x7c]	663281	1			T1	628		T4	518		T5	57
valid_sources[0x7d]	586015	1			T1	641		T4	525		T5	45
valid_sources[0x7e]	606849	1			T1	588		T4	505		T5	15
valid_sources[0x7f]	590666	1			T1	611		T4	532		T5	24
valid_sources[0x80]	598254	1			T1	511		T4	528		T5	58

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

81624992

1

T1

73425

T4

60735

T5

4546

values[0x0]

all_enables

biggest_size

42183985

1

T1

36608

T4

30164

T5

2267

values[0x1]

all_enables

biggest_size

42196958

1

T1

36023

T4

30626

T5

2326

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46221	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

152838

1

T1

22

T2

1

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	54398	1			T1	12		T4	12		T6	36
values[0x0]	69737	1			T1	22		T2	1		T3	7
values[0x1]	74924	1			T1	25		T3	7		T4	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35895	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

163164

1

T1

26

T2

1

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	721	1			T20	1		T23	10		T164	7
valid_sources[0x01]	670	1			T74	1		T22	4		T20	3
valid_sources[0x02]	784	1			T80	2		T20	1		T160	2
valid_sources[0x03]	735	1			T23	17		T50	1		T81	8
valid_sources[0x04]	652	1			T22	2		T23	10		T157	1
valid_sources[0x05]	907	1			T41	7		T22	2		T20	3
valid_sources[0x06]	843	1			T9	3		T23	12		T157	1
valid_sources[0x07]	709	1			T9	7		T80	1		T42	1
valid_sources[0x08]	774	1			T1	1		T74	1		T9	5
valid_sources[0x09]	472	1			T4	2		T80	1		T20	2
valid_sources[0x0a]	636	1			T20	5		T42	2		T23	21
valid_sources[0x0b]	886	1			T1	1		T22	9		T20	1
valid_sources[0x0c]	638	1			T22	1		T42	2		T23	17
valid_sources[0x0d]	1095	1			T1	2		T41	4		T22	200
valid_sources[0x0e]	536	1			T1	1		T160	1		T42	2
valid_sources[0x0f]	554	1			T42	1		T23	11		T21	6
valid_sources[0x10]	490	1			T1	1		T22	1		T20	1
valid_sources[0x11]	577	1			T165	1		T23	12		T65	1
valid_sources[0x12]	822	1			T40	3		T22	288		T42	2
valid_sources[0x13]	924	1			T80	1		T42	1		T23	12
valid_sources[0x14]	625	1			T4	1		T22	3		T42	2
valid_sources[0x15]	933	1			T19	1		T41	4		T42	1
valid_sources[0x16]	653	1			T22	1		T51	2		T23	6
valid_sources[0x17]	564	1			T41	4		T40	1		T80	1
valid_sources[0x18]	1163	1			T74	1		T39	1		T80	1
valid_sources[0x19]	906	1			T74	1		T42	2		T23	5
valid_sources[0x1a]	600	1			T19	2		T93	2		T22	1
valid_sources[0x1b]	665	1			T9	1		T19	3		T159	2
valid_sources[0x1c]	796	1			T41	9		T80	1		T42	2
valid_sources[0x1d]	717	1			T55	1		T42	1		T23	14
valid_sources[0x1e]	889	1			T75	2		T20	2		T23	12
valid_sources[0x1f]	852	1			T22	1		T42	1		T23	8
valid_sources[0x20]	1145	1			T4	1		T74	1		T23	10
valid_sources[0x21]	586	1			T22	2		T23	14		T68	43
valid_sources[0x22]	521	1			T40	1		T42	1		T23	11
valid_sources[0x23]	832	1			T22	2		T23	9		T157	1
valid_sources[0x24]	788	1			T76	2		T42	2		T23	11
valid_sources[0x25]	589	1			T11	1		T20	1		T42	3
valid_sources[0x26]	884	1			T20	6		T23	7		T24	3
valid_sources[0x27]	725	1			T11	1		T165	1		T23	15
valid_sources[0x28]	1021	1			T1	1		T80	1		T20	1
valid_sources[0x29]	684	1			T74	1		T41	2		T22	1
valid_sources[0x2a]	685	1			T15	1		T42	3		T23	17
valid_sources[0x2b]	708	1			T40	3		T22	202		T23	8
valid_sources[0x2c]	598	1			T22	1		T23	10		T81	5
valid_sources[0x2d]	681	1			T74	1		T39	1		T25	1
valid_sources[0x2e]	531	1			T1	1		T20	3		T23	9
valid_sources[0x2f]	693	1			T4	1		T15	2		T22	1
valid_sources[0x30]	585	1			T74	1		T22	2		T20	3
valid_sources[0x31]	833	1			T41	1		T122	1		T22	2
valid_sources[0x32]	652	1			T4	4		T22	1		T23	6
valid_sources[0x33]	552	1			T4	1		T11	1		T165	1
valid_sources[0x34]	890	1			T40	1		T80	1		T22	1
valid_sources[0x35]	555	1			T159	4		T23	16		T164	8
valid_sources[0x36]	855	1			T22	183		T42	1		T23	6
valid_sources[0x37]	840	1			T22	5		T42	2		T23	17
valid_sources[0x38]	740	1			T22	98		T159	1		T23	14
valid_sources[0x39]	714	1			T22	144		T42	1		T23	4
valid_sources[0x3a]	918	1			T19	1		T102	31		T22	1
valid_sources[0x3b]	826	1			T23	13		T166	10		T157	3
valid_sources[0x3c]	953	1			T1	1		T3	2		T74	1
valid_sources[0x3d]	548	1			T74	2		T19	1		T22	1
valid_sources[0x3e]	630	1			T1	1		T39	1		T42	1
valid_sources[0x3f]	678	1			T4	1		T19	3		T22	2
valid_sources[0x40]	699	1			T1	1		T74	1		T20	3
valid_sources[0x41]	561	1			T41	6		T80	1		T22	2
valid_sources[0x42]	823	1			T1	1		T7	2		T22	2
valid_sources[0x43]	710	1			T4	1		T41	10		T40	1
valid_sources[0x44]	606	1			T1	1		T40	2		T20	1
valid_sources[0x45]	677	1			T9	8		T20	1		T42	1
valid_sources[0x46]	861	1			T160	1		T23	18		T21	58
valid_sources[0x47]	584	1			T75	1		T165	2		T22	1
valid_sources[0x48]	659	1			T11	1		T15	1		T22	86
valid_sources[0x49]	577	1			T39	1		T80	2		T42	1
valid_sources[0x4a]	1168	1			T1	1		T80	1		T20	8
valid_sources[0x4b]	780	1			T22	1		T20	2		T23	10
valid_sources[0x4c]	696	1			T1	1		T74	2		T22	1
valid_sources[0x4d]	472	1			T1	1		T4	1		T74	1
valid_sources[0x4e]	517	1			T15	2		T42	2		T23	14
valid_sources[0x4f]	1026	1			T4	1		T41	10		T22	1
valid_sources[0x50]	590	1			T22	1		T23	8		T167	1
valid_sources[0x51]	576	1			T4	1		T74	1		T23	11
valid_sources[0x52]	957	1			T168	1		T160	2		T42	1
valid_sources[0x53]	1096	1			T1	1		T39	1		T41	4
valid_sources[0x54]	754	1			T80	1		T22	1		T23	11
valid_sources[0x55]	1198	1			T1	1		T4	2		T41	1
valid_sources[0x56]	562	1			T165	2		T20	1		T42	1
valid_sources[0x57]	1083	1			T23	12		T81	4		T145	1
valid_sources[0x58]	821	1			T9	5		T22	2		T42	1
valid_sources[0x59]	929	1			T22	157		T42	2		T23	7
valid_sources[0x5a]	822	1			T52	1		T20	2		T42	1
valid_sources[0x5b]	973	1			T42	1		T23	22		T24	162
valid_sources[0x5c]	1253	1			T160	5		T23	6		T24	13
valid_sources[0x5d]	687	1			T75	6		T20	3		T23	4
valid_sources[0x5e]	522	1			T19	1		T42	3		T23	10
valid_sources[0x5f]	678	1			T22	1		T42	1		T23	7
valid_sources[0x60]	1163	1			T1	1		T20	6		T42	1
valid_sources[0x61]	696	1			T1	1		T22	1		T23	2
valid_sources[0x62]	592	1			T20	3		T42	1		T159	1
valid_sources[0x63]	944	1			T22	214		T42	1		T23	6
valid_sources[0x64]	647	1			T1	1		T4	2		T39	1
valid_sources[0x65]	573	1			T74	1		T80	1		T22	3
valid_sources[0x66]	753	1			T80	1		T22	1		T20	5
valid_sources[0x67]	812	1			T20	7		T169	1		T23	3
valid_sources[0x68]	771	1			T1	1		T19	1		T40	1
valid_sources[0x69]	686	1			T74	1		T23	11		T157	1
valid_sources[0x6a]	890	1			T1	1		T40	1		T80	1
valid_sources[0x6b]	549	1			T74	2		T22	1		T20	1
valid_sources[0x6c]	520	1			T11	1		T165	1		T20	2
valid_sources[0x6d]	916	1			T4	2		T74	2		T19	2
valid_sources[0x6e]	533	1			T4	1		T20	2		T23	2
valid_sources[0x6f]	893	1			T40	1		T42	1		T23	7
valid_sources[0x70]	537	1			T23	16		T68	18		T157	2
valid_sources[0x71]	711	1			T80	2		T20	2		T42	3
valid_sources[0x72]	643	1			T52	1		T20	1		T42	2
valid_sources[0x73]	993	1			T22	107		T20	2		T160	4
valid_sources[0x74]	871	1			T3	7		T80	1		T22	1
valid_sources[0x75]	643	1			T20	2		T23	11		T68	34
valid_sources[0x76]	1193	1			T1	1		T3	1		T22	1
valid_sources[0x77]	592	1			T20	2		T42	1		T159	2
valid_sources[0x78]	897	1			T19	1		T42	2		T23	8
valid_sources[0x79]	1180	1			T12	51		T39	1		T42	2
valid_sources[0x7a]	774	1			T41	3		T23	11		T157	2
valid_sources[0x7b]	668	1			T23	6		T166	1		T170	1
valid_sources[0x7c]	845	1			T41	6		T22	1		T54	2
valid_sources[0x7d]	1574	1			T4	1		T39	1		T80	1
valid_sources[0x7e]	464	1			T80	1		T42	2		T23	4
valid_sources[0x7f]	516	1			T74	1		T39	1		T42	3
valid_sources[0x80]	672	1			T122	1		T80	1		T56	96

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

41187

1

T1

6

T4

6

T6

21

values[0x0]

all_enables

biggest_size

57357

1

T1

9

T2

1

T3

2

values[0x1]

all_enables

biggest_size

54294

1

T1

7

T4

4

T8

1