Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16617414

1

T1

11927

T4

11594

T5

884

full_word

162287212

1

T1

118200

T4

114567

T5

9139

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	178904316	1			T1	130127		T4	126161		T5	10023
auto[TlIntgErrCmd]	107	1			T71	3		T72	10		T73	1
auto[TlIntgErrData]	95	1			T71	4		T72	6		T73	5
auto[TlIntgErrBoth]	108	1			T71	3		T72	4		T73	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86120296

1

T1

50142

T4

59249

T5

4991

auto[1]

92784330

1

T1

79985

T4

66912

T5

5032

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8120956	1			T1	4573		T4	5472		T5	445
auto[TlIntgErrNone]	partial	auto[1]	8496176	1			T1	7354		T4	6122		T5	439
auto[TlIntgErrNone]	full_word	auto[0]	77999202	1			T1	45569		T4	53777		T5	4546
auto[TlIntgErrNone]	full_word	auto[1]	84287982	1			T1	72631		T4	60790		T5	4593
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T71	1		T72	2		T152	2
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T71	2		T72	8		T73	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T150	1		T153	1		T154	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T152	1		T155	1		T156	2
auto[TlIntgErrData]	partial	auto[0]	43	1			T71	1		T72	2		T73	5
auto[TlIntgErrData]	partial	auto[1]	40	1			T71	3		T72	4		T146	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T152	2		T146	2		T149	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T146	1		T150	1		T154	2
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T71	1		T73	1		T152	2
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T71	2		T72	3		T73	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T72	1		T151	1		T149	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T150	1		T154	1		T148	1