Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	951521	1			T6	11		T9	17		T19	3031
auto[1]	10904365	1			T1	3600		T4	7124		T8	95870
auto[2]	720895	1			T6	10		T9	19		T19	1668
auto[3]	10562716	1			T1	3015		T4	4257		T8	95048

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14292766	1			T1	5441		T4	9411		T8	6887
auto[1]	2195854	1			T1	584		T4	948		T8	29384
auto[2]	2223602	1			T1	541		T4	928		T8	29416
auto[3]	4427275	1			T1	49		T4	94		T8	125231

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9206172

1

T1

6615

T4

11381

T8

43

auto[1]

13933325

1

T8

190875

T12

5

T70

4

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	332412	1			T6	9		T9	16		T19	2483
auto[0]	auto[0]	auto[1]	34477	1			T6	1		T9	1		T19	267
auto[0]	auto[0]	auto[2]	34705	1			T6	1		T19	251		T93	31
auto[0]	auto[0]	auto[3]	70963	1			T19	30		T93	4187		T41	2
auto[0]	auto[1]	auto[0]	3286367	1			T1	2956		T4	5917		T8	2
auto[0]	auto[1]	auto[1]	343437	1			T1	313		T4	580		T12	3876
auto[0]	auto[1]	auto[2]	356875	1			T1	300		T4	575		T8	15
auto[0]	auto[1]	auto[3]	333165	1			T1	31		T4	52		T8	8
auto[0]	auto[2]	auto[0]	234206	1			T6	10		T9	16		T19	1398
auto[0]	auto[2]	auto[1]	28697	1			T9	1		T19	139		T93	327
auto[0]	auto[2]	auto[2]	29293	1			T9	1		T19	121		T93	21
auto[0]	auto[2]	auto[3]	48371	1			T9	1		T19	10		T93	2612
auto[0]	auto[3]	auto[0]	3095582	1			T1	2485		T4	3494		T12	42233
auto[0]	auto[3]	auto[1]	333310	1			T1	271		T4	368		T8	3
auto[0]	auto[3]	auto[2]	348887	1			T1	241		T4	353		T8	4
auto[0]	auto[3]	auto[3]	295425	1			T1	18		T4	42		T8	11
auto[1]	auto[0]	auto[0]	15754	1			T57	113		T125	81		T126	118
auto[1]	auto[0]	auto[1]	71325	1			T57	504		T125	404		T126	536
auto[1]	auto[0]	auto[2]	71006	1			T57	510		T125	433		T126	554
auto[1]	auto[0]	auto[3]	320879	1			T93	4		T57	2325		T125	1859
auto[1]	auto[1]	auto[0]	3659060	1			T8	3498		T12	1		T122	2653
auto[1]	auto[1]	auto[1]	679529	1			T8	13978		T122	11799		T76	5796
auto[1]	auto[1]	auto[2]	660616	1			T8	15472		T122	11616		T76	6010
auto[1]	auto[1]	auto[3]	1585316	1			T8	62897		T122	52216		T76	622
auto[1]	auto[2]	auto[0]	13216	1			T161	719		T162	418		T137	650
auto[1]	auto[2]	auto[1]	58738	1			T161	3278		T162	1738		T137	2776
auto[1]	auto[2]	auto[2]	55663	1			T57	447		T125	353		T126	464
auto[1]	auto[2]	auto[3]	252711	1			T57	2208		T125	1698		T126	2098
auto[1]	auto[3]	auto[0]	3656169	1			T8	3387		T12	4		T70	1
auto[1]	auto[3]	auto[1]	646341	1			T8	15403		T122	11539		T76	5871
auto[1]	auto[3]	auto[2]	666557	1			T8	13925		T122	11570		T76	5933
auto[1]	auto[3]	auto[3]	1520445	1			T8	62315		T70	3		T122	51723