Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1173120025	222964	0	0
ctrl_regwen_rd_A	1173120025	5107	0	0
exec_rd_A	1173120025	4349	0	0
exec_regwen_rd_A	1173120025	4743	0	0
readback_rd_A	1173120025	3728	0	0
readback_regwen_rd_A	1173120025	3024	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1173120025	222964	0	0
T20	609460	0	0	0
T22	101489	5458	0	0
T23	0	4364	0	0
T24	0	5122	0	0
T44	0	6948	0	0
T47	0	4726	0	0
T51	406537	0	0	0
T52	1018	0	0	0
T53	799	0	0	0
T54	71337	0	0	0
T55	286543	0	0	0
T56	422447	0	0	0
T57	119777	0	0	0
T58	929	0	0	0
T59	0	7796	0	0
T60	0	6371	0	0
T81	0	2052	0	0
T82	0	5963	0	0
T83	0	6861	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1173120025	5107	0	0
T47	0	214	0	0
T81	61016	226	0	0
T129	0	104	0	0
T130	0	55	0	0
T131	0	62	0	0
T132	0	84	0	0
T133	0	122	0	0
T134	0	74	0	0
T135	0	507	0	0
T136	0	217	0	0
T137	136715	0	0	0
T138	973546	0	0	0
T139	34039	0	0	0
T140	351137	0	0	0
T141	887193	0	0	0
T142	103213	0	0	0
T143	498514	0	0	0
T144	131012	0	0	0
T145	207855	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1173120025	4349	0	0
T47	0	190	0	0
T81	61016	181	0	0
T129	0	100	0	0
T130	0	65	0	0
T131	0	55	0	0
T132	0	78	0	0
T133	0	198	0	0
T134	0	85	0	0
T135	0	400	0	0
T136	0	181	0	0
T137	136715	0	0	0
T138	973546	0	0	0
T139	34039	0	0	0
T140	351137	0	0	0
T141	887193	0	0	0
T142	103213	0	0	0
T143	498514	0	0	0
T144	131012	0	0	0
T145	207855	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1173120025	4743	0	0
T47	0	178	0	0
T81	61016	190	0	0
T129	0	110	0	0
T130	0	50	0	0
T131	0	60	0	0
T132	0	112	0	0
T133	0	113	0	0
T134	0	113	0	0
T135	0	390	0	0
T136	0	221	0	0
T137	136715	0	0	0
T138	973546	0	0	0
T139	34039	0	0	0
T140	351137	0	0	0
T141	887193	0	0	0
T142	103213	0	0	0
T143	498514	0	0	0
T144	131012	0	0	0
T145	207855	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1173120025	3728	0	0
T47	0	256	0	0
T81	61016	152	0	0
T129	0	90	0	0
T130	0	68	0	0
T131	0	30	0	0
T132	0	93	0	0
T133	0	127	0	0
T134	0	97	0	0
T135	0	320	0	0
T136	0	263	0	0
T137	136715	0	0	0
T138	973546	0	0	0
T139	34039	0	0	0
T140	351137	0	0	0
T141	887193	0	0	0
T142	103213	0	0	0
T143	498514	0	0	0
T144	131012	0	0	0
T145	207855	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1173120025	3024	0	0
T47	0	177	0	0
T81	61016	151	0	0
T129	0	115	0	0
T130	0	45	0	0
T131	0	50	0	0
T132	0	73	0	0
T133	0	135	0	0
T134	0	104	0	0
T135	0	270	0	0
T136	0	147	0	0
T137	136715	0	0	0
T138	973546	0	0	0
T139	34039	0	0	0
T140	351137	0	0	0
T141	887193	0	0	0
T142	103213	0	0	0
T143	498514	0	0	0
T144	131012	0	0	0
T145	207855	0	0	0