| T310 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.3806404077 |
|
|
Aug 25 04:39:37 AM UTC 24 |
Aug 25 04:39:57 AM UTC 24 |
724100447 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.2071465866 |
|
|
Aug 25 04:39:57 AM UTC 24 |
Aug 25 04:40:03 AM UTC 24 |
1256981868 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.4015445146 |
|
|
Aug 25 04:36:51 AM UTC 24 |
Aug 25 04:40:16 AM UTC 24 |
8132551131 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.1102194981 |
|
|
Aug 25 04:36:08 AM UTC 24 |
Aug 25 04:40:18 AM UTC 24 |
10237270296 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.1190879700 |
|
|
Aug 25 04:39:37 AM UTC 24 |
Aug 25 04:40:24 AM UTC 24 |
4357288760 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.3789397473 |
|
|
Aug 25 04:17:13 AM UTC 24 |
Aug 25 04:40:25 AM UTC 24 |
34674850766 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_alert_test.1428037919 |
|
|
Aug 25 04:40:27 AM UTC 24 |
Aug 25 04:40:29 AM UTC 24 |
38489401 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.4140550708 |
|
|
Aug 25 04:29:49 AM UTC 24 |
Aug 25 04:40:35 AM UTC 24 |
75265492151 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.1684972811 |
|
|
Aug 25 04:20:13 AM UTC 24 |
Aug 25 04:40:36 AM UTC 24 |
19797673008 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.1047735720 |
|
|
Aug 25 04:36:57 AM UTC 24 |
Aug 25 04:40:37 AM UTC 24 |
20942302091 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.1779272059 |
|
|
Aug 25 04:31:50 AM UTC 24 |
Aug 25 04:40:51 AM UTC 24 |
6302575267 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_regwen.497261516 |
|
|
Aug 25 04:27:37 AM UTC 24 |
Aug 25 04:40:57 AM UTC 24 |
47379929756 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access.90032476 |
|
|
Aug 25 04:40:51 AM UTC 24 |
Aug 25 04:40:59 AM UTC 24 |
706800092 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.2609106250 |
|
|
Aug 25 04:36:04 AM UTC 24 |
Aug 25 04:41:02 AM UTC 24 |
4149265242 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.2489877011 |
|
|
Aug 25 04:17:03 AM UTC 24 |
Aug 25 04:41:05 AM UTC 24 |
16705339347 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.3933721796 |
|
|
Aug 25 04:22:11 AM UTC 24 |
Aug 25 04:41:05 AM UTC 24 |
39961705870 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.3295625163 |
|
|
Aug 25 04:34:06 AM UTC 24 |
Aug 25 04:41:13 AM UTC 24 |
5357206542 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.1036374367 |
|
|
Aug 25 04:41:03 AM UTC 24 |
Aug 25 04:41:19 AM UTC 24 |
686684353 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_smoke.3239711568 |
|
|
Aug 25 04:40:30 AM UTC 24 |
Aug 25 04:41:22 AM UTC 24 |
736050675 ps |
| T50 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3456730332 |
|
|
Aug 25 04:40:18 AM UTC 24 |
Aug 25 04:41:27 AM UTC 24 |
1264336525 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.3765127359 |
|
|
Aug 25 04:41:23 AM UTC 24 |
Aug 25 04:41:29 AM UTC 24 |
344423009 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.1625652542 |
|
|
Aug 25 04:34:21 AM UTC 24 |
Aug 25 04:41:31 AM UTC 24 |
24440151907 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.1891061075 |
|
|
Aug 25 04:40:59 AM UTC 24 |
Aug 25 04:41:36 AM UTC 24 |
1444199295 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.3309468206 |
|
|
Aug 25 04:28:17 AM UTC 24 |
Aug 25 04:41:45 AM UTC 24 |
44530338462 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_alert_test.958110824 |
|
|
Aug 25 04:41:45 AM UTC 24 |
Aug 25 04:41:47 AM UTC 24 |
13374013 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.3755361064 |
|
|
Aug 25 04:30:08 AM UTC 24 |
Aug 25 04:42:22 AM UTC 24 |
9800524091 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_smoke.1547577188 |
|
|
Aug 25 04:41:48 AM UTC 24 |
Aug 25 04:42:23 AM UTC 24 |
1628918175 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_executable.1796831342 |
|
|
Aug 25 04:32:09 AM UTC 24 |
Aug 25 04:42:27 AM UTC 24 |
29710327543 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_bijection.3255747007 |
|
|
Aug 25 04:26:29 AM UTC 24 |
Aug 25 04:42:42 AM UTC 24 |
64957352969 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.2420207556 |
|
|
Aug 25 04:25:47 AM UTC 24 |
Aug 25 04:42:49 AM UTC 24 |
15036292066 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.229254693 |
|
|
Aug 25 04:41:06 AM UTC 24 |
Aug 25 04:42:51 AM UTC 24 |
9928942889 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1522552636 |
|
|
Aug 25 04:41:32 AM UTC 24 |
Aug 25 04:43:01 AM UTC 24 |
5838803824 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.2831765066 |
|
|
Aug 25 04:21:20 AM UTC 24 |
Aug 25 04:43:07 AM UTC 24 |
37432491171 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.14972405 |
|
|
Aug 25 04:42:52 AM UTC 24 |
Aug 25 04:43:08 AM UTC 24 |
4254142991 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.1247170160 |
|
|
Aug 25 04:35:14 AM UTC 24 |
Aug 25 04:43:23 AM UTC 24 |
17976259271 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.2367833741 |
|
|
Aug 25 04:23:59 AM UTC 24 |
Aug 25 04:43:40 AM UTC 24 |
69800701038 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access.3594131253 |
|
|
Aug 25 04:42:43 AM UTC 24 |
Aug 25 04:43:43 AM UTC 24 |
1851950921 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.4165422281 |
|
|
Aug 25 04:34:43 AM UTC 24 |
Aug 25 04:43:45 AM UTC 24 |
19386226410 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.1034314144 |
|
|
Aug 25 04:43:01 AM UTC 24 |
Aug 25 04:43:49 AM UTC 24 |
2928426555 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.2501056448 |
|
|
Aug 25 04:43:44 AM UTC 24 |
Aug 25 04:43:52 AM UTC 24 |
1406757340 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.246557499 |
|
|
Aug 25 04:40:16 AM UTC 24 |
Aug 25 04:44:01 AM UTC 24 |
4621787522 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.220077638 |
|
|
Aug 25 04:41:29 AM UTC 24 |
Aug 25 04:44:36 AM UTC 24 |
14449020435 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_alert_test.1641180109 |
|
|
Aug 25 04:44:38 AM UTC 24 |
Aug 25 04:44:39 AM UTC 24 |
19621382 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_smoke.3404419591 |
|
|
Aug 25 04:44:41 AM UTC 24 |
Aug 25 04:44:53 AM UTC 24 |
1568855984 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_executable.1802590263 |
|
|
Aug 25 04:27:35 AM UTC 24 |
Aug 25 04:44:54 AM UTC 24 |
20021905886 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_regwen.1339641123 |
|
|
Aug 25 04:32:11 AM UTC 24 |
Aug 25 04:45:00 AM UTC 24 |
2269182156 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.1966924512 |
|
|
Aug 25 04:41:27 AM UTC 24 |
Aug 25 04:45:05 AM UTC 24 |
7133969460 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.3737808225 |
|
|
Aug 25 04:39:01 AM UTC 24 |
Aug 25 04:45:12 AM UTC 24 |
31066802914 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.2028020169 |
|
|
Aug 25 04:23:12 AM UTC 24 |
Aug 25 04:45:13 AM UTC 24 |
131350736296 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.1260941328 |
|
|
Aug 25 04:40:04 AM UTC 24 |
Aug 25 04:45:30 AM UTC 24 |
7881458396 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.502391746 |
|
|
Aug 25 04:43:51 AM UTC 24 |
Aug 25 04:45:37 AM UTC 24 |
2843689078 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_regwen.3919517700 |
|
|
Aug 25 04:24:36 AM UTC 24 |
Aug 25 04:45:41 AM UTC 24 |
13575173244 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.1514665382 |
|
|
Aug 25 04:45:14 AM UTC 24 |
Aug 25 04:45:41 AM UTC 24 |
707173565 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.2517441314 |
|
|
Aug 25 04:24:34 AM UTC 24 |
Aug 25 04:45:45 AM UTC 24 |
6778927669 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.3577578721 |
|
|
Aug 25 04:26:23 AM UTC 24 |
Aug 25 04:45:47 AM UTC 24 |
157578662793 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.1063377946 |
|
|
Aug 25 04:40:36 AM UTC 24 |
Aug 25 04:45:48 AM UTC 24 |
32217680233 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access.2294921717 |
|
|
Aug 25 04:45:06 AM UTC 24 |
Aug 25 04:45:50 AM UTC 24 |
8149034944 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1605883535 |
|
|
Aug 25 04:43:52 AM UTC 24 |
Aug 25 04:45:53 AM UTC 24 |
1384840687 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.705587209 |
|
|
Aug 25 04:45:48 AM UTC 24 |
Aug 25 04:45:54 AM UTC 24 |
373838321 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.530313552 |
|
|
Aug 25 04:43:07 AM UTC 24 |
Aug 25 04:45:59 AM UTC 24 |
53792973364 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_alert_test.1142613661 |
|
|
Aug 25 04:46:00 AM UTC 24 |
Aug 25 04:46:02 AM UTC 24 |
23617866 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.509496910 |
|
|
Aug 25 04:40:58 AM UTC 24 |
Aug 25 04:46:05 AM UTC 24 |
24497860222 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.874725379 |
|
|
Aug 25 04:22:12 AM UTC 24 |
Aug 25 04:46:07 AM UTC 24 |
169275968025 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_regwen.2263914193 |
|
|
Aug 25 04:36:42 AM UTC 24 |
Aug 25 04:46:52 AM UTC 24 |
18270500217 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_bijection.3392665631 |
|
|
Aug 25 04:24:13 AM UTC 24 |
Aug 25 04:46:59 AM UTC 24 |
86791735437 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.523455157 |
|
|
Aug 25 04:45:37 AM UTC 24 |
Aug 25 04:47:05 AM UTC 24 |
20189404941 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.3161375935 |
|
|
Aug 25 04:45:31 AM UTC 24 |
Aug 25 04:47:16 AM UTC 24 |
807071406 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access.331935650 |
|
|
Aug 25 04:47:00 AM UTC 24 |
Aug 25 04:47:17 AM UTC 24 |
757448018 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.280390687 |
|
|
Aug 25 04:45:50 AM UTC 24 |
Aug 25 04:47:20 AM UTC 24 |
4834234973 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.1655688709 |
|
|
Aug 25 04:23:07 AM UTC 24 |
Aug 25 04:47:20 AM UTC 24 |
135729813841 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_bijection.117366187 |
|
|
Aug 25 04:28:02 AM UTC 24 |
Aug 25 04:47:37 AM UTC 24 |
16019518659 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.2939933368 |
|
|
Aug 25 04:19:41 AM UTC 24 |
Aug 25 04:47:54 AM UTC 24 |
29463218364 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.31968932 |
|
|
Aug 25 04:40:38 AM UTC 24 |
Aug 25 04:48:00 AM UTC 24 |
5012034788 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_executable.4076573349 |
|
|
Aug 25 04:36:38 AM UTC 24 |
Aug 25 04:48:03 AM UTC 24 |
6922111048 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.3295101516 |
|
|
Aug 25 04:48:02 AM UTC 24 |
Aug 25 04:48:09 AM UTC 24 |
825245632 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.1869474175 |
|
|
Aug 25 04:47:16 AM UTC 24 |
Aug 25 04:48:09 AM UTC 24 |
756369653 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.2755880015 |
|
|
Aug 25 04:47:17 AM UTC 24 |
Aug 25 04:48:13 AM UTC 24 |
766434273 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_regwen.4012975960 |
|
|
Aug 25 04:35:05 AM UTC 24 |
Aug 25 04:48:13 AM UTC 24 |
1957697882 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.16471524 |
|
|
Aug 25 04:27:58 AM UTC 24 |
Aug 25 04:48:15 AM UTC 24 |
9714260052 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_alert_test.1595536121 |
|
|
Aug 25 04:48:14 AM UTC 24 |
Aug 25 04:48:16 AM UTC 24 |
32634886 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_smoke.2509259477 |
|
|
Aug 25 04:46:03 AM UTC 24 |
Aug 25 04:48:20 AM UTC 24 |
984032953 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2567336105 |
|
|
Aug 25 04:45:53 AM UTC 24 |
Aug 25 04:48:26 AM UTC 24 |
22029473503 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_smoke.4089546586 |
|
|
Aug 25 04:48:15 AM UTC 24 |
Aug 25 04:48:29 AM UTC 24 |
1656997344 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.3933996191 |
|
|
Aug 25 04:42:28 AM UTC 24 |
Aug 25 04:48:34 AM UTC 24 |
13891410145 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access.674777447 |
|
|
Aug 25 04:48:30 AM UTC 24 |
Aug 25 04:48:37 AM UTC 24 |
508391062 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.200665654 |
|
|
Aug 25 04:48:10 AM UTC 24 |
Aug 25 04:49:03 AM UTC 24 |
6945151608 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.865834812 |
|
|
Aug 25 04:37:31 AM UTC 24 |
Aug 25 04:49:04 AM UTC 24 |
6287451301 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_executable.3337206217 |
|
|
Aug 25 04:28:40 AM UTC 24 |
Aug 25 04:49:11 AM UTC 24 |
7865050009 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_regwen.1984790052 |
|
|
Aug 25 04:39:49 AM UTC 24 |
Aug 25 04:49:12 AM UTC 24 |
22116805000 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.1280219663 |
|
|
Aug 25 04:41:06 AM UTC 24 |
Aug 25 04:49:18 AM UTC 24 |
17693313324 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_bijection.3899887241 |
|
|
Aug 25 04:35:47 AM UTC 24 |
Aug 25 04:49:34 AM UTC 24 |
9617157429 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.1623945296 |
|
|
Aug 25 04:48:10 AM UTC 24 |
Aug 25 04:49:35 AM UTC 24 |
1917455570 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.2673488356 |
|
|
Aug 25 04:49:35 AM UTC 24 |
Aug 25 04:49:43 AM UTC 24 |
1350830189 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.3556091912 |
|
|
Aug 25 04:49:04 AM UTC 24 |
Aug 25 04:49:47 AM UTC 24 |
1481511651 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.2969985802 |
|
|
Aug 25 04:47:21 AM UTC 24 |
Aug 25 04:49:50 AM UTC 24 |
51541421107 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.3055384468 |
|
|
Aug 25 04:18:57 AM UTC 24 |
Aug 25 04:49:53 AM UTC 24 |
86370760503 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_alert_test.1048527475 |
|
|
Aug 25 04:49:54 AM UTC 24 |
Aug 25 04:49:56 AM UTC 24 |
36512307 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.3706554251 |
|
|
Aug 25 04:49:05 AM UTC 24 |
Aug 25 04:50:16 AM UTC 24 |
20026349579 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.172190499 |
|
|
Aug 25 04:20:58 AM UTC 24 |
Aug 25 04:50:19 AM UTC 24 |
83331697851 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.1203914413 |
|
|
Aug 25 04:43:46 AM UTC 24 |
Aug 25 04:50:32 AM UTC 24 |
27694249510 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.1859364220 |
|
|
Aug 25 04:19:24 AM UTC 24 |
Aug 25 04:50:35 AM UTC 24 |
39066723992 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_regwen.2226881514 |
|
|
Aug 25 04:41:20 AM UTC 24 |
Aug 25 04:50:36 AM UTC 24 |
14857783023 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.591099264 |
|
|
Aug 25 04:29:16 AM UTC 24 |
Aug 25 04:50:37 AM UTC 24 |
29012274063 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.3179682706 |
|
|
Aug 25 04:45:01 AM UTC 24 |
Aug 25 04:50:42 AM UTC 24 |
4824042015 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access.2554675882 |
|
|
Aug 25 04:50:36 AM UTC 24 |
Aug 25 04:50:46 AM UTC 24 |
807123303 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.58517576 |
|
|
Aug 25 04:50:39 AM UTC 24 |
Aug 25 04:50:49 AM UTC 24 |
684746934 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.1954130941 |
|
|
Aug 25 04:48:39 AM UTC 24 |
Aug 25 04:50:50 AM UTC 24 |
841068583 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.2411521162 |
|
|
Aug 25 04:45:13 AM UTC 24 |
Aug 25 04:50:54 AM UTC 24 |
16425449721 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.2469681674 |
|
|
Aug 25 04:50:43 AM UTC 24 |
Aug 25 04:51:02 AM UTC 24 |
2395587725 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.1793903332 |
|
|
Aug 25 04:51:02 AM UTC 24 |
Aug 25 04:51:11 AM UTC 24 |
2099528504 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.708951810 |
|
|
Aug 25 04:19:38 AM UTC 24 |
Aug 25 04:51:11 AM UTC 24 |
33801443777 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.3905460354 |
|
|
Aug 25 04:45:49 AM UTC 24 |
Aug 25 04:51:16 AM UTC 24 |
3947679828 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.1446203619 |
|
|
Aug 25 04:27:23 AM UTC 24 |
Aug 25 04:51:28 AM UTC 24 |
15950918388 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.2179670025 |
|
|
Aug 25 04:49:44 AM UTC 24 |
Aug 25 04:51:29 AM UTC 24 |
5563986904 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.2523887041 |
|
|
Aug 25 04:44:54 AM UTC 24 |
Aug 25 04:51:31 AM UTC 24 |
6381150825 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_alert_test.2757628603 |
|
|
Aug 25 04:51:31 AM UTC 24 |
Aug 25 04:51:33 AM UTC 24 |
15148531 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.1032936397 |
|
|
Aug 25 04:18:39 AM UTC 24 |
Aug 25 04:51:33 AM UTC 24 |
21713649828 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1134336197 |
|
|
Aug 25 04:49:48 AM UTC 24 |
Aug 25 04:51:33 AM UTC 24 |
2487344449 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_bijection.2962793525 |
|
|
Aug 25 04:18:21 AM UTC 24 |
Aug 25 04:51:37 AM UTC 24 |
83750004345 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_regwen.1910738477 |
|
|
Aug 25 04:45:46 AM UTC 24 |
Aug 25 04:51:37 AM UTC 24 |
16988472218 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.3433111851 |
|
|
Aug 25 04:50:47 AM UTC 24 |
Aug 25 04:51:59 AM UTC 24 |
12879485479 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_smoke.834990606 |
|
|
Aug 25 04:51:32 AM UTC 24 |
Aug 25 04:52:04 AM UTC 24 |
958624474 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.3431326476 |
|
|
Aug 25 04:48:04 AM UTC 24 |
Aug 25 04:52:06 AM UTC 24 |
9077738883 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.898178242 |
|
|
Aug 25 04:42:50 AM UTC 24 |
Aug 25 04:52:12 AM UTC 24 |
169264642511 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_smoke.2507739341 |
|
|
Aug 25 04:49:57 AM UTC 24 |
Aug 25 04:52:13 AM UTC 24 |
3926266896 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_executable.1605792279 |
|
|
Aug 25 04:43:24 AM UTC 24 |
Aug 25 04:52:20 AM UTC 24 |
6722160761 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.1037178617 |
|
|
Aug 25 04:52:00 AM UTC 24 |
Aug 25 04:52:43 AM UTC 24 |
2987311132 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.210623988 |
|
|
Aug 25 04:52:44 AM UTC 24 |
Aug 25 04:52:50 AM UTC 24 |
680333978 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.2085900389 |
|
|
Aug 25 04:51:12 AM UTC 24 |
Aug 25 04:53:02 AM UTC 24 |
9479643002 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_bijection.2401471286 |
|
|
Aug 25 04:31:32 AM UTC 24 |
Aug 25 04:53:16 AM UTC 24 |
264667166044 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_executable.48448902 |
|
|
Aug 25 04:49:13 AM UTC 24 |
Aug 25 04:53:23 AM UTC 24 |
3816520644 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_alert_test.3013615726 |
|
|
Aug 25 04:53:23 AM UTC 24 |
Aug 25 04:53:25 AM UTC 24 |
15618883 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access.2769502080 |
|
|
Aug 25 04:51:38 AM UTC 24 |
Aug 25 04:53:30 AM UTC 24 |
881744774 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_executable.1658803330 |
|
|
Aug 25 04:50:51 AM UTC 24 |
Aug 25 04:53:32 AM UTC 24 |
3191385890 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.4082771428 |
|
|
Aug 25 04:33:57 AM UTC 24 |
Aug 25 04:53:33 AM UTC 24 |
8801140854 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_smoke.3779046547 |
|
|
Aug 25 04:53:26 AM UTC 24 |
Aug 25 04:53:36 AM UTC 24 |
1513243139 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.2153407708 |
|
|
Aug 25 04:52:05 AM UTC 24 |
Aug 25 04:53:49 AM UTC 24 |
1548771600 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.3599607126 |
|
|
Aug 25 04:52:07 AM UTC 24 |
Aug 25 04:53:53 AM UTC 24 |
17666040994 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access.3205725294 |
|
|
Aug 25 04:53:37 AM UTC 24 |
Aug 25 04:54:05 AM UTC 24 |
2440810419 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.267092799 |
|
|
Aug 25 04:53:03 AM UTC 24 |
Aug 25 04:54:10 AM UTC 24 |
2079176009 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.122657485 |
|
|
Aug 25 04:53:54 AM UTC 24 |
Aug 25 04:54:23 AM UTC 24 |
2925203383 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_executable.874981674 |
|
|
Aug 25 04:45:42 AM UTC 24 |
Aug 25 04:54:30 AM UTC 24 |
109887886297 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.687792865 |
|
|
Aug 25 04:53:02 AM UTC 24 |
Aug 25 04:54:37 AM UTC 24 |
5513504266 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.2319490215 |
|
|
Aug 25 04:46:53 AM UTC 24 |
Aug 25 04:54:37 AM UTC 24 |
20591335505 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.2993208732 |
|
|
Aug 25 04:54:39 AM UTC 24 |
Aug 25 04:54:45 AM UTC 24 |
5605524560 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_bijection.3699609151 |
|
|
Aug 25 04:17:52 AM UTC 24 |
Aug 25 04:54:49 AM UTC 24 |
81927653255 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.3629261043 |
|
|
Aug 25 04:49:35 AM UTC 24 |
Aug 25 04:55:02 AM UTC 24 |
15755868446 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.4238447889 |
|
|
Aug 25 04:51:17 AM UTC 24 |
Aug 25 04:55:11 AM UTC 24 |
8893258128 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all.1767872069 |
|
|
Aug 25 04:31:07 AM UTC 24 |
Aug 25 04:55:26 AM UTC 24 |
22015071040 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_alert_test.216240283 |
|
|
Aug 25 04:55:27 AM UTC 24 |
Aug 25 04:55:29 AM UTC 24 |
31441031 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.1462068062 |
|
|
Aug 25 04:31:30 AM UTC 24 |
Aug 25 04:55:40 AM UTC 24 |
18045022320 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.2573803230 |
|
|
Aug 25 04:55:03 AM UTC 24 |
Aug 25 04:55:44 AM UTC 24 |
3473088127 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.1045821757 |
|
|
Aug 25 04:54:06 AM UTC 24 |
Aug 25 04:55:48 AM UTC 24 |
3228715403 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_smoke.889855166 |
|
|
Aug 25 04:55:30 AM UTC 24 |
Aug 25 04:56:05 AM UTC 24 |
1394866560 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access.1766518472 |
|
|
Aug 25 04:56:06 AM UTC 24 |
Aug 25 04:56:34 AM UTC 24 |
1401166118 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.3362649383 |
|
|
Aug 25 04:51:38 AM UTC 24 |
Aug 25 04:56:35 AM UTC 24 |
4219495369 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.918389139 |
|
|
Aug 25 04:54:50 AM UTC 24 |
Aug 25 04:56:39 AM UTC 24 |
19837080187 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_executable.1115581563 |
|
|
Aug 25 04:25:53 AM UTC 24 |
Aug 25 04:56:42 AM UTC 24 |
21131427132 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.3469185224 |
|
|
Aug 25 04:48:26 AM UTC 24 |
Aug 25 04:57:01 AM UTC 24 |
9838719058 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.2069180849 |
|
|
Aug 25 04:48:35 AM UTC 24 |
Aug 25 04:57:05 AM UTC 24 |
72839633127 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.3926686313 |
|
|
Aug 25 04:39:42 AM UTC 24 |
Aug 25 04:57:16 AM UTC 24 |
56926680892 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.2234790589 |
|
|
Aug 25 04:57:16 AM UTC 24 |
Aug 25 04:57:24 AM UTC 24 |
1306313230 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.3707000126 |
|
|
Aug 25 04:56:35 AM UTC 24 |
Aug 25 04:57:25 AM UTC 24 |
2877703860 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.3489017591 |
|
|
Aug 25 04:54:11 AM UTC 24 |
Aug 25 04:57:28 AM UTC 24 |
33393096077 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_bijection.3882457381 |
|
|
Aug 25 04:48:21 AM UTC 24 |
Aug 25 04:57:51 AM UTC 24 |
28708843521 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.130774006 |
|
|
Aug 25 04:56:40 AM UTC 24 |
Aug 25 04:57:52 AM UTC 24 |
13049585966 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.2439238963 |
|
|
Aug 25 04:50:33 AM UTC 24 |
Aug 25 04:57:55 AM UTC 24 |
18986405638 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_alert_test.267297361 |
|
|
Aug 25 04:57:53 AM UTC 24 |
Aug 25 04:57:55 AM UTC 24 |
14123120 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3269258952 |
|
|
Aug 25 04:57:29 AM UTC 24 |
Aug 25 04:58:18 AM UTC 24 |
2610362675 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.250932076 |
|
|
Aug 25 04:51:34 AM UTC 24 |
Aug 25 04:58:19 AM UTC 24 |
28325971698 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_smoke.265961302 |
|
|
Aug 25 04:57:56 AM UTC 24 |
Aug 25 04:58:26 AM UTC 24 |
1244469110 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.63596590 |
|
|
Aug 25 04:53:34 AM UTC 24 |
Aug 25 04:58:29 AM UTC 24 |
3215550262 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.1050618653 |
|
|
Aug 25 04:47:06 AM UTC 24 |
Aug 25 04:58:34 AM UTC 24 |
18562245523 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.2379380701 |
|
|
Aug 25 04:56:35 AM UTC 24 |
Aug 25 04:58:36 AM UTC 24 |
3093761392 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access.452551205 |
|
|
Aug 25 04:58:26 AM UTC 24 |
Aug 25 04:58:48 AM UTC 24 |
1087497731 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.386192210 |
|
|
Aug 25 04:51:11 AM UTC 24 |
Aug 25 04:59:02 AM UTC 24 |
20713907692 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.3864547097 |
|
|
Aug 25 04:58:36 AM UTC 24 |
Aug 25 04:59:03 AM UTC 24 |
5852306786 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.390271020 |
|
|
Aug 25 04:54:46 AM UTC 24 |
Aug 25 04:59:05 AM UTC 24 |
10371249279 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.4017710326 |
|
|
Aug 25 04:57:26 AM UTC 24 |
Aug 25 04:59:16 AM UTC 24 |
1445218256 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.2036446750 |
|
|
Aug 25 04:35:45 AM UTC 24 |
Aug 25 04:59:22 AM UTC 24 |
17767691382 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.3555050817 |
|
|
Aug 25 04:59:17 AM UTC 24 |
Aug 25 04:59:24 AM UTC 24 |
365473058 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.1455774528 |
|
|
Aug 25 04:50:37 AM UTC 24 |
Aug 25 04:59:33 AM UTC 24 |
16874178391 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.2322044492 |
|
|
Aug 25 04:58:38 AM UTC 24 |
Aug 25 04:59:40 AM UTC 24 |
3072156834 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_executable.3063456867 |
|
|
Aug 25 04:39:48 AM UTC 24 |
Aug 25 04:59:40 AM UTC 24 |
24540874362 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_alert_test.1884407128 |
|
|
Aug 25 04:59:41 AM UTC 24 |
Aug 25 04:59:43 AM UTC 24 |
26852084 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_regwen.1455664472 |
|
|
Aug 25 04:25:59 AM UTC 24 |
Aug 25 04:59:45 AM UTC 24 |
33191996611 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_smoke.2302933712 |
|
|
Aug 25 04:59:45 AM UTC 24 |
Aug 25 04:59:59 AM UTC 24 |
456599713 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.3399652850 |
|
|
Aug 25 04:59:33 AM UTC 24 |
Aug 25 05:00:00 AM UTC 24 |
1183650012 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.2576077764 |
|
|
Aug 25 04:57:24 AM UTC 24 |
Aug 25 05:00:04 AM UTC 24 |
7317563180 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.154802383 |
|
|
Aug 25 04:59:46 AM UTC 24 |
Aug 25 05:00:10 AM UTC 24 |
1027168150 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_regwen.4086819043 |
|
|
Aug 25 04:43:41 AM UTC 24 |
Aug 25 05:00:11 AM UTC 24 |
18497983869 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_bijection.2381271849 |
|
|
Aug 25 04:42:25 AM UTC 24 |
Aug 25 05:00:15 AM UTC 24 |
12796167326 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.3089291184 |
|
|
Aug 25 04:52:51 AM UTC 24 |
Aug 25 05:00:20 AM UTC 24 |
14425848116 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_regwen.578243852 |
|
|
Aug 25 04:57:05 AM UTC 24 |
Aug 25 05:00:22 AM UTC 24 |
3572197861 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.964720400 |
|
|
Aug 25 05:00:12 AM UTC 24 |
Aug 25 05:00:25 AM UTC 24 |
3516059206 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access.1902636562 |
|
|
Aug 25 05:00:07 AM UTC 24 |
Aug 25 05:00:37 AM UTC 24 |
425821900 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_executable.3643846470 |
|
|
Aug 25 04:35:03 AM UTC 24 |
Aug 25 05:00:38 AM UTC 24 |
84648952247 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.1452346991 |
|
|
Aug 25 05:00:39 AM UTC 24 |
Aug 25 05:00:46 AM UTC 24 |
367872485 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.4276280222 |
|
|
Aug 25 04:58:50 AM UTC 24 |
Aug 25 05:00:47 AM UTC 24 |
64571621815 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.3568554107 |
|
|
Aug 25 04:36:37 AM UTC 24 |
Aug 25 05:01:01 AM UTC 24 |
14743646834 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.2939253759 |
|
|
Aug 25 04:42:23 AM UTC 24 |
Aug 25 05:01:04 AM UTC 24 |
65537013765 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.1667549995 |
|
|
Aug 25 05:00:16 AM UTC 24 |
Aug 25 05:01:19 AM UTC 24 |
782966306 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_alert_test.3413128279 |
|
|
Aug 25 05:01:20 AM UTC 24 |
Aug 25 05:01:22 AM UTC 24 |
26056586 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2154130143 |
|
|
Aug 25 05:01:02 AM UTC 24 |
Aug 25 05:01:24 AM UTC 24 |
654227579 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.2336289464 |
|
|
Aug 25 04:55:48 AM UTC 24 |
Aug 25 05:01:32 AM UTC 24 |
16160879110 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.3991407220 |
|
|
Aug 25 04:58:20 AM UTC 24 |
Aug 25 05:01:46 AM UTC 24 |
2630664498 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_smoke.3492122111 |
|
|
Aug 25 05:01:23 AM UTC 24 |
Aug 25 05:01:53 AM UTC 24 |
626106729 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.1918446382 |
|
|
Aug 25 05:00:21 AM UTC 24 |
Aug 25 05:01:54 AM UTC 24 |
30612907013 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access.4062008093 |
|
|
Aug 25 05:01:54 AM UTC 24 |
Aug 25 05:02:06 AM UTC 24 |
502821939 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.3625081459 |
|
|
Aug 25 04:59:25 AM UTC 24 |
Aug 25 05:02:13 AM UTC 24 |
6619929225 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.2161371238 |
|
|
Aug 25 04:43:08 AM UTC 24 |
Aug 25 05:02:18 AM UTC 24 |
12121348236 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_regwen.4144668146 |
|
|
Aug 25 04:49:19 AM UTC 24 |
Aug 25 05:02:20 AM UTC 24 |
24651402596 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.817710767 |
|
|
Aug 25 04:46:06 AM UTC 24 |
Aug 25 05:02:24 AM UTC 24 |
30514521105 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_executable.3481016952 |
|
|
Aug 25 04:41:14 AM UTC 24 |
Aug 25 05:02:38 AM UTC 24 |
17995051670 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.1093678520 |
|
|
Aug 25 05:02:14 AM UTC 24 |
Aug 25 05:02:44 AM UTC 24 |
2991652756 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.535555803 |
|
|
Aug 25 04:52:13 AM UTC 24 |
Aug 25 05:02:48 AM UTC 24 |
37528410655 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.1983668090 |
|
|
Aug 25 05:02:45 AM UTC 24 |
Aug 25 05:02:51 AM UTC 24 |
1054263777 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_regwen.3742480592 |
|
|
Aug 25 04:59:06 AM UTC 24 |
Aug 25 05:03:23 AM UTC 24 |
1067702043 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_bijection.827499198 |
|
|
Aug 25 04:34:05 AM UTC 24 |
Aug 25 05:03:25 AM UTC 24 |
39240279663 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.1825460174 |
|
|
Aug 25 05:02:07 AM UTC 24 |
Aug 25 05:03:32 AM UTC 24 |
2961027378 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.3930442203 |
|
|
Aug 25 05:00:48 AM UTC 24 |
Aug 25 05:03:34 AM UTC 24 |
1600819984 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_alert_test.1585696363 |
|
|
Aug 25 05:03:33 AM UTC 24 |
Aug 25 05:03:35 AM UTC 24 |
49101722 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.2676916806 |
|
|
Aug 25 04:56:25 AM UTC 24 |
Aug 25 05:03:45 AM UTC 24 |
15026274154 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_smoke.402658375 |
|
|
Aug 25 05:03:35 AM UTC 24 |
Aug 25 05:03:50 AM UTC 24 |
1760951502 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.3513314854 |
|
|
Aug 25 04:48:17 AM UTC 24 |
Aug 25 05:03:52 AM UTC 24 |
22840454319 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.4143023016 |
|
|
Aug 25 05:01:47 AM UTC 24 |
Aug 25 05:03:54 AM UTC 24 |
2218582442 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.3132259843 |
|
|
Aug 25 05:02:19 AM UTC 24 |
Aug 25 05:03:55 AM UTC 24 |
74293334349 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.2582362010 |
|
|
Aug 25 04:49:12 AM UTC 24 |
Aug 25 05:04:04 AM UTC 24 |
54137289491 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access.1607322725 |
|
|
Aug 25 05:03:53 AM UTC 24 |
Aug 25 05:04:21 AM UTC 24 |
1506773418 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.243499094 |
|
|
Aug 25 04:58:29 AM UTC 24 |
Aug 25 05:04:35 AM UTC 24 |
49597282063 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.3303839144 |
|
|
Aug 25 05:02:52 AM UTC 24 |
Aug 25 05:04:36 AM UTC 24 |
6043937331 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.4039174582 |
|
|
Aug 25 04:53:50 AM UTC 24 |
Aug 25 05:04:42 AM UTC 24 |
21113398628 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.4056955452 |
|
|
Aug 25 05:00:47 AM UTC 24 |
Aug 25 05:04:47 AM UTC 24 |
7068404855 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.2568314765 |
|
|
Aug 25 05:04:05 AM UTC 24 |
Aug 25 05:04:49 AM UTC 24 |
764241477 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.469997878 |
|
|
Aug 25 05:04:48 AM UTC 24 |
Aug 25 05:04:59 AM UTC 24 |
5616714956 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.3051543705 |
|
|
Aug 25 05:03:55 AM UTC 24 |
Aug 25 05:05:04 AM UTC 24 |
5644292184 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_regwen.4135501789 |
|
|
Aug 25 04:28:41 AM UTC 24 |
Aug 25 05:05:19 AM UTC 24 |
74967704159 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.403925616 |
|
|
Aug 25 05:04:22 AM UTC 24 |
Aug 25 05:06:06 AM UTC 24 |
10660820455 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_alert_test.717745948 |
|
|
Aug 25 05:06:07 AM UTC 24 |
Aug 25 05:06:09 AM UTC 24 |
35448970 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_bijection.1697213780 |
|
|
Aug 25 04:55:45 AM UTC 24 |
Aug 25 05:06:20 AM UTC 24 |
31311943220 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.179079716 |
|
|
Aug 25 05:05:05 AM UTC 24 |
Aug 25 05:06:26 AM UTC 24 |
1538627380 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.221059672 |
|
|
Aug 25 04:19:42 AM UTC 24 |
Aug 25 05:06:42 AM UTC 24 |
127066983254 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_smoke.891511830 |
|
|
Aug 25 05:06:10 AM UTC 24 |
Aug 25 05:06:44 AM UTC 24 |
3185470953 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_bijection.3533924047 |
|
|
Aug 25 04:17:29 AM UTC 24 |
Aug 25 05:06:50 AM UTC 24 |
98624737371 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.3129693264 |
|
|
Aug 25 04:59:22 AM UTC 24 |
Aug 25 05:07:03 AM UTC 24 |
103445205501 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access.1591315773 |
|
|
Aug 25 05:06:44 AM UTC 24 |
Aug 25 05:07:06 AM UTC 24 |
541302863 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_bijection.56746738 |
|
|
Aug 25 04:37:29 AM UTC 24 |
Aug 25 05:07:06 AM UTC 24 |
76831164792 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_executable.2703060191 |
|
|
Aug 25 04:30:11 AM UTC 24 |
Aug 25 05:07:11 AM UTC 24 |
28226362835 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.356311134 |
|
|
Aug 25 05:07:04 AM UTC 24 |
Aug 25 05:07:13 AM UTC 24 |
704515494 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.3595288891 |
|
|
Aug 25 05:03:50 AM UTC 24 |
Aug 25 05:07:14 AM UTC 24 |
2894921715 ps |