| T798 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.4106070961 |
|
|
Aug 25 05:37:11 AM UTC 24 |
Aug 25 05:38:08 AM UTC 24 |
1489041642 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.2573413661 |
|
|
Aug 25 05:30:16 AM UTC 24 |
Aug 25 05:38:10 AM UTC 24 |
5774616512 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.2800816304 |
|
|
Aug 25 05:28:51 AM UTC 24 |
Aug 25 05:38:23 AM UTC 24 |
64684940571 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.2313535608 |
|
|
Aug 25 05:38:12 AM UTC 24 |
Aug 25 05:38:23 AM UTC 24 |
6727929143 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_executable.690879745 |
|
|
Aug 25 05:13:48 AM UTC 24 |
Aug 25 05:38:33 AM UTC 24 |
7322580677 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.658490504 |
|
|
Aug 25 05:37:22 AM UTC 24 |
Aug 25 05:38:37 AM UTC 24 |
25914013651 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_bijection.4241489868 |
|
|
Aug 25 05:00:00 AM UTC 24 |
Aug 25 05:38:43 AM UTC 24 |
27669122924 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_bijection.1279054853 |
|
|
Aug 25 05:16:57 AM UTC 24 |
Aug 25 05:38:43 AM UTC 24 |
230827057928 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.2935306289 |
|
|
Aug 25 05:06:21 AM UTC 24 |
Aug 25 05:38:45 AM UTC 24 |
130475011309 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_alert_test.1904848480 |
|
|
Aug 25 05:38:44 AM UTC 24 |
Aug 25 05:38:47 AM UTC 24 |
12235668 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.3940229806 |
|
|
Aug 25 05:29:19 AM UTC 24 |
Aug 25 05:38:53 AM UTC 24 |
7389929357 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_smoke.2168922929 |
|
|
Aug 25 05:38:44 AM UTC 24 |
Aug 25 05:38:56 AM UTC 24 |
863806843 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.322208827 |
|
|
Aug 25 05:38:33 AM UTC 24 |
Aug 25 05:38:57 AM UTC 24 |
1062309772 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.2757553522 |
|
|
Aug 25 05:37:18 AM UTC 24 |
Aug 25 05:39:02 AM UTC 24 |
3218379380 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.4262137257 |
|
|
Aug 25 05:34:53 AM UTC 24 |
Aug 25 05:39:04 AM UTC 24 |
2527263759 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_bijection.3107034816 |
|
|
Aug 25 05:12:11 AM UTC 24 |
Aug 25 05:39:04 AM UTC 24 |
22348476548 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access.2705317259 |
|
|
Aug 25 05:38:57 AM UTC 24 |
Aug 25 05:39:09 AM UTC 24 |
1672082873 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.2598533877 |
|
|
Aug 25 05:39:05 AM UTC 24 |
Aug 25 05:39:18 AM UTC 24 |
1402641777 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.3682280970 |
|
|
Aug 25 05:14:52 AM UTC 24 |
Aug 25 05:39:24 AM UTC 24 |
13538034311 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_regwen.2062173546 |
|
|
Aug 25 05:29:23 AM UTC 24 |
Aug 25 05:39:27 AM UTC 24 |
5249875178 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.3907384668 |
|
|
Aug 25 05:24:11 AM UTC 24 |
Aug 25 05:39:27 AM UTC 24 |
10618150070 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.1728178544 |
|
|
Aug 25 05:39:27 AM UTC 24 |
Aug 25 05:39:34 AM UTC 24 |
362176223 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access.1010374607 |
|
|
Aug 25 05:37:08 AM UTC 24 |
Aug 25 05:39:36 AM UTC 24 |
1999003738 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.109739846 |
|
|
Aug 25 05:36:03 AM UTC 24 |
Aug 25 05:39:37 AM UTC 24 |
4523253623 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.1530480885 |
|
|
Aug 25 05:36:00 AM UTC 24 |
Aug 25 05:39:41 AM UTC 24 |
9379779579 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.4030695513 |
|
|
Aug 25 05:25:25 AM UTC 24 |
Aug 25 05:39:42 AM UTC 24 |
12623500944 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_alert_test.2119970790 |
|
|
Aug 25 05:39:42 AM UTC 24 |
Aug 25 05:39:44 AM UTC 24 |
14839752 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.2667436200 |
|
|
Aug 25 05:31:38 AM UTC 24 |
Aug 25 05:39:55 AM UTC 24 |
71329917133 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_smoke.2473410453 |
|
|
Aug 25 05:39:43 AM UTC 24 |
Aug 25 05:39:57 AM UTC 24 |
457387328 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_bijection.4232286296 |
|
|
Aug 25 05:01:33 AM UTC 24 |
Aug 25 05:40:01 AM UTC 24 |
110818307073 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.3349126801 |
|
|
Aug 25 05:39:05 AM UTC 24 |
Aug 25 05:40:08 AM UTC 24 |
6922533774 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access.982230114 |
|
|
Aug 25 05:40:02 AM UTC 24 |
Aug 25 05:40:13 AM UTC 24 |
760101088 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_bijection.108942727 |
|
|
Aug 25 05:23:35 AM UTC 24 |
Aug 25 05:40:15 AM UTC 24 |
10946150581 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.2297683386 |
|
|
Aug 25 05:40:16 AM UTC 24 |
Aug 25 05:40:33 AM UTC 24 |
2628906577 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_executable.2391495449 |
|
|
Aug 25 05:39:19 AM UTC 24 |
Aug 25 05:40:41 AM UTC 24 |
1923432591 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.2163413065 |
|
|
Aug 25 05:39:03 AM UTC 24 |
Aug 25 05:40:45 AM UTC 24 |
769480960 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.1242494094 |
|
|
Aug 25 05:23:31 AM UTC 24 |
Aug 25 05:40:56 AM UTC 24 |
34823499753 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.2064358816 |
|
|
Aug 25 05:39:36 AM UTC 24 |
Aug 25 05:41:06 AM UTC 24 |
2840638334 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.718507025 |
|
|
Aug 25 05:41:07 AM UTC 24 |
Aug 25 05:41:14 AM UTC 24 |
1595026342 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.42480802 |
|
|
Aug 25 05:39:38 AM UTC 24 |
Aug 25 05:41:20 AM UTC 24 |
6023956213 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_executable.4141092308 |
|
|
Aug 25 05:33:41 AM UTC 24 |
Aug 25 05:41:23 AM UTC 24 |
8108374602 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all.1841265194 |
|
|
Aug 25 04:57:52 AM UTC 24 |
Aug 25 05:41:31 AM UTC 24 |
268243062510 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.146642317 |
|
|
Aug 25 05:40:14 AM UTC 24 |
Aug 25 05:41:32 AM UTC 24 |
792983707 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_alert_test.4262009514 |
|
|
Aug 25 05:41:32 AM UTC 24 |
Aug 25 05:41:34 AM UTC 24 |
137658128 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.2587333187 |
|
|
Aug 25 05:40:34 AM UTC 24 |
Aug 25 05:41:37 AM UTC 24 |
22888456191 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.1353822522 |
|
|
Aug 25 05:36:42 AM UTC 24 |
Aug 25 05:41:46 AM UTC 24 |
3406663423 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.1246880813 |
|
|
Aug 25 05:35:00 AM UTC 24 |
Aug 25 05:41:48 AM UTC 24 |
55801214464 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.2219961888 |
|
|
Aug 25 05:38:24 AM UTC 24 |
Aug 25 05:42:00 AM UTC 24 |
2690022821 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_smoke.1646216773 |
|
|
Aug 25 05:41:35 AM UTC 24 |
Aug 25 05:42:05 AM UTC 24 |
2509149958 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.2539750703 |
|
|
Aug 25 05:38:24 AM UTC 24 |
Aug 25 05:42:11 AM UTC 24 |
5098701490 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.4154906402 |
|
|
Aug 25 05:41:24 AM UTC 24 |
Aug 25 05:42:24 AM UTC 24 |
6894456169 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.2229950821 |
|
|
Aug 25 05:42:12 AM UTC 24 |
Aug 25 05:42:26 AM UTC 24 |
711922235 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.2921951837 |
|
|
Aug 25 05:32:27 AM UTC 24 |
Aug 25 05:42:55 AM UTC 24 |
6173140349 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.1062643209 |
|
|
Aug 25 05:42:27 AM UTC 24 |
Aug 25 05:43:00 AM UTC 24 |
3088317142 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.3585745730 |
|
|
Aug 25 05:18:41 AM UTC 24 |
Aug 25 05:43:10 AM UTC 24 |
23066360261 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access.1829479369 |
|
|
Aug 25 05:42:01 AM UTC 24 |
Aug 25 05:43:55 AM UTC 24 |
1404959121 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.2043169525 |
|
|
Aug 25 05:43:56 AM UTC 24 |
Aug 25 05:44:02 AM UTC 24 |
676665013 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all.4199016847 |
|
|
Aug 25 04:17:10 AM UTC 24 |
Aug 25 05:44:03 AM UTC 24 |
187856405117 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.1666181422 |
|
|
Aug 25 05:41:21 AM UTC 24 |
Aug 25 05:44:06 AM UTC 24 |
6303529928 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_bijection.1381767621 |
|
|
Aug 25 05:03:46 AM UTC 24 |
Aug 25 05:44:16 AM UTC 24 |
431306159560 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.4001330243 |
|
|
Aug 25 05:44:06 AM UTC 24 |
Aug 25 05:44:31 AM UTC 24 |
581379164 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_alert_test.2552490542 |
|
|
Aug 25 05:44:32 AM UTC 24 |
Aug 25 05:44:34 AM UTC 24 |
23546492 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.477981354 |
|
|
Aug 25 05:39:58 AM UTC 24 |
Aug 25 05:44:47 AM UTC 24 |
10563257580 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.1889322800 |
|
|
Aug 25 05:42:25 AM UTC 24 |
Aug 25 05:44:48 AM UTC 24 |
4585061621 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_regwen.1471770747 |
|
|
Aug 25 05:22:49 AM UTC 24 |
Aug 25 05:44:53 AM UTC 24 |
132850354417 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all.4049180052 |
|
|
Aug 25 04:26:11 AM UTC 24 |
Aug 25 05:45:15 AM UTC 24 |
635558728325 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.2199380767 |
|
|
Aug 25 05:44:03 AM UTC 24 |
Aug 25 05:45:48 AM UTC 24 |
2785449697 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.2997938376 |
|
|
Aug 25 05:38:53 AM UTC 24 |
Aug 25 05:45:52 AM UTC 24 |
18198850317 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_regwen.3078578385 |
|
|
Aug 25 05:15:57 AM UTC 24 |
Aug 25 05:46:03 AM UTC 24 |
28527534354 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_bijection.2949261163 |
|
|
Aug 25 04:53:34 AM UTC 24 |
Aug 25 05:46:12 AM UTC 24 |
603472031788 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.348658568 |
|
|
Aug 25 05:41:49 AM UTC 24 |
Aug 25 05:46:35 AM UTC 24 |
3743143050 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.2285093537 |
|
|
Aug 25 05:44:03 AM UTC 24 |
Aug 25 05:47:09 AM UTC 24 |
2771774805 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.1435932693 |
|
|
Aug 25 05:39:29 AM UTC 24 |
Aug 25 05:47:49 AM UTC 24 |
106506836277 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.4091357324 |
|
|
Aug 25 05:38:58 AM UTC 24 |
Aug 25 05:48:21 AM UTC 24 |
16135709598 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.251467237 |
|
|
Aug 25 05:41:15 AM UTC 24 |
Aug 25 05:48:29 AM UTC 24 |
18135264566 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_bijection.4290482938 |
|
|
Aug 25 05:07:59 AM UTC 24 |
Aug 25 05:48:53 AM UTC 24 |
28734957827 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.1249267931 |
|
|
Aug 25 05:37:10 AM UTC 24 |
Aug 25 05:49:05 AM UTC 24 |
132409380907 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.1507779192 |
|
|
Aug 25 05:33:35 AM UTC 24 |
Aug 25 05:49:19 AM UTC 24 |
20033421476 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all.424419847 |
|
|
Aug 25 04:18:19 AM UTC 24 |
Aug 25 05:49:44 AM UTC 24 |
478944081722 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.56740554 |
|
|
Aug 25 05:26:51 AM UTC 24 |
Aug 25 05:50:18 AM UTC 24 |
54500987495 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.3911819293 |
|
|
Aug 25 05:42:56 AM UTC 24 |
Aug 25 05:50:26 AM UTC 24 |
117021081602 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_bijection.2211922677 |
|
|
Aug 25 05:32:22 AM UTC 24 |
Aug 25 05:50:30 AM UTC 24 |
38586290758 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_regwen.3743183271 |
|
|
Aug 25 05:26:54 AM UTC 24 |
Aug 25 05:50:33 AM UTC 24 |
9199415889 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_regwen.1488426907 |
|
|
Aug 25 05:38:09 AM UTC 24 |
Aug 25 05:50:34 AM UTC 24 |
22067673872 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.1313691874 |
|
|
Aug 25 05:42:06 AM UTC 24 |
Aug 25 05:50:52 AM UTC 24 |
8612043930 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_regwen.2648240858 |
|
|
Aug 25 05:39:24 AM UTC 24 |
Aug 25 05:51:00 AM UTC 24 |
49763058218 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.249825935 |
|
|
Aug 25 05:40:09 AM UTC 24 |
Aug 25 05:51:05 AM UTC 24 |
98721144283 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_executable.3735809976 |
|
|
Aug 25 05:29:21 AM UTC 24 |
Aug 25 05:51:10 AM UTC 24 |
18071360520 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_regwen.1566876701 |
|
|
Aug 25 05:40:57 AM UTC 24 |
Aug 25 05:51:33 AM UTC 24 |
84744640176 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.4238575124 |
|
|
Aug 25 05:30:04 AM UTC 24 |
Aug 25 05:51:47 AM UTC 24 |
18388761040 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_executable.2949459721 |
|
|
Aug 25 05:26:52 AM UTC 24 |
Aug 25 05:51:51 AM UTC 24 |
16806706522 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all.734601375 |
|
|
Aug 25 04:41:37 AM UTC 24 |
Aug 25 05:53:08 AM UTC 24 |
178666643546 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_regwen.2755339471 |
|
|
Aug 25 05:35:47 AM UTC 24 |
Aug 25 05:53:33 AM UTC 24 |
10647145460 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all.1077030432 |
|
|
Aug 25 05:20:57 AM UTC 24 |
Aug 25 05:53:40 AM UTC 24 |
40672975121 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.1384576260 |
|
|
Aug 25 05:38:45 AM UTC 24 |
Aug 25 05:54:05 AM UTC 24 |
14215058086 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all.3836278970 |
|
|
Aug 25 05:29:55 AM UTC 24 |
Aug 25 05:54:07 AM UTC 24 |
5302716781 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.3371482507 |
|
|
Aug 25 05:39:45 AM UTC 24 |
Aug 25 05:54:15 AM UTC 24 |
29140427683 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_bijection.3827594028 |
|
|
Aug 25 05:36:30 AM UTC 24 |
Aug 25 05:54:54 AM UTC 24 |
68315848597 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_bijection.4168198512 |
|
|
Aug 25 04:58:19 AM UTC 24 |
Aug 25 05:55:03 AM UTC 24 |
150973930471 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_bijection.1729517655 |
|
|
Aug 25 05:28:39 AM UTC 24 |
Aug 25 05:55:20 AM UTC 24 |
118128315722 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_executable.1802716941 |
|
|
Aug 25 05:30:46 AM UTC 24 |
Aug 25 05:55:45 AM UTC 24 |
23905879782 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.4024991393 |
|
|
Aug 25 05:30:40 AM UTC 24 |
Aug 25 05:56:49 AM UTC 24 |
37225954800 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.2622497041 |
|
|
Aug 25 05:41:38 AM UTC 24 |
Aug 25 05:56:59 AM UTC 24 |
115479433844 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_regwen.2057870736 |
|
|
Aug 25 05:43:11 AM UTC 24 |
Aug 25 05:57:26 AM UTC 24 |
8300588466 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.3578232759 |
|
|
Aug 25 05:39:10 AM UTC 24 |
Aug 25 05:58:00 AM UTC 24 |
218741201305 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_executable.2955915434 |
|
|
Aug 25 05:40:45 AM UTC 24 |
Aug 25 05:58:01 AM UTC 24 |
33000353064 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_executable.1713401248 |
|
|
Aug 25 05:38:08 AM UTC 24 |
Aug 25 05:58:16 AM UTC 24 |
45972329627 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.3729549516 |
|
|
Aug 25 05:37:56 AM UTC 24 |
Aug 25 05:58:26 AM UTC 24 |
9975481553 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_bijection.3369037067 |
|
|
Aug 25 05:18:47 AM UTC 24 |
Aug 25 05:58:40 AM UTC 24 |
172614479808 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_executable.635965091 |
|
|
Aug 25 05:35:46 AM UTC 24 |
Aug 25 05:59:19 AM UTC 24 |
26965672007 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.3735045992 |
|
|
Aug 25 05:40:42 AM UTC 24 |
Aug 25 06:00:05 AM UTC 24 |
12365050658 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.2866222729 |
|
|
Aug 25 05:36:25 AM UTC 24 |
Aug 25 06:00:39 AM UTC 24 |
23229938780 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_bijection.885323302 |
|
|
Aug 25 05:30:05 AM UTC 24 |
Aug 25 06:01:18 AM UTC 24 |
180263696337 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_regwen.504157371 |
|
|
Aug 25 05:31:11 AM UTC 24 |
Aug 25 06:01:20 AM UTC 24 |
143449818466 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_regwen.944652912 |
|
|
Aug 25 05:33:49 AM UTC 24 |
Aug 25 06:03:09 AM UTC 24 |
13936825312 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all.3150663334 |
|
|
Aug 25 05:16:43 AM UTC 24 |
Aug 25 06:04:09 AM UTC 24 |
339679512860 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all.1518017265 |
|
|
Aug 25 05:14:23 AM UTC 24 |
Aug 25 06:05:48 AM UTC 24 |
85747504655 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all.1297671717 |
|
|
Aug 25 05:32:11 AM UTC 24 |
Aug 25 06:06:13 AM UTC 24 |
172778342359 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.1882722941 |
|
|
Aug 25 05:34:40 AM UTC 24 |
Aug 25 06:06:22 AM UTC 24 |
11011988384 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_bijection.209739670 |
|
|
Aug 25 05:41:48 AM UTC 24 |
Aug 25 06:06:38 AM UTC 24 |
111173668174 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.2557977708 |
|
|
Aug 25 04:23:50 AM UTC 24 |
Aug 25 06:08:56 AM UTC 24 |
795498796933 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all.264557688 |
|
|
Aug 25 05:23:11 AM UTC 24 |
Aug 25 06:09:03 AM UTC 24 |
105227508756 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all.3072113355 |
|
|
Aug 25 04:17:24 AM UTC 24 |
Aug 25 06:10:11 AM UTC 24 |
84146343664 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_executable.543582673 |
|
|
Aug 25 05:43:00 AM UTC 24 |
Aug 25 06:10:45 AM UTC 24 |
132591519000 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_bijection.1821090274 |
|
|
Aug 25 05:14:53 AM UTC 24 |
Aug 25 06:11:12 AM UTC 24 |
258225688759 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all.2557364575 |
|
|
Aug 25 04:55:12 AM UTC 24 |
Aug 25 06:11:35 AM UTC 24 |
145461462478 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_bijection.2928589582 |
|
|
Aug 25 05:25:27 AM UTC 24 |
Aug 25 06:13:04 AM UTC 24 |
127176175734 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_bijection.3979138350 |
|
|
Aug 25 05:34:43 AM UTC 24 |
Aug 25 06:17:59 AM UTC 24 |
56884560957 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all.1552109495 |
|
|
Aug 25 04:59:40 AM UTC 24 |
Aug 25 06:20:04 AM UTC 24 |
1570203551652 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all.3602917784 |
|
|
Aug 25 05:10:02 AM UTC 24 |
Aug 25 06:20:41 AM UTC 24 |
365059285290 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all.3858137096 |
|
|
Aug 25 04:48:13 AM UTC 24 |
Aug 25 06:24:08 AM UTC 24 |
442097899035 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all.1945272316 |
|
|
Aug 25 05:36:11 AM UTC 24 |
Aug 25 06:24:42 AM UTC 24 |
109568504120 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_bijection.3803902864 |
|
|
Aug 25 05:38:47 AM UTC 24 |
Aug 25 06:25:21 AM UTC 24 |
602118037044 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_bijection.3566464903 |
|
|
Aug 25 05:39:55 AM UTC 24 |
Aug 25 06:27:34 AM UTC 24 |
96010134503 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all.2488119296 |
|
|
Aug 25 05:38:38 AM UTC 24 |
Aug 25 06:32:23 AM UTC 24 |
101899150932 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all.3701149592 |
|
|
Aug 25 04:35:42 AM UTC 24 |
Aug 25 06:35:33 AM UTC 24 |
48455552376 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all.2962793348 |
|
|
Aug 25 05:34:30 AM UTC 24 |
Aug 25 06:35:58 AM UTC 24 |
54383761760 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all.3675425765 |
|
|
Aug 25 05:28:01 AM UTC 24 |
Aug 25 06:39:39 AM UTC 24 |
332879121221 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all.1428061093 |
|
|
Aug 25 04:51:28 AM UTC 24 |
Aug 25 06:39:53 AM UTC 24 |
136606823232 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all.3649975865 |
|
|
Aug 25 05:41:32 AM UTC 24 |
Aug 25 06:41:27 AM UTC 24 |
57073120899 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all.3872133789 |
|
|
Aug 25 04:17:47 AM UTC 24 |
Aug 25 06:43:00 AM UTC 24 |
1074391677718 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all.4142115632 |
|
|
Aug 25 04:33:17 AM UTC 24 |
Aug 25 06:44:28 AM UTC 24 |
263444538867 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all.2810047526 |
|
|
Aug 25 04:53:17 AM UTC 24 |
Aug 25 06:44:54 AM UTC 24 |
108845488835 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all.3575408564 |
|
|
Aug 25 05:05:20 AM UTC 24 |
Aug 25 06:48:12 AM UTC 24 |
55819892233 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all.3112156608 |
|
|
Aug 25 05:18:16 AM UTC 24 |
Aug 25 06:49:12 AM UTC 24 |
207731715455 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all.1013430782 |
|
|
Aug 25 05:11:52 AM UTC 24 |
Aug 25 06:50:09 AM UTC 24 |
48912426334 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all.3549657099 |
|
|
Aug 25 05:01:05 AM UTC 24 |
Aug 25 06:51:02 AM UTC 24 |
256246401247 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all.2803181400 |
|
|
Aug 25 05:44:17 AM UTC 24 |
Aug 25 07:09:37 AM UTC 24 |
55947478478 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all.3096733117 |
|
|
Aug 25 05:25:08 AM UTC 24 |
Aug 25 07:11:19 AM UTC 24 |
747834323245 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all.3981911753 |
|
|
Aug 25 05:39:38 AM UTC 24 |
Aug 25 07:12:09 AM UTC 24 |
182927721275 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all.2134788484 |
|
|
Aug 25 05:07:43 AM UTC 24 |
Aug 25 07:21:37 AM UTC 24 |
286162376984 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all.890853066 |
|
|
Aug 25 04:45:55 AM UTC 24 |
Aug 25 07:39:57 AM UTC 24 |
349599361360 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1716614419 |
|
|
Aug 25 05:44:49 AM UTC 24 |
Aug 25 05:44:53 AM UTC 24 |
151381014 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3064302185 |
|
|
Aug 25 05:44:48 AM UTC 24 |
Aug 25 05:44:56 AM UTC 24 |
137257189 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.4202042158 |
|
|
Aug 25 05:44:54 AM UTC 24 |
Aug 25 05:44:56 AM UTC 24 |
22005083 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2271743857 |
|
|
Aug 25 05:44:54 AM UTC 24 |
Aug 25 05:44:56 AM UTC 24 |
25035055 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3040078737 |
|
|
Aug 25 05:46:34 AM UTC 24 |
Aug 25 05:46:41 AM UTC 24 |
166928033 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.534989055 |
|
|
Aug 25 05:44:56 AM UTC 24 |
Aug 25 05:44:59 AM UTC 24 |
37879781 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.791653301 |
|
|
Aug 25 05:44:57 AM UTC 24 |
Aug 25 05:44:59 AM UTC 24 |
15118291 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.685006265 |
|
|
Aug 25 05:44:57 AM UTC 24 |
Aug 25 05:45:00 AM UTC 24 |
35673720 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1778383205 |
|
|
Aug 25 05:45:01 AM UTC 24 |
Aug 25 05:45:05 AM UTC 24 |
76163466 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2385662623 |
|
|
Aug 25 05:45:00 AM UTC 24 |
Aug 25 05:45:08 AM UTC 24 |
1468801060 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.234196505 |
|
|
Aug 25 05:45:06 AM UTC 24 |
Aug 25 05:45:10 AM UTC 24 |
611275089 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2047931845 |
|
|
Aug 25 05:45:09 AM UTC 24 |
Aug 25 05:45:11 AM UTC 24 |
13968659 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3816123284 |
|
|
Aug 25 05:45:11 AM UTC 24 |
Aug 25 05:45:13 AM UTC 24 |
16203457 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.450320871 |
|
|
Aug 25 05:45:12 AM UTC 24 |
Aug 25 05:45:15 AM UTC 24 |
92097599 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3383691824 |
|
|
Aug 25 05:45:14 AM UTC 24 |
Aug 25 05:45:16 AM UTC 24 |
20799027 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1882141200 |
|
|
Aug 25 05:45:16 AM UTC 24 |
Aug 25 05:45:19 AM UTC 24 |
40858724 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.766921613 |
|
|
Aug 25 05:45:16 AM UTC 24 |
Aug 25 05:45:24 AM UTC 24 |
1392549872 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3270842687 |
|
|
Aug 25 05:45:19 AM UTC 24 |
Aug 25 05:45:27 AM UTC 24 |
284914745 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.249986667 |
|
|
Aug 25 05:44:35 AM UTC 24 |
Aug 25 05:45:28 AM UTC 24 |
7516585368 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3249381051 |
|
|
Aug 25 05:45:25 AM UTC 24 |
Aug 25 05:45:30 AM UTC 24 |
365824568 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2020379319 |
|
|
Aug 25 05:45:28 AM UTC 24 |
Aug 25 05:45:30 AM UTC 24 |
29439318 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2278219344 |
|
|
Aug 25 05:45:29 AM UTC 24 |
Aug 25 05:45:31 AM UTC 24 |
48440233 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2754860474 |
|
|
Aug 25 05:45:30 AM UTC 24 |
Aug 25 05:45:33 AM UTC 24 |
27345813 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.10058347 |
|
|
Aug 25 05:45:31 AM UTC 24 |
Aug 25 05:45:34 AM UTC 24 |
59935615 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.773850859 |
|
|
Aug 25 05:45:32 AM UTC 24 |
Aug 25 05:45:35 AM UTC 24 |
91276652 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.196641476 |
|
|
Aug 25 05:45:33 AM UTC 24 |
Aug 25 05:45:42 AM UTC 24 |
376676391 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1572992005 |
|
|
Aug 25 05:45:37 AM UTC 24 |
Aug 25 05:45:43 AM UTC 24 |
86550526 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2344374064 |
|
|
Aug 25 05:45:44 AM UTC 24 |
Aug 25 05:45:46 AM UTC 24 |
23490085 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.611688761 |
|
|
Aug 25 05:45:43 AM UTC 24 |
Aug 25 05:45:48 AM UTC 24 |
280748210 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2809902489 |
|
|
Aug 25 05:45:47 AM UTC 24 |
Aug 25 05:45:49 AM UTC 24 |
34404447 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2291844424 |
|
|
Aug 25 05:45:49 AM UTC 24 |
Aug 25 05:45:51 AM UTC 24 |
25063566 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2339230242 |
|
|
Aug 25 05:45:48 AM UTC 24 |
Aug 25 05:45:52 AM UTC 24 |
80307060 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.535245635 |
|
|
Aug 25 05:45:50 AM UTC 24 |
Aug 25 05:45:53 AM UTC 24 |
25994429 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2738752619 |
|
|
Aug 25 05:45:01 AM UTC 24 |
Aug 25 05:45:56 AM UTC 24 |
10544002637 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.81124213 |
|
|
Aug 25 05:45:54 AM UTC 24 |
Aug 25 05:45:57 AM UTC 24 |
356156408 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1418407149 |
|
|
Aug 25 05:45:57 AM UTC 24 |
Aug 25 05:45:59 AM UTC 24 |
15357454 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1027799442 |
|
|
Aug 25 05:45:54 AM UTC 24 |
Aug 25 05:45:59 AM UTC 24 |
333588023 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2478267554 |
|
|
Aug 25 05:45:58 AM UTC 24 |
Aug 25 05:46:00 AM UTC 24 |
16416144 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.793702277 |
|
|
Aug 25 05:45:52 AM UTC 24 |
Aug 25 05:46:01 AM UTC 24 |
713708051 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.922343680 |
|
|
Aug 25 05:46:00 AM UTC 24 |
Aug 25 05:46:02 AM UTC 24 |
28712199 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.4100703284 |
|
|
Aug 25 05:46:01 AM UTC 24 |
Aug 25 05:46:03 AM UTC 24 |
233956561 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3422896988 |
|
|
Aug 25 05:46:00 AM UTC 24 |
Aug 25 05:46:05 AM UTC 24 |
119018589 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2111960030 |
|
|
Aug 25 05:46:04 AM UTC 24 |
Aug 25 05:46:07 AM UTC 24 |
113479901 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2567912799 |
|
|
Aug 25 05:46:06 AM UTC 24 |
Aug 25 05:46:08 AM UTC 24 |
21116353 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2424610316 |
|
|
Aug 25 05:45:17 AM UTC 24 |
Aug 25 05:46:08 AM UTC 24 |
3843690583 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.4015824610 |
|
|
Aug 25 05:46:08 AM UTC 24 |
Aug 25 05:46:11 AM UTC 24 |
26317943 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3745824591 |
|
|
Aug 25 05:46:03 AM UTC 24 |
Aug 25 05:46:12 AM UTC 24 |
2296905841 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2301351070 |
|
|
Aug 25 05:46:04 AM UTC 24 |
Aug 25 05:46:13 AM UTC 24 |
263512929 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1207477331 |
|
|
Aug 25 05:46:13 AM UTC 24 |
Aug 25 05:46:15 AM UTC 24 |
14790952 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1837698621 |
|
|
Aug 25 05:46:13 AM UTC 24 |
Aug 25 05:46:15 AM UTC 24 |
73335992 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3381261994 |
|
|
Aug 25 05:46:12 AM UTC 24 |
Aug 25 05:46:17 AM UTC 24 |
55401521 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1609630305 |
|
|
Aug 25 05:46:13 AM UTC 24 |
Aug 25 05:46:18 AM UTC 24 |
264476738 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1391364373 |
|
|
Aug 25 05:46:09 AM UTC 24 |
Aug 25 05:46:19 AM UTC 24 |
1326595491 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.4242670264 |
|
|
Aug 25 05:46:20 AM UTC 24 |
Aug 25 05:46:22 AM UTC 24 |
48834608 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2926657367 |
|
|
Aug 25 05:46:18 AM UTC 24 |
Aug 25 05:46:24 AM UTC 24 |
229959180 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1585148202 |
|
|
Aug 25 05:46:17 AM UTC 24 |
Aug 25 05:46:24 AM UTC 24 |
158609305 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.198956685 |
|
|
Aug 25 05:46:16 AM UTC 24 |
Aug 25 05:46:25 AM UTC 24 |
1866880153 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.541273976 |
|
|
Aug 25 05:46:23 AM UTC 24 |
Aug 25 05:46:25 AM UTC 24 |
113549031 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.575118664 |
|
|
Aug 25 05:45:35 AM UTC 24 |
Aug 25 05:46:29 AM UTC 24 |
3692101249 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2711698254 |
|
|
Aug 25 05:46:26 AM UTC 24 |
Aug 25 05:46:30 AM UTC 24 |
82775411 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.4069327023 |
|
|
Aug 25 05:46:29 AM UTC 24 |
Aug 25 05:46:31 AM UTC 24 |
43715671 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4156139845 |
|
|
Aug 25 05:46:26 AM UTC 24 |
Aug 25 05:46:31 AM UTC 24 |
322925939 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3953640964 |
|
|
Aug 25 05:46:25 AM UTC 24 |
Aug 25 05:46:33 AM UTC 24 |
433364302 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3011058150 |
|
|
Aug 25 05:46:31 AM UTC 24 |
Aug 25 05:46:34 AM UTC 24 |
46263100 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2061777020 |
|
|
Aug 25 05:46:36 AM UTC 24 |
Aug 25 05:46:38 AM UTC 24 |
16322623 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.4199426020 |
|
|
Aug 25 05:46:35 AM UTC 24 |
Aug 25 05:46:39 AM UTC 24 |
505932679 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.295505417 |
|
|
Aug 25 05:46:39 AM UTC 24 |
Aug 25 05:46:41 AM UTC 24 |
17173771 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2435612186 |
|
|
Aug 25 05:46:33 AM UTC 24 |
Aug 25 05:46:42 AM UTC 24 |
475149250 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2219471908 |
|
|
Aug 25 05:46:44 AM UTC 24 |
Aug 25 05:46:47 AM UTC 24 |
464652595 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1505141140 |
|
|
Aug 25 05:46:40 AM UTC 24 |
Aug 25 05:46:48 AM UTC 24 |
681040617 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.841191976 |
|
|
Aug 25 05:46:48 AM UTC 24 |
Aug 25 05:46:50 AM UTC 24 |
11877936 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3354851871 |
|
|
Aug 25 05:46:43 AM UTC 24 |
Aug 25 05:46:51 AM UTC 24 |
95878185 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3052301817 |
|
|
Aug 25 05:46:49 AM UTC 24 |
Aug 25 05:46:51 AM UTC 24 |
23392931 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2368261001 |
|
|
Aug 25 05:46:50 AM UTC 24 |
Aug 25 05:46:57 AM UTC 24 |
1073075350 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.662969094 |
|
|
Aug 25 05:46:52 AM UTC 24 |
Aug 25 05:46:59 AM UTC 24 |
2021670724 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1215013407 |
|
|
Aug 25 05:47:01 AM UTC 24 |
Aug 25 05:47:03 AM UTC 24 |
40019345 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.719412114 |
|
|
Aug 25 05:46:57 AM UTC 24 |
Aug 25 05:47:03 AM UTC 24 |
2429473959 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1351673156 |
|
|
Aug 25 05:46:10 AM UTC 24 |
Aug 25 05:47:03 AM UTC 24 |
15395229770 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4021540090 |
|
|
Aug 25 05:47:04 AM UTC 24 |
Aug 25 05:47:06 AM UTC 24 |
22020644 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.402295444 |
|
|
Aug 25 05:47:04 AM UTC 24 |
Aug 25 05:47:11 AM UTC 24 |
1362525281 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1285881133 |
|
|
Aug 25 05:47:12 AM UTC 24 |
Aug 25 05:47:14 AM UTC 24 |
69472743 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2743332881 |
|
|
Aug 25 05:47:10 AM UTC 24 |
Aug 25 05:47:14 AM UTC 24 |
648983272 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1633563538 |
|
|
Aug 25 05:47:07 AM UTC 24 |
Aug 25 05:47:15 AM UTC 24 |
230710148 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2151827504 |
|
|
Aug 25 05:47:15 AM UTC 24 |
Aug 25 05:47:17 AM UTC 24 |
49639178 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.104705369 |
|
|
Aug 25 05:47:16 AM UTC 24 |
Aug 25 05:47:24 AM UTC 24 |
1546855468 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.4144417115 |
|
|
Aug 25 05:47:18 AM UTC 24 |
Aug 25 05:47:26 AM UTC 24 |
576531851 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.567575695 |
|
|
Aug 25 05:47:25 AM UTC 24 |
Aug 25 05:47:29 AM UTC 24 |
111259325 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2947035280 |
|
|
Aug 25 05:47:27 AM UTC 24 |
Aug 25 05:47:29 AM UTC 24 |
35573440 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.348571995 |
|
|
Aug 25 05:47:29 AM UTC 24 |
Aug 25 05:47:32 AM UTC 24 |
32680499 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1874129411 |
|
|
Aug 25 05:45:52 AM UTC 24 |
Aug 25 05:47:37 AM UTC 24 |
14441789389 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2171465062 |
|
|
Aug 25 05:47:31 AM UTC 24 |
Aug 25 05:47:37 AM UTC 24 |
1462370374 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3395073342 |
|
|
Aug 25 05:47:38 AM UTC 24 |
Aug 25 05:47:42 AM UTC 24 |
283726690 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2216336479 |
|
|
Aug 25 05:47:43 AM UTC 24 |
Aug 25 05:47:45 AM UTC 24 |
30206944 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3710636885 |
|
|
Aug 25 05:47:38 AM UTC 24 |
Aug 25 05:47:45 AM UTC 24 |
126888537 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2284633598 |
|
|
Aug 25 05:46:03 AM UTC 24 |
Aug 25 05:47:48 AM UTC 24 |
88035970938 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1216922952 |
|
|
Aug 25 05:47:46 AM UTC 24 |
Aug 25 05:47:49 AM UTC 24 |
45104461 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3558609896 |
|
|
Aug 25 05:46:16 AM UTC 24 |
Aug 25 05:47:51 AM UTC 24 |
7045286850 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3312639370 |
|
|
Aug 25 05:47:46 AM UTC 24 |
Aug 25 05:47:53 AM UTC 24 |
364721281 ps |