| T548 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_regwen.2506279949 |
|
|
Aug 25 04:50:55 AM UTC 24 |
Aug 25 05:07:15 AM UTC 24 |
13489809136 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.2465257311 |
|
|
Aug 25 05:07:15 AM UTC 24 |
Aug 25 05:07:22 AM UTC 24 |
357809759 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.2110437130 |
|
|
Aug 25 05:07:07 AM UTC 24 |
Aug 25 05:07:37 AM UTC 24 |
727380119 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.3394465139 |
|
|
Aug 25 05:00:01 AM UTC 24 |
Aug 25 05:07:41 AM UTC 24 |
22415252219 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.2275122827 |
|
|
Aug 25 04:22:34 AM UTC 24 |
Aug 25 05:07:42 AM UTC 24 |
517949933440 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3028986820 |
|
|
Aug 25 05:03:24 AM UTC 24 |
Aug 25 05:07:51 AM UTC 24 |
3972021629 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.2737048676 |
|
|
Aug 25 05:07:41 AM UTC 24 |
Aug 25 05:07:53 AM UTC 24 |
128018214 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_alert_test.4146442479 |
|
|
Aug 25 05:07:53 AM UTC 24 |
Aug 25 05:07:55 AM UTC 24 |
26974984 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.4043222074 |
|
|
Aug 25 04:50:50 AM UTC 24 |
Aug 25 05:07:58 AM UTC 24 |
10042687787 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all.1181664671 |
|
|
Aug 25 04:27:52 AM UTC 24 |
Aug 25 05:08:09 AM UTC 24 |
38315539229 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.2236331778 |
|
|
Aug 25 04:59:03 AM UTC 24 |
Aug 25 05:08:17 AM UTC 24 |
9859244264 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access.3800444489 |
|
|
Aug 25 05:08:17 AM UTC 24 |
Aug 25 05:08:30 AM UTC 24 |
826770425 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.3942301911 |
|
|
Aug 25 05:04:50 AM UTC 24 |
Aug 25 05:08:35 AM UTC 24 |
76963610813 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.2862559531 |
|
|
Aug 25 05:01:55 AM UTC 24 |
Aug 25 05:08:58 AM UTC 24 |
5835875273 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.923713181 |
|
|
Aug 25 05:04:59 AM UTC 24 |
Aug 25 05:09:00 AM UTC 24 |
5222093825 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.1098222980 |
|
|
Aug 25 05:08:36 AM UTC 24 |
Aug 25 05:09:10 AM UTC 24 |
1566361034 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.1755997384 |
|
|
Aug 25 04:50:17 AM UTC 24 |
Aug 25 05:09:11 AM UTC 24 |
20128504225 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.3169881406 |
|
|
Aug 25 04:51:34 AM UTC 24 |
Aug 25 05:09:23 AM UTC 24 |
8051180481 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.2000883294 |
|
|
Aug 25 05:07:08 AM UTC 24 |
Aug 25 05:09:33 AM UTC 24 |
42582854059 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.3731852930 |
|
|
Aug 25 05:09:34 AM UTC 24 |
Aug 25 05:09:41 AM UTC 24 |
1408072210 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_smoke.83709612 |
|
|
Aug 25 05:07:54 AM UTC 24 |
Aug 25 05:09:49 AM UTC 24 |
1583150938 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.2203111437 |
|
|
Aug 25 05:02:49 AM UTC 24 |
Aug 25 05:10:01 AM UTC 24 |
14419275691 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_executable.2107055937 |
|
|
Aug 25 04:52:14 AM UTC 24 |
Aug 25 05:10:02 AM UTC 24 |
27886908634 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all.1037393952 |
|
|
Aug 25 04:40:24 AM UTC 24 |
Aug 25 05:10:08 AM UTC 24 |
39400433894 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_executable.1128733330 |
|
|
Aug 25 04:57:01 AM UTC 24 |
Aug 25 05:10:09 AM UTC 24 |
7980833126 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.971157083 |
|
|
Aug 25 04:37:16 AM UTC 24 |
Aug 25 05:10:11 AM UTC 24 |
54902582994 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_alert_test.2540097384 |
|
|
Aug 25 05:10:09 AM UTC 24 |
Aug 25 05:10:12 AM UTC 24 |
24249356 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.3076385838 |
|
|
Aug 25 04:55:40 AM UTC 24 |
Aug 25 05:10:17 AM UTC 24 |
13356587835 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2709630662 |
|
|
Aug 25 05:10:01 AM UTC 24 |
Aug 25 05:10:20 AM UTC 24 |
348475616 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.969472668 |
|
|
Aug 25 05:08:58 AM UTC 24 |
Aug 25 05:10:23 AM UTC 24 |
3131781556 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_bijection.511394100 |
|
|
Aug 25 04:50:20 AM UTC 24 |
Aug 25 05:10:33 AM UTC 24 |
67289190530 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.3557375227 |
|
|
Aug 25 05:00:10 AM UTC 24 |
Aug 25 05:10:39 AM UTC 24 |
17989998218 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.2665434063 |
|
|
Aug 25 05:09:01 AM UTC 24 |
Aug 25 05:10:51 AM UTC 24 |
50874067996 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.1166007839 |
|
|
Aug 25 05:10:34 AM UTC 24 |
Aug 25 05:10:52 AM UTC 24 |
1390287481 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access.1810824305 |
|
|
Aug 25 05:10:21 AM UTC 24 |
Aug 25 05:10:57 AM UTC 24 |
3373029111 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.1614212837 |
|
|
Aug 25 05:07:37 AM UTC 24 |
Aug 25 05:11:11 AM UTC 24 |
10123827486 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.194916395 |
|
|
Aug 25 05:10:40 AM UTC 24 |
Aug 25 05:11:21 AM UTC 24 |
2861033245 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_regwen.2366490702 |
|
|
Aug 25 05:02:39 AM UTC 24 |
Aug 25 05:11:25 AM UTC 24 |
5873740585 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_bijection.1609878921 |
|
|
Aug 25 04:17:03 AM UTC 24 |
Aug 25 05:11:27 AM UTC 24 |
482363306257 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.2410323392 |
|
|
Aug 25 05:11:22 AM UTC 24 |
Aug 25 05:11:30 AM UTC 24 |
3056072774 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.3101931101 |
|
|
Aug 25 05:07:56 AM UTC 24 |
Aug 25 05:11:51 AM UTC 24 |
2656747640 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_smoke.2335846220 |
|
|
Aug 25 05:10:09 AM UTC 24 |
Aug 25 05:12:04 AM UTC 24 |
1755255482 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_alert_test.672514721 |
|
|
Aug 25 05:12:04 AM UTC 24 |
Aug 25 05:12:06 AM UTC 24 |
70722795 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2316884152 |
|
|
Aug 25 05:11:31 AM UTC 24 |
Aug 25 05:12:10 AM UTC 24 |
756221612 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.3972640570 |
|
|
Aug 25 05:06:42 AM UTC 24 |
Aug 25 05:12:10 AM UTC 24 |
14548996359 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_executable.3217994804 |
|
|
Aug 25 05:07:14 AM UTC 24 |
Aug 25 05:12:11 AM UTC 24 |
12818837231 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_regwen.2226245320 |
|
|
Aug 25 05:04:43 AM UTC 24 |
Aug 25 05:12:46 AM UTC 24 |
9795076391 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_smoke.1811427416 |
|
|
Aug 25 05:12:07 AM UTC 24 |
Aug 25 05:12:52 AM UTC 24 |
1491798835 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.422760938 |
|
|
Aug 25 05:08:09 AM UTC 24 |
Aug 25 05:12:57 AM UTC 24 |
9168259519 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.1127411426 |
|
|
Aug 25 05:12:57 AM UTC 24 |
Aug 25 05:13:46 AM UTC 24 |
1462916001 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.3495812499 |
|
|
Aug 25 05:09:49 AM UTC 24 |
Aug 25 05:13:47 AM UTC 24 |
6426195623 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_bijection.1508042323 |
|
|
Aug 25 04:25:12 AM UTC 24 |
Aug 25 05:13:47 AM UTC 24 |
210995230324 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_regwen.2057499571 |
|
|
Aug 25 04:52:21 AM UTC 24 |
Aug 25 05:13:51 AM UTC 24 |
14827898507 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.800133269 |
|
|
Aug 25 05:10:52 AM UTC 24 |
Aug 25 05:13:54 AM UTC 24 |
17208591701 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.768133765 |
|
|
Aug 25 05:13:46 AM UTC 24 |
Aug 25 05:14:01 AM UTC 24 |
1994261506 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.3043141059 |
|
|
Aug 25 05:13:55 AM UTC 24 |
Aug 25 05:14:01 AM UTC 24 |
687269777 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.1539082939 |
|
|
Aug 25 05:03:55 AM UTC 24 |
Aug 25 05:14:09 AM UTC 24 |
38868899575 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access.1908592046 |
|
|
Aug 25 05:12:35 AM UTC 24 |
Aug 25 05:14:23 AM UTC 24 |
6411034648 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.2435585862 |
|
|
Aug 25 05:07:22 AM UTC 24 |
Aug 25 05:14:25 AM UTC 24 |
27680637338 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_alert_test.211587316 |
|
|
Aug 25 05:14:26 AM UTC 24 |
Aug 25 05:14:28 AM UTC 24 |
11357611 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.1646416602 |
|
|
Aug 25 05:11:28 AM UTC 24 |
Aug 25 05:14:51 AM UTC 24 |
4388006335 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.2231410747 |
|
|
Aug 25 05:12:53 AM UTC 24 |
Aug 25 05:14:52 AM UTC 24 |
791807147 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.2145535392 |
|
|
Aug 25 05:06:51 AM UTC 24 |
Aug 25 05:14:54 AM UTC 24 |
57954191001 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.3850074413 |
|
|
Aug 25 05:08:30 AM UTC 24 |
Aug 25 05:15:09 AM UTC 24 |
11288891331 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.3398607665 |
|
|
Aug 25 04:56:43 AM UTC 24 |
Aug 25 05:15:34 AM UTC 24 |
45603830528 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_regwen.353710229 |
|
|
Aug 25 05:13:53 AM UTC 24 |
Aug 25 05:15:34 AM UTC 24 |
6030976684 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.1629783014 |
|
|
Aug 25 05:10:24 AM UTC 24 |
Aug 25 05:15:37 AM UTC 24 |
36376200099 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_bijection.1643764466 |
|
|
Aug 25 04:46:07 AM UTC 24 |
Aug 25 05:15:45 AM UTC 24 |
20849729276 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_smoke.3104739632 |
|
|
Aug 25 05:14:29 AM UTC 24 |
Aug 25 05:15:52 AM UTC 24 |
4356630975 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all.1314133941 |
|
|
Aug 25 04:37:06 AM UTC 24 |
Aug 25 05:15:52 AM UTC 24 |
369601983280 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.1166728811 |
|
|
Aug 25 05:15:35 AM UTC 24 |
Aug 25 05:15:57 AM UTC 24 |
2921218795 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.1853401519 |
|
|
Aug 25 04:45:42 AM UTC 24 |
Aug 25 05:16:08 AM UTC 24 |
15005652694 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.2509404060 |
|
|
Aug 25 05:15:37 AM UTC 24 |
Aug 25 05:16:09 AM UTC 24 |
740271409 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.3006391193 |
|
|
Aug 25 05:16:09 AM UTC 24 |
Aug 25 05:16:17 AM UTC 24 |
709212405 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.3968674839 |
|
|
Aug 25 05:04:36 AM UTC 24 |
Aug 25 05:16:35 AM UTC 24 |
9735552136 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.1201600158 |
|
|
Aug 25 05:15:45 AM UTC 24 |
Aug 25 05:16:42 AM UTC 24 |
30614053232 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_regwen.1819990629 |
|
|
Aug 25 05:00:38 AM UTC 24 |
Aug 25 05:16:44 AM UTC 24 |
13444413207 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_alert_test.3716855904 |
|
|
Aug 25 05:16:45 AM UTC 24 |
Aug 25 05:16:47 AM UTC 24 |
19943624 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.1277310083 |
|
|
Aug 25 05:14:02 AM UTC 24 |
Aug 25 05:16:55 AM UTC 24 |
3807143243 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.2065719998 |
|
|
Aug 25 05:09:42 AM UTC 24 |
Aug 25 05:16:55 AM UTC 24 |
13828410669 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access.270810709 |
|
|
Aug 25 05:15:10 AM UTC 24 |
Aug 25 05:16:56 AM UTC 24 |
902598337 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3651647654 |
|
|
Aug 25 05:16:36 AM UTC 24 |
Aug 25 05:16:57 AM UTC 24 |
294303716 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_smoke.315647951 |
|
|
Aug 25 05:16:48 AM UTC 24 |
Aug 25 05:17:01 AM UTC 24 |
2786475147 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access.454414879 |
|
|
Aug 25 05:16:58 AM UTC 24 |
Aug 25 05:17:05 AM UTC 24 |
369039012 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.4257315669 |
|
|
Aug 25 05:14:10 AM UTC 24 |
Aug 25 05:17:20 AM UTC 24 |
10594252344 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.1403764334 |
|
|
Aug 25 04:54:23 AM UTC 24 |
Aug 25 05:17:26 AM UTC 24 |
58970080638 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.3175399021 |
|
|
Aug 25 05:14:02 AM UTC 24 |
Aug 25 05:17:32 AM UTC 24 |
27640715473 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.1115585280 |
|
|
Aug 25 05:11:26 AM UTC 24 |
Aug 25 05:17:35 AM UTC 24 |
5363111327 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_regwen.3289860739 |
|
|
Aug 25 04:47:55 AM UTC 24 |
Aug 25 05:17:38 AM UTC 24 |
17020400056 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.2737212225 |
|
|
Aug 25 05:17:21 AM UTC 24 |
Aug 25 05:17:38 AM UTC 24 |
1447233148 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.3219358197 |
|
|
Aug 25 05:17:40 AM UTC 24 |
Aug 25 05:17:46 AM UTC 24 |
348046292 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.1743979847 |
|
|
Aug 25 05:10:18 AM UTC 24 |
Aug 25 05:18:05 AM UTC 24 |
22737066311 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_bijection.1248420800 |
|
|
Aug 25 04:29:18 AM UTC 24 |
Aug 25 05:18:05 AM UTC 24 |
657555592510 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_executable.4231416840 |
|
|
Aug 25 04:47:38 AM UTC 24 |
Aug 25 05:18:15 AM UTC 24 |
20648359776 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.431597525 |
|
|
Aug 25 05:12:12 AM UTC 24 |
Aug 25 05:18:19 AM UTC 24 |
5349218692 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_alert_test.4120152325 |
|
|
Aug 25 05:18:20 AM UTC 24 |
Aug 25 05:18:22 AM UTC 24 |
13947744 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.4151537528 |
|
|
Aug 25 05:14:55 AM UTC 24 |
Aug 25 05:18:41 AM UTC 24 |
16652048631 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all.957083498 |
|
|
Aug 25 04:24:57 AM UTC 24 |
Aug 25 05:18:47 AM UTC 24 |
84108667080 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.232414457 |
|
|
Aug 25 05:18:06 AM UTC 24 |
Aug 25 05:18:58 AM UTC 24 |
4256057833 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.2204299063 |
|
|
Aug 25 05:17:06 AM UTC 24 |
Aug 25 05:18:59 AM UTC 24 |
1535968864 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.1205795065 |
|
|
Aug 25 05:16:18 AM UTC 24 |
Aug 25 05:19:04 AM UTC 24 |
1616989999 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access.1307401290 |
|
|
Aug 25 05:19:00 AM UTC 24 |
Aug 25 05:19:09 AM UTC 24 |
418380130 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_executable.4068654 |
|
|
Aug 25 04:54:31 AM UTC 24 |
Aug 25 05:19:14 AM UTC 24 |
30885404764 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.2829858613 |
|
|
Aug 25 05:17:27 AM UTC 24 |
Aug 25 05:19:21 AM UTC 24 |
11112464770 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.1119484087 |
|
|
Aug 25 05:12:48 AM UTC 24 |
Aug 25 05:19:44 AM UTC 24 |
14177087911 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_smoke.1746079775 |
|
|
Aug 25 05:18:23 AM UTC 24 |
Aug 25 05:20:16 AM UTC 24 |
5613162927 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_executable.3835678534 |
|
|
Aug 25 05:04:37 AM UTC 24 |
Aug 25 05:20:17 AM UTC 24 |
79976323089 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.4008071317 |
|
|
Aug 25 04:47:21 AM UTC 24 |
Aug 25 05:20:26 AM UTC 24 |
103503667081 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.1580001037 |
|
|
Aug 25 05:03:36 AM UTC 24 |
Aug 25 05:20:31 AM UTC 24 |
11252625076 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.4015715651 |
|
|
Aug 25 05:20:28 AM UTC 24 |
Aug 25 05:20:36 AM UTC 24 |
4205991456 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.1856095678 |
|
|
Aug 25 05:19:22 AM UTC 24 |
Aug 25 05:20:53 AM UTC 24 |
9902108513 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.3742713319 |
|
|
Aug 25 04:21:39 AM UTC 24 |
Aug 25 05:20:56 AM UTC 24 |
40700266053 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.1316457592 |
|
|
Aug 25 05:19:10 AM UTC 24 |
Aug 25 05:21:00 AM UTC 24 |
790839954 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_alert_test.77707196 |
|
|
Aug 25 05:21:01 AM UTC 24 |
Aug 25 05:21:03 AM UTC 24 |
68284639 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3359169254 |
|
|
Aug 25 05:20:54 AM UTC 24 |
Aug 25 05:21:26 AM UTC 24 |
1136057769 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_smoke.997125666 |
|
|
Aug 25 05:21:04 AM UTC 24 |
Aug 25 05:21:27 AM UTC 24 |
3697125573 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_regwen.1291115813 |
|
|
Aug 25 04:54:38 AM UTC 24 |
Aug 25 05:21:29 AM UTC 24 |
10421821988 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.1425372651 |
|
|
Aug 25 05:17:02 AM UTC 24 |
Aug 25 05:21:32 AM UTC 24 |
4320840044 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.3158615163 |
|
|
Aug 25 05:19:15 AM UTC 24 |
Aug 25 05:21:38 AM UTC 24 |
794889951 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.3636245052 |
|
|
Aug 25 05:18:06 AM UTC 24 |
Aug 25 05:22:05 AM UTC 24 |
55031535308 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access.1348639210 |
|
|
Aug 25 05:21:33 AM UTC 24 |
Aug 25 05:22:25 AM UTC 24 |
1883637732 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.2784350441 |
|
|
Aug 25 05:20:37 AM UTC 24 |
Aug 25 05:22:25 AM UTC 24 |
9838005192 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.4028127800 |
|
|
Aug 25 05:22:06 AM UTC 24 |
Aug 25 05:22:28 AM UTC 24 |
1460522748 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.2320816583 |
|
|
Aug 25 05:15:35 AM UTC 24 |
Aug 25 05:22:31 AM UTC 24 |
11350133695 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.4021662377 |
|
|
Aug 25 05:22:25 AM UTC 24 |
Aug 25 05:22:48 AM UTC 24 |
729292817 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.190844009 |
|
|
Aug 25 05:22:26 AM UTC 24 |
Aug 25 05:22:50 AM UTC 24 |
2165169492 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_bijection.648521443 |
|
|
Aug 25 05:10:13 AM UTC 24 |
Aug 25 05:22:50 AM UTC 24 |
34215155009 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_regwen.3861365217 |
|
|
Aug 25 05:17:39 AM UTC 24 |
Aug 25 05:22:58 AM UTC 24 |
5216550512 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.4231790237 |
|
|
Aug 25 05:22:51 AM UTC 24 |
Aug 25 05:23:01 AM UTC 24 |
6715470254 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_executable.376895100 |
|
|
Aug 25 05:10:57 AM UTC 24 |
Aug 25 05:23:10 AM UTC 24 |
125740444303 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1506328007 |
|
|
Aug 25 05:23:02 AM UTC 24 |
Aug 25 05:23:22 AM UTC 24 |
506697154 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_alert_test.2969797395 |
|
|
Aug 25 05:23:23 AM UTC 24 |
Aug 25 05:23:25 AM UTC 24 |
43307226 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.3338656522 |
|
|
Aug 25 04:57:56 AM UTC 24 |
Aug 25 05:23:30 AM UTC 24 |
77391926165 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_executable.1081558263 |
|
|
Aug 25 04:59:04 AM UTC 24 |
Aug 25 05:23:35 AM UTC 24 |
22420605947 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_regwen.2974078101 |
|
|
Aug 25 05:07:15 AM UTC 24 |
Aug 25 05:23:38 AM UTC 24 |
4626930571 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_smoke.544976221 |
|
|
Aug 25 05:23:26 AM UTC 24 |
Aug 25 05:23:40 AM UTC 24 |
467838498 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all.2923411049 |
|
|
Aug 25 04:44:02 AM UTC 24 |
Aug 25 05:23:45 AM UTC 24 |
98880041102 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.3758470313 |
|
|
Aug 25 05:13:47 AM UTC 24 |
Aug 25 05:23:59 AM UTC 24 |
6447817033 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.1912651705 |
|
|
Aug 25 05:17:47 AM UTC 24 |
Aug 25 05:24:08 AM UTC 24 |
10720932322 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.173175805 |
|
|
Aug 25 05:15:52 AM UTC 24 |
Aug 25 05:24:11 AM UTC 24 |
29720764741 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_executable.159227041 |
|
|
Aug 25 05:02:24 AM UTC 24 |
Aug 25 05:24:11 AM UTC 24 |
22857691567 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.401871832 |
|
|
Aug 25 05:16:10 AM UTC 24 |
Aug 25 05:24:19 AM UTC 24 |
74670317462 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access.2221069052 |
|
|
Aug 25 05:23:41 AM UTC 24 |
Aug 25 05:24:21 AM UTC 24 |
5977719689 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.3256350330 |
|
|
Aug 25 05:22:59 AM UTC 24 |
Aug 25 05:24:33 AM UTC 24 |
2710631396 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.2728134226 |
|
|
Aug 25 05:24:34 AM UTC 24 |
Aug 25 05:24:42 AM UTC 24 |
1401748905 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.2547898426 |
|
|
Aug 25 05:24:00 AM UTC 24 |
Aug 25 05:24:42 AM UTC 24 |
2888076639 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.2803361903 |
|
|
Aug 25 05:16:57 AM UTC 24 |
Aug 25 05:24:48 AM UTC 24 |
5265391588 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2642961474 |
|
|
Aug 25 05:24:49 AM UTC 24 |
Aug 25 05:25:07 AM UTC 24 |
941370233 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.1290697375 |
|
|
Aug 25 05:24:11 AM UTC 24 |
Aug 25 05:25:19 AM UTC 24 |
16377977556 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_alert_test.2199855727 |
|
|
Aug 25 05:25:20 AM UTC 24 |
Aug 25 05:25:22 AM UTC 24 |
19792215 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all.2733945020 |
|
|
Aug 25 04:18:45 AM UTC 24 |
Aug 25 05:25:24 AM UTC 24 |
95447536040 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.729995380 |
|
|
Aug 25 05:24:09 AM UTC 24 |
Aug 25 05:25:27 AM UTC 24 |
3750917742 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.179229001 |
|
|
Aug 25 05:10:13 AM UTC 24 |
Aug 25 05:25:41 AM UTC 24 |
11015971000 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_smoke.1709489804 |
|
|
Aug 25 05:25:23 AM UTC 24 |
Aug 25 05:25:45 AM UTC 24 |
2881095791 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access.904824194 |
|
|
Aug 25 05:25:46 AM UTC 24 |
Aug 25 05:26:18 AM UTC 24 |
5739094228 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.3117747449 |
|
|
Aug 25 05:19:05 AM UTC 24 |
Aug 25 05:26:25 AM UTC 24 |
12260749584 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.1434120723 |
|
|
Aug 25 05:21:26 AM UTC 24 |
Aug 25 05:26:32 AM UTC 24 |
30146339643 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.2316153420 |
|
|
Aug 25 05:24:43 AM UTC 24 |
Aug 25 05:26:45 AM UTC 24 |
2921184358 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.2458358827 |
|
|
Aug 25 05:26:26 AM UTC 24 |
Aug 25 05:26:50 AM UTC 24 |
3010435361 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.3273099237 |
|
|
Aug 25 05:12:11 AM UTC 24 |
Aug 25 05:26:52 AM UTC 24 |
23724215426 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.1799620695 |
|
|
Aug 25 05:18:59 AM UTC 24 |
Aug 25 05:26:52 AM UTC 24 |
26687098191 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.174566389 |
|
|
Aug 25 05:07:12 AM UTC 24 |
Aug 25 05:27:09 AM UTC 24 |
32788513120 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.726885144 |
|
|
Aug 25 05:27:10 AM UTC 24 |
Aug 25 05:27:16 AM UTC 24 |
2396659542 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.4210798403 |
|
|
Aug 25 05:26:32 AM UTC 24 |
Aug 25 05:27:49 AM UTC 24 |
1596205010 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.1012447232 |
|
|
Aug 25 05:01:25 AM UTC 24 |
Aug 25 05:27:52 AM UTC 24 |
12290130466 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.2886839745 |
|
|
Aug 25 05:24:43 AM UTC 24 |
Aug 25 05:28:00 AM UTC 24 |
10959504029 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.3621608875 |
|
|
Aug 25 05:20:32 AM UTC 24 |
Aug 25 05:28:00 AM UTC 24 |
21528546052 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_alert_test.3883806145 |
|
|
Aug 25 05:28:01 AM UTC 24 |
Aug 25 05:28:03 AM UTC 24 |
55847592 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all.3366304979 |
|
|
Aug 25 04:28:57 AM UTC 24 |
Aug 25 05:28:25 AM UTC 24 |
140816271161 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_bijection.825708521 |
|
|
Aug 25 04:51:34 AM UTC 24 |
Aug 25 05:28:38 AM UTC 24 |
74536531838 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.113799686 |
|
|
Aug 25 05:26:45 AM UTC 24 |
Aug 25 05:28:42 AM UTC 24 |
10157787222 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_smoke.212921369 |
|
|
Aug 25 05:28:04 AM UTC 24 |
Aug 25 05:28:46 AM UTC 24 |
2694245981 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_executable.1152485561 |
|
|
Aug 25 05:09:13 AM UTC 24 |
Aug 25 05:28:50 AM UTC 24 |
21562836268 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.535341708 |
|
|
Aug 25 05:00:23 AM UTC 24 |
Aug 25 05:28:51 AM UTC 24 |
35510110547 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.3491241591 |
|
|
Aug 25 05:21:39 AM UTC 24 |
Aug 25 05:28:55 AM UTC 24 |
14274873880 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.367433223 |
|
|
Aug 25 05:21:30 AM UTC 24 |
Aug 25 05:29:08 AM UTC 24 |
23447145701 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_bijection.1004190772 |
|
|
Aug 25 05:06:27 AM UTC 24 |
Aug 25 05:29:18 AM UTC 24 |
67071810709 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.845243577 |
|
|
Aug 25 05:16:55 AM UTC 24 |
Aug 25 05:29:20 AM UTC 24 |
23559775418 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.2986081052 |
|
|
Aug 25 05:28:27 AM UTC 24 |
Aug 25 05:29:22 AM UTC 24 |
3369300939 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access.3324211791 |
|
|
Aug 25 05:28:47 AM UTC 24 |
Aug 25 05:29:36 AM UTC 24 |
812988394 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.2214743337 |
|
|
Aug 25 05:29:37 AM UTC 24 |
Aug 25 05:29:43 AM UTC 24 |
1404221419 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_executable.4070297037 |
|
|
Aug 25 05:20:17 AM UTC 24 |
Aug 25 05:29:46 AM UTC 24 |
36087792567 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.935770920 |
|
|
Aug 25 05:27:50 AM UTC 24 |
Aug 25 05:29:48 AM UTC 24 |
29604485011 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.284376744 |
|
|
Aug 25 05:28:52 AM UTC 24 |
Aug 25 05:29:55 AM UTC 24 |
776475307 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.1433713363 |
|
|
Aug 25 05:29:08 AM UTC 24 |
Aug 25 05:30:00 AM UTC 24 |
4909711462 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_bijection.2217696320 |
|
|
Aug 25 04:40:37 AM UTC 24 |
Aug 25 05:30:01 AM UTC 24 |
414605500116 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_alert_test.2614770929 |
|
|
Aug 25 05:30:01 AM UTC 24 |
Aug 25 05:30:03 AM UTC 24 |
23248777 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.271154092 |
|
|
Aug 25 05:25:43 AM UTC 24 |
Aug 25 05:30:04 AM UTC 24 |
6051214964 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.492281163 |
|
|
Aug 25 05:22:51 AM UTC 24 |
Aug 25 05:30:12 AM UTC 24 |
27674355912 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_smoke.1708331542 |
|
|
Aug 25 05:30:01 AM UTC 24 |
Aug 25 05:30:14 AM UTC 24 |
767623276 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.462355005 |
|
|
Aug 25 05:22:28 AM UTC 24 |
Aug 25 05:30:15 AM UTC 24 |
49065894967 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.3300051874 |
|
|
Aug 25 05:28:55 AM UTC 24 |
Aug 25 05:30:22 AM UTC 24 |
3192521621 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.1329375961 |
|
|
Aug 25 05:23:46 AM UTC 24 |
Aug 25 05:30:31 AM UTC 24 |
39788860488 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.184152420 |
|
|
Aug 25 05:29:49 AM UTC 24 |
Aug 25 05:30:39 AM UTC 24 |
1253539385 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access.197376848 |
|
|
Aug 25 05:30:15 AM UTC 24 |
Aug 25 05:30:40 AM UTC 24 |
1683395537 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_regwen.2281963012 |
|
|
Aug 25 05:09:24 AM UTC 24 |
Aug 25 05:30:45 AM UTC 24 |
27462531588 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.2713828704 |
|
|
Aug 25 05:09:11 AM UTC 24 |
Aug 25 05:31:10 AM UTC 24 |
29072748677 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.2228600502 |
|
|
Aug 25 05:30:23 AM UTC 24 |
Aug 25 05:31:29 AM UTC 24 |
4867153615 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.330127251 |
|
|
Aug 25 05:31:30 AM UTC 24 |
Aug 25 05:31:37 AM UTC 24 |
675829850 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.1528507955 |
|
|
Aug 25 05:29:47 AM UTC 24 |
Aug 25 05:31:40 AM UTC 24 |
10128466221 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.3534188604 |
|
|
Aug 25 04:53:31 AM UTC 24 |
Aug 25 05:31:40 AM UTC 24 |
90663165626 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.533658473 |
|
|
Aug 25 05:02:21 AM UTC 24 |
Aug 25 05:32:10 AM UTC 24 |
53625628756 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.2954852185 |
|
|
Aug 25 05:30:40 AM UTC 24 |
Aug 25 05:32:10 AM UTC 24 |
20296573441 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.662147515 |
|
|
Aug 25 05:30:32 AM UTC 24 |
Aug 25 05:32:12 AM UTC 24 |
792129672 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_alert_test.3687080574 |
|
|
Aug 25 05:32:11 AM UTC 24 |
Aug 25 05:32:13 AM UTC 24 |
58273694 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.376553261 |
|
|
Aug 25 05:27:53 AM UTC 24 |
Aug 25 05:32:21 AM UTC 24 |
11000001902 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.28929917 |
|
|
Aug 25 05:31:41 AM UTC 24 |
Aug 25 05:32:26 AM UTC 24 |
677484342 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.429522896 |
|
|
Aug 25 05:23:40 AM UTC 24 |
Aug 25 05:32:26 AM UTC 24 |
9817376668 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_executable.3808518943 |
|
|
Aug 25 05:17:35 AM UTC 24 |
Aug 25 05:32:29 AM UTC 24 |
5053999403 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_smoke.3825622174 |
|
|
Aug 25 05:32:13 AM UTC 24 |
Aug 25 05:32:38 AM UTC 24 |
3749987469 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_regwen.2612963307 |
|
|
Aug 25 05:20:18 AM UTC 24 |
Aug 25 05:32:57 AM UTC 24 |
8756999106 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.1429221027 |
|
|
Aug 25 05:28:43 AM UTC 24 |
Aug 25 05:33:02 AM UTC 24 |
3227618477 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_bijection.1772069249 |
|
|
Aug 25 04:44:55 AM UTC 24 |
Aug 25 05:33:34 AM UTC 24 |
371418901650 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_executable.1011469572 |
|
|
Aug 25 05:24:19 AM UTC 24 |
Aug 25 05:33:40 AM UTC 24 |
34455593200 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access.3488036671 |
|
|
Aug 25 05:32:28 AM UTC 24 |
Aug 25 05:33:48 AM UTC 24 |
969697083 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.4269201851 |
|
|
Aug 25 05:32:58 AM UTC 24 |
Aug 25 05:33:50 AM UTC 24 |
2978965297 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.1418172039 |
|
|
Aug 25 05:10:53 AM UTC 24 |
Aug 25 05:33:52 AM UTC 24 |
12742083579 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.164134760 |
|
|
Aug 25 05:33:51 AM UTC 24 |
Aug 25 05:33:58 AM UTC 24 |
705711675 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_regwen.1621759045 |
|
|
Aug 25 05:24:22 AM UTC 24 |
Aug 25 05:34:01 AM UTC 24 |
85911182305 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2331348216 |
|
|
Aug 25 05:34:02 AM UTC 24 |
Aug 25 05:34:29 AM UTC 24 |
3544966786 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.498112648 |
|
|
Aug 25 05:30:13 AM UTC 24 |
Aug 25 05:34:35 AM UTC 24 |
2956838823 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_alert_test.2020748480 |
|
|
Aug 25 05:34:35 AM UTC 24 |
Aug 25 05:34:37 AM UTC 24 |
44012876 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.4000392647 |
|
|
Aug 25 05:31:41 AM UTC 24 |
Aug 25 05:34:40 AM UTC 24 |
5006622470 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.2082748582 |
|
|
Aug 25 05:33:03 AM UTC 24 |
Aug 25 05:34:42 AM UTC 24 |
18100005965 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_smoke.3477659084 |
|
|
Aug 25 05:34:38 AM UTC 24 |
Aug 25 05:34:51 AM UTC 24 |
3413093466 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.1150164519 |
|
|
Aug 25 05:32:39 AM UTC 24 |
Aug 25 05:34:53 AM UTC 24 |
6346980396 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_executable.2414175552 |
|
|
Aug 25 05:15:53 AM UTC 24 |
Aug 25 05:34:59 AM UTC 24 |
54837310189 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access.3008770972 |
|
|
Aug 25 05:34:54 AM UTC 24 |
Aug 25 05:35:05 AM UTC 24 |
518871760 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all.4153808235 |
|
|
Aug 25 05:03:26 AM UTC 24 |
Aug 25 05:35:12 AM UTC 24 |
20086756260 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.412788540 |
|
|
Aug 25 05:27:17 AM UTC 24 |
Aug 25 05:35:24 AM UTC 24 |
57545714889 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.2480073535 |
|
|
Aug 25 05:35:06 AM UTC 24 |
Aug 25 05:35:26 AM UTC 24 |
2860491931 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.1084294562 |
|
|
Aug 25 05:33:59 AM UTC 24 |
Aug 25 05:35:45 AM UTC 24 |
2737325701 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.3403602784 |
|
|
Aug 25 05:17:33 AM UTC 24 |
Aug 25 05:35:47 AM UTC 24 |
42479072397 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.3765235671 |
|
|
Aug 25 05:19:45 AM UTC 24 |
Aug 25 05:35:54 AM UTC 24 |
132667463095 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_executable.1460772525 |
|
|
Aug 25 05:22:31 AM UTC 24 |
Aug 25 05:35:59 AM UTC 24 |
26924428167 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.3045877486 |
|
|
Aug 25 05:35:56 AM UTC 24 |
Aug 25 05:36:02 AM UTC 24 |
844900270 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.1547133590 |
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|
Aug 25 05:35:27 AM UTC 24 |
Aug 25 05:36:10 AM UTC 24 |
24273698152 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.2999039005 |
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|
Aug 25 05:32:14 AM UTC 24 |
Aug 25 05:36:10 AM UTC 24 |
8914760567 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.1068694155 |
|
|
Aug 25 05:35:12 AM UTC 24 |
Aug 25 05:36:13 AM UTC 24 |
757421475 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_alert_test.57984299 |
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|
Aug 25 05:36:14 AM UTC 24 |
Aug 25 05:36:16 AM UTC 24 |
31279986 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_executable.3927025346 |
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|
Aug 25 05:00:26 AM UTC 24 |
Aug 25 05:36:25 AM UTC 24 |
123678269791 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all.1846387738 |
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|
Aug 25 04:49:51 AM UTC 24 |
Aug 25 05:36:29 AM UTC 24 |
487658135471 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_smoke.352406932 |
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|
Aug 25 05:36:17 AM UTC 24 |
Aug 25 05:36:41 AM UTC 24 |
3264919886 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.429148532 |
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|
Aug 25 05:32:31 AM UTC 24 |
Aug 25 05:37:07 AM UTC 24 |
3722183359 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.2429069360 |
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|
Aug 25 04:20:39 AM UTC 24 |
Aug 25 05:37:09 AM UTC 24 |
196788129172 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.161182006 |
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|
Aug 25 05:33:53 AM UTC 24 |
Aug 25 05:37:10 AM UTC 24 |
2636118469 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.23880478 |
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|
Aug 25 05:29:44 AM UTC 24 |
Aug 25 05:37:17 AM UTC 24 |
14557105639 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.3993413250 |
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|
Aug 25 05:26:19 AM UTC 24 |
Aug 25 05:37:21 AM UTC 24 |
70439759134 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.1364199539 |
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|
Aug 25 05:35:25 AM UTC 24 |
Aug 25 05:37:55 AM UTC 24 |
44079999027 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3599688064 |
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|
Aug 25 05:36:11 AM UTC 24 |
Aug 25 05:38:07 AM UTC 24 |
7676694216 ps |