| T307 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.3206143013 |
|
|
Sep 01 10:33:08 AM UTC 24 |
Sep 01 10:35:21 AM UTC 24 |
2905064627 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.2195729366 |
|
|
Sep 01 10:33:47 AM UTC 24 |
Sep 01 10:35:24 AM UTC 24 |
2034998047 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.1291389484 |
|
|
Sep 01 10:35:22 AM UTC 24 |
Sep 01 10:35:53 AM UTC 24 |
727878015 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_bijection.14445117 |
|
|
Sep 01 09:55:58 AM UTC 24 |
Sep 01 10:35:59 AM UTC 24 |
151403689416 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.2130624263 |
|
|
Sep 01 10:32:56 AM UTC 24 |
Sep 01 10:36:02 AM UTC 24 |
30817535629 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.1528197404 |
|
|
Sep 01 10:33:50 AM UTC 24 |
Sep 01 10:36:05 AM UTC 24 |
9651887306 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.3969493732 |
|
|
Sep 01 10:36:06 AM UTC 24 |
Sep 01 10:36:12 AM UTC 24 |
1351437331 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.1873925562 |
|
|
Sep 01 10:35:10 AM UTC 24 |
Sep 01 10:36:18 AM UTC 24 |
1511566648 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.4033856221 |
|
|
Sep 01 10:26:22 AM UTC 24 |
Sep 01 10:36:29 AM UTC 24 |
9850272827 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access.1303755186 |
|
|
Sep 01 10:34:59 AM UTC 24 |
Sep 01 10:36:34 AM UTC 24 |
4713536241 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_bijection.4251842184 |
|
|
Sep 01 10:26:33 AM UTC 24 |
Sep 01 10:36:42 AM UTC 24 |
16740646498 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.3417539094 |
|
|
Sep 01 10:35:25 AM UTC 24 |
Sep 01 10:36:44 AM UTC 24 |
12422712928 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_alert_test.265817876 |
|
|
Sep 01 10:36:43 AM UTC 24 |
Sep 01 10:36:45 AM UTC 24 |
39064309 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_smoke.3199989085 |
|
|
Sep 01 10:36:44 AM UTC 24 |
Sep 01 10:37:06 AM UTC 24 |
3897831354 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.3917252025 |
|
|
Sep 01 10:33:47 AM UTC 24 |
Sep 01 10:37:12 AM UTC 24 |
33010054606 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1146211282 |
|
|
Sep 01 10:36:30 AM UTC 24 |
Sep 01 10:37:37 AM UTC 24 |
2066765676 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.2994810528 |
|
|
Sep 01 10:34:58 AM UTC 24 |
Sep 01 10:37:43 AM UTC 24 |
2521452485 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.1281792281 |
|
|
Sep 01 10:29:49 AM UTC 24 |
Sep 01 10:38:01 AM UTC 24 |
6669344040 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access.3265716814 |
|
|
Sep 01 10:37:38 AM UTC 24 |
Sep 01 10:38:04 AM UTC 24 |
602741864 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.2311224543 |
|
|
Sep 01 10:36:18 AM UTC 24 |
Sep 01 10:38:09 AM UTC 24 |
6281987950 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.477197214 |
|
|
Sep 01 10:35:53 AM UTC 24 |
Sep 01 10:38:29 AM UTC 24 |
17714718693 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.323195398 |
|
|
Sep 01 10:23:11 AM UTC 24 |
Sep 01 10:39:28 AM UTC 24 |
35999998336 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.2602662231 |
|
|
Sep 01 10:38:05 AM UTC 24 |
Sep 01 10:39:34 AM UTC 24 |
798650876 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.3655460318 |
|
|
Sep 01 10:36:13 AM UTC 24 |
Sep 01 10:39:53 AM UTC 24 |
13552562115 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.530934467 |
|
|
Sep 01 10:38:02 AM UTC 24 |
Sep 01 10:39:56 AM UTC 24 |
816635539 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.1935745267 |
|
|
Sep 01 10:39:54 AM UTC 24 |
Sep 01 10:40:01 AM UTC 24 |
391392650 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_executable.1764139321 |
|
|
Sep 01 10:27:59 AM UTC 24 |
Sep 01 10:40:22 AM UTC 24 |
12750623345 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_bijection.3857340075 |
|
|
Sep 01 09:58:20 AM UTC 24 |
Sep 01 10:40:33 AM UTC 24 |
93986748130 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.1264204126 |
|
|
Sep 01 10:03:21 AM UTC 24 |
Sep 01 10:40:43 AM UTC 24 |
29804196609 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_alert_test.1539494536 |
|
|
Sep 01 10:40:44 AM UTC 24 |
Sep 01 10:40:46 AM UTC 24 |
29012779 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.453831325 |
|
|
Sep 01 10:40:22 AM UTC 24 |
Sep 01 10:40:46 AM UTC 24 |
4391622711 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_smoke.1970820854 |
|
|
Sep 01 10:40:47 AM UTC 24 |
Sep 01 10:41:07 AM UTC 24 |
2276525858 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all.1724412028 |
|
|
Sep 01 10:19:29 AM UTC 24 |
Sep 01 10:41:17 AM UTC 24 |
97577427081 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.1732814185 |
|
|
Sep 01 10:08:53 AM UTC 24 |
Sep 01 10:41:24 AM UTC 24 |
34919798808 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.1812817575 |
|
|
Sep 01 10:38:09 AM UTC 24 |
Sep 01 10:41:33 AM UTC 24 |
135429941697 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.864573582 |
|
|
Sep 01 10:31:28 AM UTC 24 |
Sep 01 10:41:41 AM UTC 24 |
35100659846 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access.3495801358 |
|
|
Sep 01 10:41:25 AM UTC 24 |
Sep 01 10:41:45 AM UTC 24 |
1682319234 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.4091470128 |
|
|
Sep 01 10:21:28 AM UTC 24 |
Sep 01 10:41:51 AM UTC 24 |
29235652611 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.2546109094 |
|
|
Sep 01 10:40:02 AM UTC 24 |
Sep 01 10:42:01 AM UTC 24 |
17568932290 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.1491348585 |
|
|
Sep 01 10:32:05 AM UTC 24 |
Sep 01 10:42:19 AM UTC 24 |
18581400648 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.2917543734 |
|
|
Sep 01 10:41:42 AM UTC 24 |
Sep 01 10:42:31 AM UTC 24 |
751302653 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.2422343079 |
|
|
Sep 01 10:35:07 AM UTC 24 |
Sep 01 10:42:51 AM UTC 24 |
15794299122 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_executable.422086123 |
|
|
Sep 01 10:33:33 AM UTC 24 |
Sep 01 10:42:55 AM UTC 24 |
18664007627 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.1508210511 |
|
|
Sep 01 10:41:46 AM UTC 24 |
Sep 01 10:42:57 AM UTC 24 |
3168903209 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.1461943561 |
|
|
Sep 01 10:42:51 AM UTC 24 |
Sep 01 10:43:01 AM UTC 24 |
4811911346 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.1803836567 |
|
|
Sep 01 10:37:13 AM UTC 24 |
Sep 01 10:43:03 AM UTC 24 |
4603748371 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.2479757837 |
|
|
Sep 01 10:41:53 AM UTC 24 |
Sep 01 10:43:29 AM UTC 24 |
9201917876 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_alert_test.1791025599 |
|
|
Sep 01 10:43:30 AM UTC 24 |
Sep 01 10:43:32 AM UTC 24 |
21326626 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2056538701 |
|
|
Sep 01 10:43:01 AM UTC 24 |
Sep 01 10:43:36 AM UTC 24 |
614261890 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_executable.1842627333 |
|
|
Sep 01 10:42:20 AM UTC 24 |
Sep 01 10:43:41 AM UTC 24 |
8826437438 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.3797578573 |
|
|
Sep 01 10:34:45 AM UTC 24 |
Sep 01 10:43:58 AM UTC 24 |
90931388505 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_smoke.1921435310 |
|
|
Sep 01 10:43:33 AM UTC 24 |
Sep 01 10:44:06 AM UTC 24 |
5664022865 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.2384035361 |
|
|
Sep 01 10:39:57 AM UTC 24 |
Sep 01 10:44:11 AM UTC 24 |
46179207073 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.1592523631 |
|
|
Sep 01 10:44:12 AM UTC 24 |
Sep 01 10:44:57 AM UTC 24 |
3095680654 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_executable.2223797944 |
|
|
Sep 01 10:21:36 AM UTC 24 |
Sep 01 10:45:16 AM UTC 24 |
23994694519 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access.4209900527 |
|
|
Sep 01 10:44:09 AM UTC 24 |
Sep 01 10:45:03 AM UTC 24 |
2606548781 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.164378733 |
|
|
Sep 01 10:42:58 AM UTC 24 |
Sep 01 10:45:07 AM UTC 24 |
5263613724 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.4058234390 |
|
|
Sep 01 10:41:18 AM UTC 24 |
Sep 01 10:45:33 AM UTC 24 |
4768069798 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.1416467989 |
|
|
Sep 01 10:44:58 AM UTC 24 |
Sep 01 10:45:36 AM UTC 24 |
2806322491 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.2117062545 |
|
|
Sep 01 10:42:56 AM UTC 24 |
Sep 01 10:45:41 AM UTC 24 |
10954982197 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.3936216708 |
|
|
Sep 01 10:45:36 AM UTC 24 |
Sep 01 10:45:43 AM UTC 24 |
1353090801 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.2949814770 |
|
|
Sep 01 10:45:04 AM UTC 24 |
Sep 01 10:46:03 AM UTC 24 |
5531798986 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3883113226 |
|
|
Sep 01 10:46:03 AM UTC 24 |
Sep 01 10:46:32 AM UTC 24 |
1792322252 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.2003666200 |
|
|
Sep 01 10:37:44 AM UTC 24 |
Sep 01 10:46:39 AM UTC 24 |
18078830721 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_alert_test.2185217166 |
|
|
Sep 01 10:46:40 AM UTC 24 |
Sep 01 10:46:42 AM UTC 24 |
64736147 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_bijection.367729399 |
|
|
Sep 01 10:23:11 AM UTC 24 |
Sep 01 10:46:51 AM UTC 24 |
57654779862 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_smoke.4117877788 |
|
|
Sep 01 10:46:43 AM UTC 24 |
Sep 01 10:46:56 AM UTC 24 |
721165574 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.2144915382 |
|
|
Sep 01 10:24:43 AM UTC 24 |
Sep 01 10:47:18 AM UTC 24 |
100838960996 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_bijection.1905722163 |
|
|
Sep 01 10:31:42 AM UTC 24 |
Sep 01 10:47:25 AM UTC 24 |
154201793263 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.1839303878 |
|
|
Sep 01 10:46:52 AM UTC 24 |
Sep 01 10:47:29 AM UTC 24 |
1519691024 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.3390949273 |
|
|
Sep 01 10:45:44 AM UTC 24 |
Sep 01 10:47:38 AM UTC 24 |
2948383983 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_regwen.1783889338 |
|
|
Sep 01 10:33:37 AM UTC 24 |
Sep 01 10:47:40 AM UTC 24 |
32266958400 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.2110663880 |
|
|
Sep 01 10:47:39 AM UTC 24 |
Sep 01 10:47:50 AM UTC 24 |
708582369 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access.2027292309 |
|
|
Sep 01 10:47:26 AM UTC 24 |
Sep 01 10:47:52 AM UTC 24 |
1680607722 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.3220269059 |
|
|
Sep 01 10:47:41 AM UTC 24 |
Sep 01 10:48:12 AM UTC 24 |
1893431651 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.1078038332 |
|
|
Sep 01 10:41:34 AM UTC 24 |
Sep 01 10:48:33 AM UTC 24 |
7436456141 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.3948521107 |
|
|
Sep 01 10:44:08 AM UTC 24 |
Sep 01 10:49:05 AM UTC 24 |
19844892716 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.432808411 |
|
|
Sep 01 10:49:06 AM UTC 24 |
Sep 01 10:49:12 AM UTC 24 |
359434384 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.2693207758 |
|
|
Sep 01 10:47:51 AM UTC 24 |
Sep 01 10:49:34 AM UTC 24 |
10757239243 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.1002412296 |
|
|
Sep 01 10:30:31 AM UTC 24 |
Sep 01 10:49:34 AM UTC 24 |
13463889218 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.2877712628 |
|
|
Sep 01 10:38:29 AM UTC 24 |
Sep 01 10:49:58 AM UTC 24 |
51912457837 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.46301225 |
|
|
Sep 01 10:49:36 AM UTC 24 |
Sep 01 10:50:03 AM UTC 24 |
1022198165 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_alert_test.4245083134 |
|
|
Sep 01 10:50:04 AM UTC 24 |
Sep 01 10:50:06 AM UTC 24 |
44556083 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.3009503869 |
|
|
Sep 01 10:13:45 AM UTC 24 |
Sep 01 10:50:27 AM UTC 24 |
124281750193 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.1160911715 |
|
|
Sep 01 10:44:09 AM UTC 24 |
Sep 01 10:50:29 AM UTC 24 |
69114980922 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_regwen.2838189364 |
|
|
Sep 01 10:28:11 AM UTC 24 |
Sep 01 10:50:42 AM UTC 24 |
25997906086 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.1673898799 |
|
|
Sep 01 10:11:33 AM UTC 24 |
Sep 01 10:50:47 AM UTC 24 |
115455793324 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.549226448 |
|
|
Sep 01 10:42:02 AM UTC 24 |
Sep 01 10:50:50 AM UTC 24 |
10346611739 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.999843801 |
|
|
Sep 01 10:36:46 AM UTC 24 |
Sep 01 10:51:13 AM UTC 24 |
59230396081 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.1253282203 |
|
|
Sep 01 10:49:35 AM UTC 24 |
Sep 01 10:51:13 AM UTC 24 |
2829682354 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access.1143814752 |
|
|
Sep 01 10:50:48 AM UTC 24 |
Sep 01 10:51:17 AM UTC 24 |
2751456402 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.1635051137 |
|
|
Sep 01 10:45:42 AM UTC 24 |
Sep 01 10:51:30 AM UTC 24 |
16423964978 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.3562200312 |
|
|
Sep 01 10:45:08 AM UTC 24 |
Sep 01 10:51:33 AM UTC 24 |
7382385779 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_smoke.2470639887 |
|
|
Sep 01 10:50:07 AM UTC 24 |
Sep 01 10:51:39 AM UTC 24 |
1225563087 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_executable.4124151123 |
|
|
Sep 01 10:39:29 AM UTC 24 |
Sep 01 10:51:40 AM UTC 24 |
16185655071 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.2034890332 |
|
|
Sep 01 10:51:41 AM UTC 24 |
Sep 01 10:51:48 AM UTC 24 |
1298540543 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.551054529 |
|
|
Sep 01 10:51:18 AM UTC 24 |
Sep 01 10:52:05 AM UTC 24 |
5234415999 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.2845949360 |
|
|
Sep 01 10:49:13 AM UTC 24 |
Sep 01 10:52:22 AM UTC 24 |
31380149168 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.2341214211 |
|
|
Sep 01 10:51:14 AM UTC 24 |
Sep 01 10:52:22 AM UTC 24 |
3217563935 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2904626693 |
|
|
Sep 01 10:52:23 AM UTC 24 |
Sep 01 10:52:39 AM UTC 24 |
1050248753 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_alert_test.510316690 |
|
|
Sep 01 10:52:39 AM UTC 24 |
Sep 01 10:52:41 AM UTC 24 |
20506212 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.1564576824 |
|
|
Sep 01 10:47:30 AM UTC 24 |
Sep 01 10:52:49 AM UTC 24 |
5227942961 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.398735636 |
|
|
Sep 01 10:51:14 AM UTC 24 |
Sep 01 10:52:51 AM UTC 24 |
784346252 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_regwen.491753043 |
|
|
Sep 01 10:36:03 AM UTC 24 |
Sep 01 10:52:55 AM UTC 24 |
49012972016 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_regwen.2384825806 |
|
|
Sep 01 10:51:40 AM UTC 24 |
Sep 01 10:52:58 AM UTC 24 |
2324586371 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_executable.934816020 |
|
|
Sep 01 10:36:00 AM UTC 24 |
Sep 01 10:53:01 AM UTC 24 |
138983575205 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_smoke.265014374 |
|
|
Sep 01 10:52:42 AM UTC 24 |
Sep 01 10:53:07 AM UTC 24 |
570741092 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.767950257 |
|
|
Sep 01 10:52:06 AM UTC 24 |
Sep 01 10:53:12 AM UTC 24 |
1465632945 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access.1802536324 |
|
|
Sep 01 10:52:59 AM UTC 24 |
Sep 01 10:53:35 AM UTC 24 |
1671210701 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_regwen.455784126 |
|
|
Sep 01 10:48:34 AM UTC 24 |
Sep 01 10:53:58 AM UTC 24 |
58522292268 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.3881852354 |
|
|
Sep 01 10:53:13 AM UTC 24 |
Sep 01 10:54:31 AM UTC 24 |
765831066 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.265986530 |
|
|
Sep 01 10:47:19 AM UTC 24 |
Sep 01 10:54:42 AM UTC 24 |
41974747150 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.2656754127 |
|
|
Sep 01 10:53:08 AM UTC 24 |
Sep 01 10:54:45 AM UTC 24 |
1580688807 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.2292548393 |
|
|
Sep 01 10:54:46 AM UTC 24 |
Sep 01 10:54:53 AM UTC 24 |
345342595 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.2895643351 |
|
|
Sep 01 10:51:49 AM UTC 24 |
Sep 01 10:55:05 AM UTC 24 |
24671332533 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.3392414563 |
|
|
Sep 01 10:50:43 AM UTC 24 |
Sep 01 10:55:13 AM UTC 24 |
17960015658 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1101796968 |
|
|
Sep 01 10:55:14 AM UTC 24 |
Sep 01 10:55:31 AM UTC 24 |
550721969 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.1017473778 |
|
|
Sep 01 10:53:36 AM UTC 24 |
Sep 01 10:55:47 AM UTC 24 |
10019012287 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_alert_test.2463533467 |
|
|
Sep 01 10:55:49 AM UTC 24 |
Sep 01 10:55:51 AM UTC 24 |
21796730 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_smoke.464443279 |
|
|
Sep 01 10:55:52 AM UTC 24 |
Sep 01 10:56:06 AM UTC 24 |
445808612 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_executable.1127825576 |
|
|
Sep 01 10:45:17 AM UTC 24 |
Sep 01 10:56:21 AM UTC 24 |
7666259224 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.879719118 |
|
|
Sep 01 10:50:51 AM UTC 24 |
Sep 01 10:57:04 AM UTC 24 |
58502092291 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_bijection.3427763383 |
|
|
Sep 01 10:41:08 AM UTC 24 |
Sep 01 10:57:05 AM UTC 24 |
120185034848 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access.3218436912 |
|
|
Sep 01 10:57:05 AM UTC 24 |
Sep 01 10:57:26 AM UTC 24 |
3496946006 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.1990057430 |
|
|
Sep 01 10:57:27 AM UTC 24 |
Sep 01 10:57:43 AM UTC 24 |
2838775754 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.1627106361 |
|
|
Sep 01 10:52:56 AM UTC 24 |
Sep 01 10:57:44 AM UTC 24 |
58836764353 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.3573830568 |
|
|
Sep 01 10:57:46 AM UTC 24 |
Sep 01 10:58:01 AM UTC 24 |
3510035757 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.1605998218 |
|
|
Sep 01 10:57:44 AM UTC 24 |
Sep 01 10:58:15 AM UTC 24 |
4204659041 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.139191062 |
|
|
Sep 01 10:54:54 AM UTC 24 |
Sep 01 10:58:39 AM UTC 24 |
27674781402 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.3416893885 |
|
|
Sep 01 10:55:06 AM UTC 24 |
Sep 01 10:58:42 AM UTC 24 |
5002818242 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.2364363733 |
|
|
Sep 01 10:05:53 AM UTC 24 |
Sep 01 10:58:54 AM UTC 24 |
233226680961 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.1304432135 |
|
|
Sep 01 10:58:50 AM UTC 24 |
Sep 01 10:58:56 AM UTC 24 |
691006069 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.1409994568 |
|
|
Sep 01 10:53:02 AM UTC 24 |
Sep 01 10:59:30 AM UTC 24 |
20061257258 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_alert_test.3590085637 |
|
|
Sep 01 10:59:31 AM UTC 24 |
Sep 01 10:59:33 AM UTC 24 |
42648148 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.440690564 |
|
|
Sep 01 10:59:03 AM UTC 24 |
Sep 01 10:59:42 AM UTC 24 |
699092172 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_smoke.4059229915 |
|
|
Sep 01 10:59:34 AM UTC 24 |
Sep 01 11:00:57 AM UTC 24 |
1212604803 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_regwen.1669029610 |
|
|
Sep 01 10:39:35 AM UTC 24 |
Sep 01 11:01:11 AM UTC 24 |
23057172149 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access.1177575061 |
|
|
Sep 01 11:01:12 AM UTC 24 |
Sep 01 11:01:27 AM UTC 24 |
752777542 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.3858501448 |
|
|
Sep 01 10:43:38 AM UTC 24 |
Sep 01 11:01:30 AM UTC 24 |
22508572882 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_regwen.3128829531 |
|
|
Sep 01 10:42:32 AM UTC 24 |
Sep 01 11:01:38 AM UTC 24 |
8127143814 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_bijection.3523226514 |
|
|
Sep 01 10:37:07 AM UTC 24 |
Sep 01 11:01:48 AM UTC 24 |
132254278006 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.9927714 |
|
|
Sep 01 10:59:03 AM UTC 24 |
Sep 01 11:02:04 AM UTC 24 |
18215342918 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.1048452374 |
|
|
Sep 01 10:58:50 AM UTC 24 |
Sep 01 11:02:26 AM UTC 24 |
7212594618 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.341783872 |
|
|
Sep 01 11:01:49 AM UTC 24 |
Sep 01 11:02:33 AM UTC 24 |
65458361999 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_bijection.3269143466 |
|
|
Sep 01 10:46:57 AM UTC 24 |
Sep 01 11:02:36 AM UTC 24 |
202023156429 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.391944811 |
|
|
Sep 01 11:02:37 AM UTC 24 |
Sep 01 11:02:44 AM UTC 24 |
656419596 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.3680302811 |
|
|
Sep 01 11:01:39 AM UTC 24 |
Sep 01 11:02:52 AM UTC 24 |
5391341486 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.3256992756 |
|
|
Sep 01 10:51:31 AM UTC 24 |
Sep 01 11:02:56 AM UTC 24 |
13332956875 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.2995587863 |
|
|
Sep 01 11:01:31 AM UTC 24 |
Sep 01 11:03:02 AM UTC 24 |
6344508319 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3613132772 |
|
|
Sep 01 11:02:57 AM UTC 24 |
Sep 01 11:03:32 AM UTC 24 |
832086359 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all.1440113778 |
|
|
Sep 01 09:58:09 AM UTC 24 |
Sep 01 11:03:34 AM UTC 24 |
120018567373 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_alert_test.1795086445 |
|
|
Sep 01 11:03:33 AM UTC 24 |
Sep 01 11:03:36 AM UTC 24 |
15154383 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.3213755982 |
|
|
Sep 01 10:57:06 AM UTC 24 |
Sep 01 11:04:01 AM UTC 24 |
49144248583 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_bijection.1423563122 |
|
|
Sep 01 10:34:57 AM UTC 24 |
Sep 01 11:04:04 AM UTC 24 |
20289110400 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.652349398 |
|
|
Sep 01 10:56:27 AM UTC 24 |
Sep 01 11:04:06 AM UTC 24 |
5431686822 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_regwen.654932304 |
|
|
Sep 01 10:54:43 AM UTC 24 |
Sep 01 11:04:18 AM UTC 24 |
63380517313 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.3676421840 |
|
|
Sep 01 11:02:53 AM UTC 24 |
Sep 01 11:04:26 AM UTC 24 |
5801915556 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_executable.3565313879 |
|
|
Sep 01 10:48:13 AM UTC 24 |
Sep 01 11:04:31 AM UTC 24 |
69180227739 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_smoke.3382553832 |
|
|
Sep 01 11:03:35 AM UTC 24 |
Sep 01 11:04:32 AM UTC 24 |
6173520588 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access.324278090 |
|
|
Sep 01 11:04:07 AM UTC 24 |
Sep 01 11:04:35 AM UTC 24 |
911792646 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.2337008112 |
|
|
Sep 01 10:56:07 AM UTC 24 |
Sep 01 11:04:44 AM UTC 24 |
58250933299 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.1106893839 |
|
|
Sep 01 10:50:28 AM UTC 24 |
Sep 01 11:04:45 AM UTC 24 |
18431375536 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.3862834778 |
|
|
Sep 01 10:47:53 AM UTC 24 |
Sep 01 11:04:58 AM UTC 24 |
29808801039 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.2981416542 |
|
|
Sep 01 11:04:59 AM UTC 24 |
Sep 01 11:05:06 AM UTC 24 |
360652519 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.419848962 |
|
|
Sep 01 11:04:27 AM UTC 24 |
Sep 01 11:05:07 AM UTC 24 |
2860098145 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.3960183751 |
|
|
Sep 01 11:04:32 AM UTC 24 |
Sep 01 11:05:14 AM UTC 24 |
2951157039 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.162366789 |
|
|
Sep 01 11:05:15 AM UTC 24 |
Sep 01 11:05:52 AM UTC 24 |
814717749 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_regwen.4270183870 |
|
|
Sep 01 10:45:34 AM UTC 24 |
Sep 01 11:05:59 AM UTC 24 |
62866097445 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_alert_test.3457034334 |
|
|
Sep 01 11:06:00 AM UTC 24 |
Sep 01 11:06:02 AM UTC 24 |
26364682 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.3641146525 |
|
|
Sep 01 11:04:32 AM UTC 24 |
Sep 01 11:06:04 AM UTC 24 |
15887694099 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_smoke.1361278015 |
|
|
Sep 01 11:06:03 AM UTC 24 |
Sep 01 11:06:25 AM UTC 24 |
1630804497 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.3818733150 |
|
|
Sep 01 11:04:05 AM UTC 24 |
Sep 01 11:07:37 AM UTC 24 |
6284823446 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.65579705 |
|
|
Sep 01 11:05:08 AM UTC 24 |
Sep 01 11:07:50 AM UTC 24 |
4993205329 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.3897192618 |
|
|
Sep 01 10:13:21 AM UTC 24 |
Sep 01 11:07:54 AM UTC 24 |
41749271682 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access.2816500024 |
|
|
Sep 01 11:07:51 AM UTC 24 |
Sep 01 11:08:08 AM UTC 24 |
916302634 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.1532108351 |
|
|
Sep 01 11:08:10 AM UTC 24 |
Sep 01 11:08:29 AM UTC 24 |
2838313865 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.2705335246 |
|
|
Sep 01 11:00:58 AM UTC 24 |
Sep 01 11:08:32 AM UTC 24 |
60848547428 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_executable.1936746163 |
|
|
Sep 01 10:51:34 AM UTC 24 |
Sep 01 11:08:40 AM UTC 24 |
36344890319 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.2451761422 |
|
|
Sep 01 11:01:28 AM UTC 24 |
Sep 01 11:08:52 AM UTC 24 |
15930900566 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.738247832 |
|
|
Sep 01 11:08:30 AM UTC 24 |
Sep 01 11:09:04 AM UTC 24 |
1485091259 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.1980442492 |
|
|
Sep 01 11:02:45 AM UTC 24 |
Sep 01 11:09:16 AM UTC 24 |
147643688929 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.1440185118 |
|
|
Sep 01 11:08:33 AM UTC 24 |
Sep 01 11:09:16 AM UTC 24 |
26524986162 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.3105704231 |
|
|
Sep 01 11:09:16 AM UTC 24 |
Sep 01 11:09:21 AM UTC 24 |
1399481782 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_regwen.3041593824 |
|
|
Sep 01 10:58:40 AM UTC 24 |
Sep 01 11:09:23 AM UTC 24 |
11541226549 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.2948024962 |
|
|
Sep 01 11:08:41 AM UTC 24 |
Sep 01 11:09:32 AM UTC 24 |
1883638566 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.481489865 |
|
|
Sep 01 11:02:04 AM UTC 24 |
Sep 01 11:09:34 AM UTC 24 |
9904543943 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_alert_test.1336771708 |
|
|
Sep 01 11:09:35 AM UTC 24 |
Sep 01 11:09:37 AM UTC 24 |
13396454 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.385581292 |
|
|
Sep 01 11:04:18 AM UTC 24 |
Sep 01 11:09:51 AM UTC 24 |
17246268849 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_smoke.698340443 |
|
|
Sep 01 11:09:36 AM UTC 24 |
Sep 01 11:09:56 AM UTC 24 |
942207482 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.4199033178 |
|
|
Sep 01 11:09:24 AM UTC 24 |
Sep 01 11:09:58 AM UTC 24 |
969609211 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.1258904446 |
|
|
Sep 01 10:40:47 AM UTC 24 |
Sep 01 11:10:05 AM UTC 24 |
128025803224 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access.833911849 |
|
|
Sep 01 11:10:00 AM UTC 24 |
Sep 01 11:10:16 AM UTC 24 |
1009739543 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.2715521870 |
|
|
Sep 01 10:54:00 AM UTC 24 |
Sep 01 11:10:50 AM UTC 24 |
58683570596 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.2369469336 |
|
|
Sep 01 11:10:17 AM UTC 24 |
Sep 01 11:11:20 AM UTC 24 |
745438698 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.1157475373 |
|
|
Sep 01 11:07:37 AM UTC 24 |
Sep 01 11:11:43 AM UTC 24 |
3227302611 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.3871107233 |
|
|
Sep 01 11:09:22 AM UTC 24 |
Sep 01 11:11:46 AM UTC 24 |
2548603155 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.341490593 |
|
|
Sep 01 11:10:50 AM UTC 24 |
Sep 01 11:12:13 AM UTC 24 |
819342070 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.3896972444 |
|
|
Sep 01 11:11:20 AM UTC 24 |
Sep 01 11:12:22 AM UTC 24 |
32747016947 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.3923235447 |
|
|
Sep 01 11:12:23 AM UTC 24 |
Sep 01 11:12:30 AM UTC 24 |
358228226 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.3785735627 |
|
|
Sep 01 11:05:07 AM UTC 24 |
Sep 01 11:13:04 AM UTC 24 |
57523974854 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.925197732 |
|
|
Sep 01 10:59:43 AM UTC 24 |
Sep 01 11:13:57 AM UTC 24 |
135117763937 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.4053814370 |
|
|
Sep 01 11:13:57 AM UTC 24 |
Sep 01 11:14:22 AM UTC 24 |
3850627186 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.2136838708 |
|
|
Sep 01 11:09:38 AM UTC 24 |
Sep 01 11:14:30 AM UTC 24 |
14240928636 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_alert_test.2614730264 |
|
|
Sep 01 11:14:31 AM UTC 24 |
Sep 01 11:14:33 AM UTC 24 |
68406039 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_smoke.3717343255 |
|
|
Sep 01 11:14:34 AM UTC 24 |
Sep 01 11:14:50 AM UTC 24 |
4446302247 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_bijection.1901795853 |
|
|
Sep 01 10:29:36 AM UTC 24 |
Sep 01 11:14:54 AM UTC 24 |
383723547085 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.2213539099 |
|
|
Sep 01 10:58:02 AM UTC 24 |
Sep 01 11:14:57 AM UTC 24 |
14369619966 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.3016385938 |
|
|
Sep 01 11:17:15 AM UTC 24 |
Sep 01 11:26:40 AM UTC 24 |
98940972283 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_executable.2497563908 |
|
|
Sep 01 10:54:32 AM UTC 24 |
Sep 01 11:15:00 AM UTC 24 |
66411641113 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.957078741 |
|
|
Sep 01 11:09:18 AM UTC 24 |
Sep 01 11:15:00 AM UTC 24 |
79632038153 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.2856585722 |
|
|
Sep 01 11:09:56 AM UTC 24 |
Sep 01 11:15:04 AM UTC 24 |
22703322269 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_executable.50272755 |
|
|
Sep 01 11:08:53 AM UTC 24 |
Sep 01 11:15:12 AM UTC 24 |
43119205452 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.2620510130 |
|
|
Sep 01 10:08:33 AM UTC 24 |
Sep 01 11:15:16 AM UTC 24 |
191829373169 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all.1759255580 |
|
|
Sep 01 09:51:10 AM UTC 24 |
Sep 01 11:15:22 AM UTC 24 |
48646572768 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.3308973038 |
|
|
Sep 01 11:15:13 AM UTC 24 |
Sep 01 11:15:24 AM UTC 24 |
679056815 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access.3422900456 |
|
|
Sep 01 11:15:01 AM UTC 24 |
Sep 01 11:15:27 AM UTC 24 |
2204914516 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.3246795718 |
|
|
Sep 01 11:15:04 AM UTC 24 |
Sep 01 11:15:31 AM UTC 24 |
773850412 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.4194253274 |
|
|
Sep 01 11:15:32 AM UTC 24 |
Sep 01 11:15:39 AM UTC 24 |
459989321 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_executable.882114056 |
|
|
Sep 01 11:11:47 AM UTC 24 |
Sep 01 11:15:52 AM UTC 24 |
10575246504 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_bijection.2284327624 |
|
|
Sep 01 10:50:29 AM UTC 24 |
Sep 01 11:15:53 AM UTC 24 |
21725364166 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.2124537661 |
|
|
Sep 01 11:15:17 AM UTC 24 |
Sep 01 11:15:58 AM UTC 24 |
3024948355 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.3812437908 |
|
|
Sep 01 11:06:05 AM UTC 24 |
Sep 01 11:16:08 AM UTC 24 |
59761728244 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_alert_test.638987708 |
|
|
Sep 01 11:16:09 AM UTC 24 |
Sep 01 11:16:11 AM UTC 24 |
14328956 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_executable.1193569698 |
|
|
Sep 01 11:15:25 AM UTC 24 |
Sep 01 11:16:33 AM UTC 24 |
10825013250 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.4117328659 |
|
|
Sep 01 11:13:05 AM UTC 24 |
Sep 01 11:16:35 AM UTC 24 |
9253988322 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_smoke.660092223 |
|
|
Sep 01 11:16:12 AM UTC 24 |
Sep 01 11:16:43 AM UTC 24 |
12250689727 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.4078341978 |
|
|
Sep 01 11:07:55 AM UTC 24 |
Sep 01 11:17:00 AM UTC 24 |
17234837755 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1235217311 |
|
|
Sep 01 11:15:53 AM UTC 24 |
Sep 01 11:17:15 AM UTC 24 |
2157354365 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access.2705008539 |
|
|
Sep 01 11:17:01 AM UTC 24 |
Sep 01 11:17:19 AM UTC 24 |
2155974585 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.1033947155 |
|
|
Sep 01 11:15:40 AM UTC 24 |
Sep 01 11:17:53 AM UTC 24 |
2086589203 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_regwen.4090162354 |
|
|
Sep 01 11:04:47 AM UTC 24 |
Sep 01 11:18:07 AM UTC 24 |
22258439189 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_regwen.2341033929 |
|
|
Sep 01 11:02:34 AM UTC 24 |
Sep 01 11:18:27 AM UTC 24 |
21513603747 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_bijection.1332133809 |
|
|
Sep 01 10:19:54 AM UTC 24 |
Sep 01 11:18:35 AM UTC 24 |
622635541271 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.2176935326 |
|
|
Sep 01 11:10:06 AM UTC 24 |
Sep 01 11:18:43 AM UTC 24 |
56070963253 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.4261061093 |
|
|
Sep 01 11:12:31 AM UTC 24 |
Sep 01 11:18:45 AM UTC 24 |
57701569956 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.3088141561 |
|
|
Sep 01 11:15:52 AM UTC 24 |
Sep 01 11:18:51 AM UTC 24 |
1634422301 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.1926040829 |
|
|
Sep 01 11:17:20 AM UTC 24 |
Sep 01 11:18:51 AM UTC 24 |
886553738 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.67935669 |
|
|
Sep 01 11:18:45 AM UTC 24 |
Sep 01 11:18:52 AM UTC 24 |
354981565 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.1339194866 |
|
|
Sep 01 11:16:34 AM UTC 24 |
Sep 01 11:18:52 AM UTC 24 |
2826152248 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.206965442 |
|
|
Sep 01 11:18:08 AM UTC 24 |
Sep 01 11:18:58 AM UTC 24 |
18875909553 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_alert_test.1494806931 |
|
|
Sep 01 11:18:59 AM UTC 24 |
Sep 01 11:19:01 AM UTC 24 |
41195875 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_smoke.1060913987 |
|
|
Sep 01 11:19:02 AM UTC 24 |
Sep 01 11:19:10 AM UTC 24 |
1433742502 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.1016370704 |
|
|
Sep 01 11:17:54 AM UTC 24 |
Sep 01 11:19:10 AM UTC 24 |
800177894 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2581562139 |
|
|
Sep 01 11:18:53 AM UTC 24 |
Sep 01 11:19:27 AM UTC 24 |
533671099 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.1406295929 |
|
|
Sep 01 11:14:58 AM UTC 24 |
Sep 01 11:19:45 AM UTC 24 |
3386860060 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.3452924730 |
|
|
Sep 01 11:11:44 AM UTC 24 |
Sep 01 11:19:55 AM UTC 24 |
10313887599 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.986823489 |
|
|
Sep 01 11:16:43 AM UTC 24 |
Sep 01 11:20:13 AM UTC 24 |
8211880781 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access.3741461244 |
|
|
Sep 01 11:19:46 AM UTC 24 |
Sep 01 11:20:15 AM UTC 24 |
5665504353 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.2699560551 |
|
|
Sep 01 11:20:15 AM UTC 24 |
Sep 01 11:20:49 AM UTC 24 |
2939781360 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all.1859644667 |
|
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Sep 01 10:22:33 AM UTC 24 |
Sep 01 11:20:59 AM UTC 24 |
66953529975 ps |