| T799 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.2787033402 |
|
|
Sep 01 11:57:40 AM UTC 24 |
Sep 01 12:03:30 PM UTC 24 |
104477326341 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.3613631857 |
|
|
Sep 01 11:59:32 AM UTC 24 |
Sep 01 12:03:55 PM UTC 24 |
10868626658 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.3403980706 |
|
|
Sep 01 12:03:02 PM UTC 24 |
Sep 01 12:03:59 PM UTC 24 |
3179100202 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.376246720 |
|
|
Sep 01 12:03:13 PM UTC 24 |
Sep 01 12:04:02 PM UTC 24 |
11565128443 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.3885412200 |
|
|
Sep 01 12:03:56 PM UTC 24 |
Sep 01 12:04:03 PM UTC 24 |
1412286078 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2938376278 |
|
|
Sep 01 12:04:03 PM UTC 24 |
Sep 01 12:04:13 PM UTC 24 |
158002561 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_bijection.1435637268 |
|
|
Sep 01 11:14:55 AM UTC 24 |
Sep 01 12:04:51 PM UTC 24 |
779236920652 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_alert_test.1147197342 |
|
|
Sep 01 12:04:53 PM UTC 24 |
Sep 01 12:04:55 PM UTC 24 |
35748751 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.1395329595 |
|
|
Sep 01 12:01:53 PM UTC 24 |
Sep 01 12:05:12 PM UTC 24 |
19950178765 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.1265026525 |
|
|
Sep 01 12:04:03 PM UTC 24 |
Sep 01 12:05:39 PM UTC 24 |
2738763662 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_smoke.1312854375 |
|
|
Sep 01 12:04:56 PM UTC 24 |
Sep 01 12:05:43 PM UTC 24 |
771005703 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.2739278913 |
|
|
Sep 01 11:51:19 AM UTC 24 |
Sep 01 12:06:05 PM UTC 24 |
9266491566 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all.2763353590 |
|
|
Sep 01 11:09:33 AM UTC 24 |
Sep 01 12:06:24 PM UTC 24 |
188602621457 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_bijection.2524259661 |
|
|
Sep 01 11:43:09 AM UTC 24 |
Sep 01 12:06:31 PM UTC 24 |
18109834788 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.157441278 |
|
|
Sep 01 12:00:07 PM UTC 24 |
Sep 01 12:07:01 PM UTC 24 |
6657296167 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.207202473 |
|
|
Sep 01 12:06:28 PM UTC 24 |
Sep 01 12:07:09 PM UTC 24 |
3795009237 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_bijection.729440003 |
|
|
Sep 01 11:46:56 AM UTC 24 |
Sep 01 12:07:14 PM UTC 24 |
13725218493 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access.2357686818 |
|
|
Sep 01 12:06:06 PM UTC 24 |
Sep 01 12:07:21 PM UTC 24 |
1203390003 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.1614748965 |
|
|
Sep 01 12:04:00 PM UTC 24 |
Sep 01 12:07:23 PM UTC 24 |
9468552512 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_executable.1974552977 |
|
|
Sep 01 11:54:40 AM UTC 24 |
Sep 01 12:07:27 PM UTC 24 |
9432131955 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.2981227023 |
|
|
Sep 01 12:07:24 PM UTC 24 |
Sep 01 12:07:31 PM UTC 24 |
1608015635 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.2372114608 |
|
|
Sep 01 12:03:02 PM UTC 24 |
Sep 01 12:07:33 PM UTC 24 |
31247220829 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.3281083991 |
|
|
Sep 01 12:07:02 PM UTC 24 |
Sep 01 12:07:36 PM UTC 24 |
13864039094 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.3079027518 |
|
|
Sep 01 11:53:00 AM UTC 24 |
Sep 01 12:08:06 PM UTC 24 |
111277803340 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_alert_test.3839690134 |
|
|
Sep 01 12:08:07 PM UTC 24 |
Sep 01 12:08:09 PM UTC 24 |
33889462 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.123247268 |
|
|
Sep 01 12:02:45 PM UTC 24 |
Sep 01 12:08:15 PM UTC 24 |
13471068804 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3674870445 |
|
|
Sep 01 12:07:34 PM UTC 24 |
Sep 01 12:08:15 PM UTC 24 |
1134296330 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.481692103 |
|
|
Sep 01 12:06:32 PM UTC 24 |
Sep 01 12:08:17 PM UTC 24 |
3250842460 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.2403443154 |
|
|
Sep 01 12:01:50 PM UTC 24 |
Sep 01 12:08:37 PM UTC 24 |
14429643182 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_smoke.1664836234 |
|
|
Sep 01 12:08:10 PM UTC 24 |
Sep 01 12:09:03 PM UTC 24 |
1649442373 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access.3332624843 |
|
|
Sep 01 12:08:38 PM UTC 24 |
Sep 01 12:09:13 PM UTC 24 |
889370682 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.2052142308 |
|
|
Sep 01 12:09:15 PM UTC 24 |
Sep 01 12:09:27 PM UTC 24 |
1399393735 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.2892712179 |
|
|
Sep 01 12:09:28 PM UTC 24 |
Sep 01 12:09:38 PM UTC 24 |
689374472 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.2113349186 |
|
|
Sep 01 12:07:31 PM UTC 24 |
Sep 01 12:09:45 PM UTC 24 |
1591676366 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_bijection.4194548493 |
|
|
Sep 01 11:16:36 AM UTC 24 |
Sep 01 12:09:47 PM UTC 24 |
154898058501 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all.1281733903 |
|
|
Sep 01 11:34:06 AM UTC 24 |
Sep 01 12:09:59 PM UTC 24 |
39098426272 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.3643505189 |
|
|
Sep 01 12:05:43 PM UTC 24 |
Sep 01 12:10:46 PM UTC 24 |
6230780431 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.2586266843 |
|
|
Sep 01 12:06:25 PM UTC 24 |
Sep 01 12:10:48 PM UTC 24 |
19268519223 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.3634636538 |
|
|
Sep 01 12:10:47 PM UTC 24 |
Sep 01 12:10:52 PM UTC 24 |
634897418 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.11973801 |
|
|
Sep 01 11:58:14 AM UTC 24 |
Sep 01 12:11:38 PM UTC 24 |
61247860410 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.3836630294 |
|
|
Sep 01 12:09:39 PM UTC 24 |
Sep 01 12:12:01 PM UTC 24 |
74755383267 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all.1529078713 |
|
|
Sep 01 11:05:54 AM UTC 24 |
Sep 01 12:12:13 PM UTC 24 |
177592548602 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_alert_test.418594397 |
|
|
Sep 01 12:12:15 PM UTC 24 |
Sep 01 12:12:17 PM UTC 24 |
39335693 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_regwen.2549236038 |
|
|
Sep 01 12:01:08 PM UTC 24 |
Sep 01 12:12:36 PM UTC 24 |
30996758663 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.601942852 |
|
|
Sep 01 12:11:39 PM UTC 24 |
Sep 01 12:12:36 PM UTC 24 |
5971188428 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_smoke.1072020310 |
|
|
Sep 01 12:12:18 PM UTC 24 |
Sep 01 12:12:43 PM UTC 24 |
1732578346 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_bijection.383075165 |
|
|
Sep 01 11:50:09 AM UTC 24 |
Sep 01 12:12:57 PM UTC 24 |
70541213244 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.3521303228 |
|
|
Sep 01 12:10:53 PM UTC 24 |
Sep 01 12:13:06 PM UTC 24 |
1677342216 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access.2401737017 |
|
|
Sep 01 12:12:58 PM UTC 24 |
Sep 01 12:13:12 PM UTC 24 |
735602886 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.609542904 |
|
|
Sep 01 12:07:28 PM UTC 24 |
Sep 01 12:13:17 PM UTC 24 |
43189626703 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.1463389093 |
|
|
Sep 01 12:13:18 PM UTC 24 |
Sep 01 12:13:56 PM UTC 24 |
3275086273 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.334198632 |
|
|
Sep 01 12:08:18 PM UTC 24 |
Sep 01 12:14:19 PM UTC 24 |
16918256896 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_executable.3693279709 |
|
|
Sep 01 12:07:15 PM UTC 24 |
Sep 01 12:14:25 PM UTC 24 |
77749923904 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.1820731794 |
|
|
Sep 01 12:10:49 PM UTC 24 |
Sep 01 12:14:28 PM UTC 24 |
14112542887 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.2144471957 |
|
|
Sep 01 12:00:40 PM UTC 24 |
Sep 01 12:14:29 PM UTC 24 |
16223547623 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.660249022 |
|
|
Sep 01 12:14:30 PM UTC 24 |
Sep 01 12:14:36 PM UTC 24 |
1348012947 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.1424727608 |
|
|
Sep 01 12:13:13 PM UTC 24 |
Sep 01 12:15:12 PM UTC 24 |
2719730073 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.1537592252 |
|
|
Sep 01 12:12:44 PM UTC 24 |
Sep 01 12:16:04 PM UTC 24 |
2048031075 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_executable.506614230 |
|
|
Sep 01 12:03:21 PM UTC 24 |
Sep 01 12:16:09 PM UTC 24 |
15498315268 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.3198646335 |
|
|
Sep 01 12:13:57 PM UTC 24 |
Sep 01 12:16:28 PM UTC 24 |
49925327255 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_alert_test.3817998799 |
|
|
Sep 01 12:16:29 PM UTC 24 |
Sep 01 12:16:31 PM UTC 24 |
13053013 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_bijection.3207190756 |
|
|
Sep 01 11:53:13 AM UTC 24 |
Sep 01 12:16:48 PM UTC 24 |
160648711534 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.619068416 |
|
|
Sep 01 12:16:05 PM UTC 24 |
Sep 01 12:17:32 PM UTC 24 |
2487323539 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.4285551982 |
|
|
Sep 01 12:09:04 PM UTC 24 |
Sep 01 12:17:32 PM UTC 24 |
14373315908 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_smoke.453147616 |
|
|
Sep 01 12:16:32 PM UTC 24 |
Sep 01 12:17:39 PM UTC 24 |
886707554 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.2257970259 |
|
|
Sep 01 12:15:13 PM UTC 24 |
Sep 01 12:17:57 PM UTC 24 |
1655616998 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access.1760898506 |
|
|
Sep 01 12:17:40 PM UTC 24 |
Sep 01 12:18:06 PM UTC 24 |
2278541775 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all.4272196201 |
|
|
Sep 01 11:18:53 AM UTC 24 |
Sep 01 12:18:22 PM UTC 24 |
44252936364 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.2257914405 |
|
|
Sep 01 12:18:06 PM UTC 24 |
Sep 01 12:18:29 PM UTC 24 |
3651504856 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.2492787759 |
|
|
Sep 01 12:18:22 PM UTC 24 |
Sep 01 12:18:43 PM UTC 24 |
2940628085 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.2519849432 |
|
|
Sep 01 12:13:06 PM UTC 24 |
Sep 01 12:19:02 PM UTC 24 |
21572356785 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_bijection.2239122087 |
|
|
Sep 01 11:59:32 AM UTC 24 |
Sep 01 12:19:21 PM UTC 24 |
173705183646 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.4073288670 |
|
|
Sep 01 12:18:30 PM UTC 24 |
Sep 01 12:20:04 PM UTC 24 |
36938765149 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.1978864247 |
|
|
Sep 01 12:20:05 PM UTC 24 |
Sep 01 12:20:12 PM UTC 24 |
356114679 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.3987756074 |
|
|
Sep 01 12:05:13 PM UTC 24 |
Sep 01 12:20:13 PM UTC 24 |
8818139679 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_bijection.1429190632 |
|
|
Sep 01 11:34:35 AM UTC 24 |
Sep 01 12:20:13 PM UTC 24 |
309682122719 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_executable.784766705 |
|
|
Sep 01 11:58:28 AM UTC 24 |
Sep 01 12:20:28 PM UTC 24 |
13972584532 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.19390381 |
|
|
Sep 01 12:20:14 PM UTC 24 |
Sep 01 12:20:31 PM UTC 24 |
1367335214 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_executable.520179020 |
|
|
Sep 01 12:09:48 PM UTC 24 |
Sep 01 12:20:32 PM UTC 24 |
30547059938 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_alert_test.2832094107 |
|
|
Sep 01 12:20:32 PM UTC 24 |
Sep 01 12:20:34 PM UTC 24 |
55696478 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.1726848289 |
|
|
Sep 01 12:12:37 PM UTC 24 |
Sep 01 12:20:44 PM UTC 24 |
5293956294 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.974090659 |
|
|
Sep 01 12:14:37 PM UTC 24 |
Sep 01 12:20:49 PM UTC 24 |
78750353953 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_smoke.3372981765 |
|
|
Sep 01 12:20:33 PM UTC 24 |
Sep 01 12:21:01 PM UTC 24 |
792578763 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.1199526460 |
|
|
Sep 01 12:17:33 PM UTC 24 |
Sep 01 12:21:16 PM UTC 24 |
7383449542 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_bijection.2010564769 |
|
|
Sep 01 12:08:16 PM UTC 24 |
Sep 01 12:21:16 PM UTC 24 |
166224000726 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access.1684922529 |
|
|
Sep 01 12:21:01 PM UTC 24 |
Sep 01 12:21:31 PM UTC 24 |
3613556043 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all.1679094425 |
|
|
Sep 01 11:03:03 AM UTC 24 |
Sep 01 12:21:44 PM UTC 24 |
43951583077 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.3446041806 |
|
|
Sep 01 12:21:32 PM UTC 24 |
Sep 01 12:21:46 PM UTC 24 |
2824139297 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all.2416109713 |
|
|
Sep 01 11:46:15 AM UTC 24 |
Sep 01 12:21:53 PM UTC 24 |
31141473643 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.348013564 |
|
|
Sep 01 12:20:14 PM UTC 24 |
Sep 01 12:22:04 PM UTC 24 |
9828550618 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.1933124206 |
|
|
Sep 01 12:21:18 PM UTC 24 |
Sep 01 12:22:14 PM UTC 24 |
1467780943 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_bijection.1938892431 |
|
|
Sep 01 12:12:37 PM UTC 24 |
Sep 01 12:22:14 PM UTC 24 |
97132342985 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.4164290907 |
|
|
Sep 01 12:22:14 PM UTC 24 |
Sep 01 12:22:21 PM UTC 24 |
1419626144 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.2606834374 |
|
|
Sep 01 12:08:16 PM UTC 24 |
Sep 01 12:22:31 PM UTC 24 |
19177855496 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.362677652 |
|
|
Sep 01 12:21:45 PM UTC 24 |
Sep 01 12:22:49 PM UTC 24 |
7056169028 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.887792469 |
|
|
Sep 01 12:07:10 PM UTC 24 |
Sep 01 12:23:05 PM UTC 24 |
12431968427 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_alert_test.1619207569 |
|
|
Sep 01 12:23:06 PM UTC 24 |
Sep 01 12:23:08 PM UTC 24 |
143475520 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_regwen.352933701 |
|
|
Sep 01 12:07:21 PM UTC 24 |
Sep 01 12:23:56 PM UTC 24 |
18518828431 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1754226816 |
|
|
Sep 01 12:22:32 PM UTC 24 |
Sep 01 12:24:00 PM UTC 24 |
4193319237 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_regwen.4199718898 |
|
|
Sep 01 12:14:29 PM UTC 24 |
Sep 01 12:24:08 PM UTC 24 |
33314701079 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.1739829461 |
|
|
Sep 01 12:22:22 PM UTC 24 |
Sep 01 12:24:09 PM UTC 24 |
6768271705 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.3264513627 |
|
|
Sep 01 12:14:20 PM UTC 24 |
Sep 01 12:25:04 PM UTC 24 |
7271441509 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_regwen.3003125537 |
|
|
Sep 01 12:03:31 PM UTC 24 |
Sep 01 12:25:24 PM UTC 24 |
53421466577 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_executable.4126058616 |
|
|
Sep 01 12:14:26 PM UTC 24 |
Sep 01 12:25:35 PM UTC 24 |
8134441198 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.2388332989 |
|
|
Sep 01 12:20:12 PM UTC 24 |
Sep 01 12:26:08 PM UTC 24 |
5417845407 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all.1825832433 |
|
|
Sep 01 09:55:14 AM UTC 24 |
Sep 01 12:26:14 PM UTC 24 |
428621870478 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_regwen.343664972 |
|
|
Sep 01 12:19:22 PM UTC 24 |
Sep 01 12:26:15 PM UTC 24 |
16379628448 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.1326529082 |
|
|
Sep 01 12:20:50 PM UTC 24 |
Sep 01 12:26:18 PM UTC 24 |
4013056717 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.3188971623 |
|
|
Sep 01 12:02:33 PM UTC 24 |
Sep 01 12:26:29 PM UTC 24 |
54836576372 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_bijection.1704411181 |
|
|
Sep 01 11:56:41 AM UTC 24 |
Sep 01 12:26:34 PM UTC 24 |
307413956200 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.2285620877 |
|
|
Sep 01 12:03:18 PM UTC 24 |
Sep 01 12:27:00 PM UTC 24 |
56211928960 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all.1845437632 |
|
|
Sep 01 12:22:50 PM UTC 24 |
Sep 01 12:27:25 PM UTC 24 |
92789429711 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_executable.1927586855 |
|
|
Sep 01 12:21:54 PM UTC 24 |
Sep 01 12:27:36 PM UTC 24 |
6621231875 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all.2021586231 |
|
|
Sep 01 11:42:38 AM UTC 24 |
Sep 01 12:28:26 PM UTC 24 |
250755956638 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.1323734253 |
|
|
Sep 01 12:21:18 PM UTC 24 |
Sep 01 12:28:33 PM UTC 24 |
31868275914 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.1712013849 |
|
|
Sep 01 12:22:15 PM UTC 24 |
Sep 01 12:28:42 PM UTC 24 |
13967127499 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all.890307156 |
|
|
Sep 01 11:15:59 AM UTC 24 |
Sep 01 12:28:51 PM UTC 24 |
218699353557 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.3190487807 |
|
|
Sep 01 12:17:58 PM UTC 24 |
Sep 01 12:29:11 PM UTC 24 |
98610383098 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.3532380170 |
|
|
Sep 01 12:21:46 PM UTC 24 |
Sep 01 12:29:43 PM UTC 24 |
33778240567 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.2443851309 |
|
|
Sep 01 12:20:35 PM UTC 24 |
Sep 01 12:29:45 PM UTC 24 |
38846779264 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.4254893960 |
|
|
Sep 01 12:09:46 PM UTC 24 |
Sep 01 12:30:44 PM UTC 24 |
60688292444 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_regwen.1666552232 |
|
|
Sep 01 12:10:00 PM UTC 24 |
Sep 01 12:30:59 PM UTC 24 |
14416787876 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_bijection.560342334 |
|
|
Sep 01 12:20:45 PM UTC 24 |
Sep 01 12:31:43 PM UTC 24 |
43060057239 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_executable.3284824056 |
|
|
Sep 01 12:19:03 PM UTC 24 |
Sep 01 12:32:50 PM UTC 24 |
69979762563 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.1780681630 |
|
|
Sep 01 12:18:43 PM UTC 24 |
Sep 01 12:33:20 PM UTC 24 |
14121939797 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_regwen.914588723 |
|
|
Sep 01 12:22:05 PM UTC 24 |
Sep 01 12:33:40 PM UTC 24 |
3032820293 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all.478361516 |
|
|
Sep 01 11:49:43 AM UTC 24 |
Sep 01 12:35:01 PM UTC 24 |
213297987658 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_bijection.1893459525 |
|
|
Sep 01 12:05:40 PM UTC 24 |
Sep 01 12:35:30 PM UTC 24 |
67265691394 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.303800094 |
|
|
Sep 01 12:16:49 PM UTC 24 |
Sep 01 12:37:38 PM UTC 24 |
25174288767 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all.3911837650 |
|
|
Sep 01 11:59:12 AM UTC 24 |
Sep 01 12:41:16 PM UTC 24 |
177442620627 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_bijection.136155818 |
|
|
Sep 01 12:02:41 PM UTC 24 |
Sep 01 12:41:44 PM UTC 24 |
460414005058 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all.3073780498 |
|
|
Sep 01 11:52:24 AM UTC 24 |
Sep 01 12:49:51 PM UTC 24 |
125904859587 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all.3194645496 |
|
|
Sep 01 11:28:42 AM UTC 24 |
Sep 01 12:51:27 PM UTC 24 |
167572151804 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all.649519174 |
|
|
Sep 01 11:25:45 AM UTC 24 |
Sep 01 12:52:44 PM UTC 24 |
276840186590 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all.2159959890 |
|
|
Sep 01 10:52:23 AM UTC 24 |
Sep 01 12:53:49 PM UTC 24 |
1365613428600 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all.1610192479 |
|
|
Sep 01 10:49:59 AM UTC 24 |
Sep 01 12:54:08 PM UTC 24 |
421347377733 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all.3219384931 |
|
|
Sep 01 11:40:23 AM UTC 24 |
Sep 01 12:56:18 PM UTC 24 |
529729350907 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all.2244561419 |
|
|
Sep 01 11:14:23 AM UTC 24 |
Sep 01 12:56:53 PM UTC 24 |
48499192645 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_bijection.2819864806 |
|
|
Sep 01 12:17:33 PM UTC 24 |
Sep 01 01:01:13 PM UTC 24 |
295573290110 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all.3050766993 |
|
|
Sep 01 12:16:09 PM UTC 24 |
Sep 01 01:02:52 PM UTC 24 |
48142880400 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all.1865949371 |
|
|
Sep 01 11:22:17 AM UTC 24 |
Sep 01 01:04:33 PM UTC 24 |
698246720054 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all.2222972027 |
|
|
Sep 01 11:55:48 AM UTC 24 |
Sep 01 01:05:48 PM UTC 24 |
323614266262 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all.3603333610 |
|
|
Sep 01 12:02:22 PM UTC 24 |
Sep 01 01:07:32 PM UTC 24 |
163324009323 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all.3204860065 |
|
|
Sep 01 11:37:45 AM UTC 24 |
Sep 01 01:08:47 PM UTC 24 |
196079064631 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all.983756241 |
|
|
Sep 01 12:04:13 PM UTC 24 |
Sep 01 01:08:57 PM UTC 24 |
194015726432 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all.2985929438 |
|
|
Sep 01 12:07:37 PM UTC 24 |
Sep 01 01:10:16 PM UTC 24 |
111796465542 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all.2849900022 |
|
|
Sep 01 12:12:02 PM UTC 24 |
Sep 01 01:15:31 PM UTC 24 |
156165696010 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all.1949413143 |
|
|
Sep 01 12:20:30 PM UTC 24 |
Sep 01 01:29:24 PM UTC 24 |
206639580940 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3113989373 |
|
|
Sep 01 12:23:09 PM UTC 24 |
Sep 01 12:24:00 PM UTC 24 |
15351672652 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1044961290 |
|
|
Sep 01 12:23:58 PM UTC 24 |
Sep 01 12:24:02 PM UTC 24 |
48008326 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2970460583 |
|
|
Sep 01 12:24:01 PM UTC 24 |
Sep 01 12:24:03 PM UTC 24 |
43582159 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3343531394 |
|
|
Sep 01 12:24:01 PM UTC 24 |
Sep 01 12:24:04 PM UTC 24 |
345759224 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2035473628 |
|
|
Sep 01 12:24:03 PM UTC 24 |
Sep 01 12:24:05 PM UTC 24 |
13594923 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1463849617 |
|
|
Sep 01 12:24:05 PM UTC 24 |
Sep 01 12:24:07 PM UTC 24 |
18481878 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3301085959 |
|
|
Sep 01 12:24:06 PM UTC 24 |
Sep 01 12:24:08 PM UTC 24 |
30397284 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3385296915 |
|
|
Sep 01 12:24:04 PM UTC 24 |
Sep 01 12:24:10 PM UTC 24 |
1443101401 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3652152800 |
|
|
Sep 01 12:24:11 PM UTC 24 |
Sep 01 12:24:13 PM UTC 24 |
31118166 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2716412284 |
|
|
Sep 01 12:24:08 PM UTC 24 |
Sep 01 12:24:14 PM UTC 24 |
352082449 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.199611941 |
|
|
Sep 01 12:24:11 PM UTC 24 |
Sep 01 12:24:14 PM UTC 24 |
148278509 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4217169628 |
|
|
Sep 01 12:24:14 PM UTC 24 |
Sep 01 12:24:16 PM UTC 24 |
35759261 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2321039675 |
|
|
Sep 01 12:24:09 PM UTC 24 |
Sep 01 12:24:17 PM UTC 24 |
120793810 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3182207385 |
|
|
Sep 01 12:24:15 PM UTC 24 |
Sep 01 12:24:17 PM UTC 24 |
24474878 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3228477481 |
|
|
Sep 01 12:24:15 PM UTC 24 |
Sep 01 12:24:18 PM UTC 24 |
83324494 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2208568861 |
|
|
Sep 01 12:24:16 PM UTC 24 |
Sep 01 12:24:18 PM UTC 24 |
19950594 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2370070109 |
|
|
Sep 01 12:24:19 PM UTC 24 |
Sep 01 12:24:24 PM UTC 24 |
508451179 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.441115037 |
|
|
Sep 01 12:24:19 PM UTC 24 |
Sep 01 12:24:25 PM UTC 24 |
355524874 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3745709588 |
|
|
Sep 01 12:24:19 PM UTC 24 |
Sep 01 12:24:25 PM UTC 24 |
110356049 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1199719778 |
|
|
Sep 01 12:24:25 PM UTC 24 |
Sep 01 12:24:27 PM UTC 24 |
12726573 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3142612406 |
|
|
Sep 01 12:24:25 PM UTC 24 |
Sep 01 12:24:27 PM UTC 24 |
54318518 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2434698059 |
|
|
Sep 01 12:24:27 PM UTC 24 |
Sep 01 12:24:30 PM UTC 24 |
294196089 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1125572702 |
|
|
Sep 01 12:24:26 PM UTC 24 |
Sep 01 12:24:30 PM UTC 24 |
168683986 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1951275646 |
|
|
Sep 01 12:24:29 PM UTC 24 |
Sep 01 12:24:30 PM UTC 24 |
58511967 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.308216288 |
|
|
Sep 01 12:24:32 PM UTC 24 |
Sep 01 12:24:37 PM UTC 24 |
320795937 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2478529927 |
|
|
Sep 01 12:24:31 PM UTC 24 |
Sep 01 12:24:38 PM UTC 24 |
358713643 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.4247283723 |
|
|
Sep 01 12:24:39 PM UTC 24 |
Sep 01 12:24:41 PM UTC 24 |
25558038 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.4293720093 |
|
|
Sep 01 12:24:38 PM UTC 24 |
Sep 01 12:24:41 PM UTC 24 |
451908064 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.947291225 |
|
|
Sep 01 12:24:42 PM UTC 24 |
Sep 01 12:24:44 PM UTC 24 |
16691189 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.4269757223 |
|
|
Sep 01 12:24:42 PM UTC 24 |
Sep 01 12:24:47 PM UTC 24 |
344528606 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1854719843 |
|
|
Sep 01 12:24:46 PM UTC 24 |
Sep 01 12:24:47 PM UTC 24 |
31661692 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3532842079 |
|
|
Sep 01 12:24:48 PM UTC 24 |
Sep 01 12:24:50 PM UTC 24 |
52462379 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1645685027 |
|
|
Sep 01 12:24:49 PM UTC 24 |
Sep 01 12:24:57 PM UTC 24 |
4826612630 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.383856658 |
|
|
Sep 01 12:24:19 PM UTC 24 |
Sep 01 12:25:04 PM UTC 24 |
3812603878 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1714724321 |
|
|
Sep 01 12:24:58 PM UTC 24 |
Sep 01 12:25:04 PM UTC 24 |
40273126 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.534203591 |
|
|
Sep 01 12:25:05 PM UTC 24 |
Sep 01 12:25:07 PM UTC 24 |
30534045 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3356705726 |
|
|
Sep 01 12:25:05 PM UTC 24 |
Sep 01 12:25:07 PM UTC 24 |
36240899 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.537503772 |
|
|
Sep 01 12:25:05 PM UTC 24 |
Sep 01 12:25:08 PM UTC 24 |
90505642 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1542900152 |
|
|
Sep 01 12:25:09 PM UTC 24 |
Sep 01 12:25:11 PM UTC 24 |
32061596 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3186247898 |
|
|
Sep 01 12:25:09 PM UTC 24 |
Sep 01 12:25:11 PM UTC 24 |
45526812 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3673028405 |
|
|
Sep 01 12:24:08 PM UTC 24 |
Sep 01 12:25:11 PM UTC 24 |
14764864720 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2441926938 |
|
|
Sep 01 12:25:09 PM UTC 24 |
Sep 01 12:25:12 PM UTC 24 |
149718052 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.733812197 |
|
|
Sep 01 12:25:13 PM UTC 24 |
Sep 01 12:25:16 PM UTC 24 |
256255006 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1116175039 |
|
|
Sep 01 12:25:12 PM UTC 24 |
Sep 01 12:25:19 PM UTC 24 |
92866709 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2789134524 |
|
|
Sep 01 12:25:12 PM UTC 24 |
Sep 01 12:25:19 PM UTC 24 |
355667148 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.871308076 |
|
|
Sep 01 12:25:17 PM UTC 24 |
Sep 01 12:25:20 PM UTC 24 |
43096948 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.4107024534 |
|
|
Sep 01 12:25:20 PM UTC 24 |
Sep 01 12:25:23 PM UTC 24 |
65592095 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.987989693 |
|
|
Sep 01 12:25:21 PM UTC 24 |
Sep 01 12:25:28 PM UTC 24 |
370392923 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4195719698 |
|
|
Sep 01 12:25:25 PM UTC 24 |
Sep 01 12:25:28 PM UTC 24 |
315696289 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2755839772 |
|
|
Sep 01 12:25:24 PM UTC 24 |
Sep 01 12:25:30 PM UTC 24 |
90774083 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1465210615 |
|
|
Sep 01 12:25:29 PM UTC 24 |
Sep 01 12:25:32 PM UTC 24 |
14530717 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.733487359 |
|
|
Sep 01 12:25:29 PM UTC 24 |
Sep 01 12:25:32 PM UTC 24 |
58742023 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.4202978337 |
|
|
Sep 01 12:25:30 PM UTC 24 |
Sep 01 12:25:36 PM UTC 24 |
355041389 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2045627388 |
|
|
Sep 01 12:25:32 PM UTC 24 |
Sep 01 12:25:40 PM UTC 24 |
254739424 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3765872901 |
|
|
Sep 01 12:25:38 PM UTC 24 |
Sep 01 12:25:40 PM UTC 24 |
26472203 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.133020820 |
|
|
Sep 01 12:25:37 PM UTC 24 |
Sep 01 12:25:40 PM UTC 24 |
145928617 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.778184322 |
|
|
Sep 01 12:25:41 PM UTC 24 |
Sep 01 12:25:43 PM UTC 24 |
15961310 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1706581396 |
|
|
Sep 01 12:25:12 PM UTC 24 |
Sep 01 12:25:46 PM UTC 24 |
7016149882 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3436559018 |
|
|
Sep 01 12:25:41 PM UTC 24 |
Sep 01 12:25:49 PM UTC 24 |
710110561 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.579830809 |
|
|
Sep 01 12:25:44 PM UTC 24 |
Sep 01 12:25:49 PM UTC 24 |
70966336 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.690997166 |
|
|
Sep 01 12:25:49 PM UTC 24 |
Sep 01 12:25:51 PM UTC 24 |
39689717 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1371020563 |
|
|
Sep 01 12:25:47 PM UTC 24 |
Sep 01 12:25:52 PM UTC 24 |
220229696 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.267254805 |
|
|
Sep 01 12:25:50 PM UTC 24 |
Sep 01 12:25:53 PM UTC 24 |
71324871 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.312337655 |
|
|
Sep 01 12:25:54 PM UTC 24 |
Sep 01 12:26:00 PM UTC 24 |
78267608 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3160544028 |
|
|
Sep 01 12:25:53 PM UTC 24 |
Sep 01 12:26:00 PM UTC 24 |
360589406 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.897452396 |
|
|
Sep 01 12:24:31 PM UTC 24 |
Sep 01 12:26:01 PM UTC 24 |
14711279028 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.488866859 |
|
|
Sep 01 12:26:01 PM UTC 24 |
Sep 01 12:26:03 PM UTC 24 |
50942327 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2136620949 |
|
|
Sep 01 12:26:02 PM UTC 24 |
Sep 01 12:26:04 PM UTC 24 |
56575171 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1883952390 |
|
|
Sep 01 12:26:01 PM UTC 24 |
Sep 01 12:26:05 PM UTC 24 |
1608014555 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1214673877 |
|
|
Sep 01 12:26:04 PM UTC 24 |
Sep 01 12:26:10 PM UTC 24 |
1534459087 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2458123204 |
|
|
Sep 01 12:26:09 PM UTC 24 |
Sep 01 12:26:12 PM UTC 24 |
360829629 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1651159390 |
|
|
Sep 01 12:26:11 PM UTC 24 |
Sep 01 12:26:13 PM UTC 24 |
21845631 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.670556890 |
|
|
Sep 01 12:26:06 PM UTC 24 |
Sep 01 12:26:14 PM UTC 24 |
146478582 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1428863941 |
|
|
Sep 01 12:26:13 PM UTC 24 |
Sep 01 12:26:15 PM UTC 24 |
15466687 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.870398282 |
|
|
Sep 01 12:25:32 PM UTC 24 |
Sep 01 12:26:15 PM UTC 24 |
3786844925 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1583312419 |
|
|
Sep 01 12:26:16 PM UTC 24 |
Sep 01 12:26:18 PM UTC 24 |
39609089 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.60878555 |
|
|
Sep 01 12:26:25 PM UTC 24 |
Sep 01 12:26:27 PM UTC 24 |
43715214 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2509424353 |
|
|
Sep 01 12:26:17 PM UTC 24 |
Sep 01 12:26:19 PM UTC 24 |
147621117 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2187170258 |
|
|
Sep 01 12:26:15 PM UTC 24 |
Sep 01 12:26:19 PM UTC 24 |
152417262 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3846908693 |
|
|
Sep 01 12:26:16 PM UTC 24 |
Sep 01 12:26:20 PM UTC 24 |
129869423 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.4076580056 |
|
|
Sep 01 12:24:51 PM UTC 24 |
Sep 01 12:26:21 PM UTC 24 |
26085355457 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1110543125 |
|
|
Sep 01 12:26:14 PM UTC 24 |
Sep 01 12:26:21 PM UTC 24 |
400246917 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1491287655 |
|
|
Sep 01 12:26:21 PM UTC 24 |
Sep 01 12:26:23 PM UTC 24 |
14745056 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3925727077 |
|
|
Sep 01 12:26:21 PM UTC 24 |
Sep 01 12:26:23 PM UTC 24 |
26051136 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2245269479 |
|
|
Sep 01 12:26:20 PM UTC 24 |
Sep 01 12:26:24 PM UTC 24 |
142622188 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3029560743 |
|
|
Sep 01 12:26:19 PM UTC 24 |
Sep 01 12:26:24 PM UTC 24 |
396169796 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.828354153 |
|
|
Sep 01 12:26:20 PM UTC 24 |
Sep 01 12:26:26 PM UTC 24 |
37511043 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2695708892 |
|
|
Sep 01 12:26:25 PM UTC 24 |
Sep 01 12:26:29 PM UTC 24 |
77142928 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.4287090235 |
|
|
Sep 01 12:26:27 PM UTC 24 |
Sep 01 12:26:29 PM UTC 24 |
36070483 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.71837286 |
|
|
Sep 01 12:26:24 PM UTC 24 |
Sep 01 12:26:30 PM UTC 24 |
78135370 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.909408661 |
|
|
Sep 01 12:26:23 PM UTC 24 |
Sep 01 12:26:31 PM UTC 24 |
845539615 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.737845237 |
|
|
Sep 01 12:25:53 PM UTC 24 |
Sep 01 12:26:31 PM UTC 24 |
7520080306 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.123062559 |
|
|
Sep 01 12:26:31 PM UTC 24 |
Sep 01 12:26:33 PM UTC 24 |
19399516 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.196971973 |
|
|
Sep 01 12:26:31 PM UTC 24 |
Sep 01 12:26:34 PM UTC 24 |
24590949 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.807735508 |
|
|
Sep 01 12:26:30 PM UTC 24 |
Sep 01 12:26:35 PM UTC 24 |
270767770 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2298300643 |
|
|
Sep 01 12:25:41 PM UTC 24 |
Sep 01 12:26:36 PM UTC 24 |
3765898657 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.826600353 |
|
|
Sep 01 12:26:30 PM UTC 24 |
Sep 01 12:26:36 PM UTC 24 |
226518483 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3936653569 |
|
|
Sep 01 12:26:36 PM UTC 24 |
Sep 01 12:26:38 PM UTC 24 |
36060759 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2917788919 |
|
|
Sep 01 12:26:29 PM UTC 24 |
Sep 01 12:26:38 PM UTC 24 |
1462968792 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2713352701 |
|
|
Sep 01 12:26:33 PM UTC 24 |
Sep 01 12:26:38 PM UTC 24 |
2293326420 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1301356963 |
|
|
Sep 01 12:26:35 PM UTC 24 |
Sep 01 12:26:39 PM UTC 24 |
221667322 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.644639879 |
|
|
Sep 01 12:26:38 PM UTC 24 |
Sep 01 12:26:40 PM UTC 24 |
25557806 ps |