| T556 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.299134803 |
|
|
Sep 01 11:04:36 AM UTC 24 |
Sep 01 11:21:12 AM UTC 24 |
14972686410 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.1655424767 |
|
|
Sep 01 11:03:37 AM UTC 24 |
Sep 01 11:21:31 AM UTC 24 |
71748959272 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.677024338 |
|
|
Sep 01 11:20:16 AM UTC 24 |
Sep 01 11:21:45 AM UTC 24 |
779374385 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.1543319838 |
|
|
Sep 01 11:21:46 AM UTC 24 |
Sep 01 11:21:54 AM UTC 24 |
1412616934 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_executable.1847819488 |
|
|
Sep 01 11:02:28 AM UTC 24 |
Sep 01 11:22:04 AM UTC 24 |
9819903794 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_regwen.517716051 |
|
|
Sep 01 11:18:43 AM UTC 24 |
Sep 01 11:22:12 AM UTC 24 |
13248364460 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_executable.433129536 |
|
|
Sep 01 11:04:46 AM UTC 24 |
Sep 01 11:22:16 AM UTC 24 |
40127391777 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.2771214961 |
|
|
Sep 01 11:18:51 AM UTC 24 |
Sep 01 11:22:38 AM UTC 24 |
6662238838 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.2996102838 |
|
|
Sep 01 11:20:50 AM UTC 24 |
Sep 01 11:22:41 AM UTC 24 |
9395925222 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_alert_test.946552114 |
|
|
Sep 01 11:22:39 AM UTC 24 |
Sep 01 11:22:41 AM UTC 24 |
13903716 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1495057573 |
|
|
Sep 01 11:22:13 AM UTC 24 |
Sep 01 11:22:42 AM UTC 24 |
405393025 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_smoke.4187461298 |
|
|
Sep 01 11:22:41 AM UTC 24 |
Sep 01 11:22:59 AM UTC 24 |
1534444726 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_regwen.3139273187 |
|
|
Sep 01 11:12:15 AM UTC 24 |
Sep 01 11:23:04 AM UTC 24 |
11080525122 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all.3631247339 |
|
|
Sep 01 10:40:33 AM UTC 24 |
Sep 01 11:23:07 AM UTC 24 |
131163988515 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_regwen.30240626 |
|
|
Sep 01 11:09:04 AM UTC 24 |
Sep 01 11:23:53 AM UTC 24 |
16302065997 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.4028209873 |
|
|
Sep 01 11:14:51 AM UTC 24 |
Sep 01 11:24:14 AM UTC 24 |
7120784817 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.661650502 |
|
|
Sep 01 11:24:15 AM UTC 24 |
Sep 01 11:24:36 AM UTC 24 |
2807994093 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access.1804288793 |
|
|
Sep 01 11:23:05 AM UTC 24 |
Sep 01 11:24:59 AM UTC 24 |
890978385 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.1110676302 |
|
|
Sep 01 11:23:54 AM UTC 24 |
Sep 01 11:25:03 AM UTC 24 |
800731447 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all.1306132864 |
|
|
Sep 01 10:29:07 AM UTC 24 |
Sep 01 11:25:07 AM UTC 24 |
281513320825 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_bijection.650052598 |
|
|
Sep 01 10:56:22 AM UTC 24 |
Sep 01 11:25:11 AM UTC 24 |
922585633457 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.3292954536 |
|
|
Sep 01 11:15:01 AM UTC 24 |
Sep 01 11:25:11 AM UTC 24 |
20246361749 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.2906191409 |
|
|
Sep 01 11:25:12 AM UTC 24 |
Sep 01 11:25:19 AM UTC 24 |
346218455 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.337465165 |
|
|
Sep 01 11:21:56 AM UTC 24 |
Sep 01 11:25:26 AM UTC 24 |
28849549747 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.3281920798 |
|
|
Sep 01 11:18:51 AM UTC 24 |
Sep 01 11:25:43 AM UTC 24 |
19185383149 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.1681194315 |
|
|
Sep 01 11:22:05 AM UTC 24 |
Sep 01 11:26:02 AM UTC 24 |
87678728315 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_alert_test.2846645917 |
|
|
Sep 01 11:26:03 AM UTC 24 |
Sep 01 11:26:05 AM UTC 24 |
13701407 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2531920544 |
|
|
Sep 01 11:25:26 AM UTC 24 |
Sep 01 11:26:13 AM UTC 24 |
1151894712 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.1172223052 |
|
|
Sep 01 11:23:00 AM UTC 24 |
Sep 01 11:26:19 AM UTC 24 |
3833203367 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.3741708925 |
|
|
Sep 01 11:19:11 AM UTC 24 |
Sep 01 11:26:33 AM UTC 24 |
4781142201 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_smoke.2374321378 |
|
|
Sep 01 11:26:06 AM UTC 24 |
Sep 01 11:26:38 AM UTC 24 |
1275161458 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all.2585798284 |
|
|
Sep 01 10:59:20 AM UTC 24 |
Sep 01 11:26:42 AM UTC 24 |
47334351331 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.2388977534 |
|
|
Sep 01 11:24:37 AM UTC 24 |
Sep 01 11:26:44 AM UTC 24 |
10523880138 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.3219539796 |
|
|
Sep 01 11:19:28 AM UTC 24 |
Sep 01 11:26:45 AM UTC 24 |
21349804952 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.2673174749 |
|
|
Sep 01 11:26:45 AM UTC 24 |
Sep 01 11:26:57 AM UTC 24 |
1354237681 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_executable.1717449434 |
|
|
Sep 01 11:18:36 AM UTC 24 |
Sep 01 11:26:59 AM UTC 24 |
6452659565 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access.139466908 |
|
|
Sep 01 11:26:38 AM UTC 24 |
Sep 01 11:27:19 AM UTC 24 |
7675367870 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.583642140 |
|
|
Sep 01 11:26:43 AM UTC 24 |
Sep 01 11:27:21 AM UTC 24 |
1420953638 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.2289483939 |
|
|
Sep 01 11:27:21 AM UTC 24 |
Sep 01 11:27:30 AM UTC 24 |
5614611343 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.1788660612 |
|
|
Sep 01 11:25:20 AM UTC 24 |
Sep 01 11:28:22 AM UTC 24 |
2578797878 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.3893391905 |
|
|
Sep 01 11:15:23 AM UTC 24 |
Sep 01 11:28:27 AM UTC 24 |
31687780550 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.3858567296 |
|
|
Sep 01 11:19:56 AM UTC 24 |
Sep 01 11:28:40 AM UTC 24 |
18265245189 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.4283194816 |
|
|
Sep 01 11:26:47 AM UTC 24 |
Sep 01 11:28:51 AM UTC 24 |
8648402871 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_alert_test.2355898067 |
|
|
Sep 01 11:28:52 AM UTC 24 |
Sep 01 11:28:54 AM UTC 24 |
13495354 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all.3755442179 |
|
|
Sep 01 10:36:35 AM UTC 24 |
Sep 01 11:28:55 AM UTC 24 |
57342668069 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.2177897634 |
|
|
Sep 01 11:25:12 AM UTC 24 |
Sep 01 11:29:05 AM UTC 24 |
7278718217 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_smoke.2173358360 |
|
|
Sep 01 11:28:55 AM UTC 24 |
Sep 01 11:29:16 AM UTC 24 |
466988141 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_executable.2400679727 |
|
|
Sep 01 11:21:13 AM UTC 24 |
Sep 01 11:29:23 AM UTC 24 |
4998677841 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.3536686468 |
|
|
Sep 01 11:28:56 AM UTC 24 |
Sep 01 11:29:36 AM UTC 24 |
1969909067 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.1524812967 |
|
|
Sep 01 11:28:23 AM UTC 24 |
Sep 01 11:29:39 AM UTC 24 |
2458463053 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.2509319226 |
|
|
Sep 01 11:28:28 AM UTC 24 |
Sep 01 11:29:43 AM UTC 24 |
25181579432 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_executable.3951863257 |
|
|
Sep 01 11:25:04 AM UTC 24 |
Sep 01 11:29:46 AM UTC 24 |
12296786492 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.1540255660 |
|
|
Sep 01 11:29:40 AM UTC 24 |
Sep 01 11:29:54 AM UTC 24 |
2816654145 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_bijection.3964399008 |
|
|
Sep 01 10:43:42 AM UTC 24 |
Sep 01 11:30:01 AM UTC 24 |
98717603478 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_bijection.1557734176 |
|
|
Sep 01 11:00:47 AM UTC 24 |
Sep 01 11:30:30 AM UTC 24 |
156898795279 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.138216133 |
|
|
Sep 01 11:29:44 AM UTC 24 |
Sep 01 11:30:54 AM UTC 24 |
790262797 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all.1379728182 |
|
|
Sep 01 10:55:31 AM UTC 24 |
Sep 01 11:30:56 AM UTC 24 |
89371846158 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.1626468927 |
|
|
Sep 01 11:30:55 AM UTC 24 |
Sep 01 11:31:02 AM UTC 24 |
1354140549 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.611550595 |
|
|
Sep 01 11:29:47 AM UTC 24 |
Sep 01 11:31:11 AM UTC 24 |
35708545557 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access.1021009152 |
|
|
Sep 01 11:29:25 AM UTC 24 |
Sep 01 11:31:14 AM UTC 24 |
1314640331 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1432846621 |
|
|
Sep 01 11:31:12 AM UTC 24 |
Sep 01 11:31:46 AM UTC 24 |
2780934575 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_alert_test.1353228170 |
|
|
Sep 01 11:31:46 AM UTC 24 |
Sep 01 11:31:48 AM UTC 24 |
24240897 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_regwen.2380248865 |
|
|
Sep 01 11:15:28 AM UTC 24 |
Sep 01 11:32:05 AM UTC 24 |
77022670049 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.2378556230 |
|
|
Sep 01 11:26:14 AM UTC 24 |
Sep 01 11:32:05 AM UTC 24 |
3813179020 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_smoke.3292602247 |
|
|
Sep 01 11:31:49 AM UTC 24 |
Sep 01 11:32:09 AM UTC 24 |
491593182 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_bijection.3615749577 |
|
|
Sep 01 11:19:11 AM UTC 24 |
Sep 01 11:32:18 AM UTC 24 |
12151477139 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.98386717 |
|
|
Sep 01 11:25:00 AM UTC 24 |
Sep 01 11:32:19 AM UTC 24 |
48281117079 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.3677205642 |
|
|
Sep 01 11:31:03 AM UTC 24 |
Sep 01 11:32:23 AM UTC 24 |
2906919166 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.1563735283 |
|
|
Sep 01 11:26:34 AM UTC 24 |
Sep 01 11:32:27 AM UTC 24 |
4776050627 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access.1613335452 |
|
|
Sep 01 11:32:10 AM UTC 24 |
Sep 01 11:32:39 AM UTC 24 |
2478496820 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.1247793621 |
|
|
Sep 01 11:32:24 AM UTC 24 |
Sep 01 11:32:42 AM UTC 24 |
2754420358 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_bijection.935896686 |
|
|
Sep 01 11:04:02 AM UTC 24 |
Sep 01 11:32:52 AM UTC 24 |
816475068706 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.1119020902 |
|
|
Sep 01 11:20:59 AM UTC 24 |
Sep 01 11:32:55 AM UTC 24 |
97587787317 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.259315928 |
|
|
Sep 01 11:32:56 AM UTC 24 |
Sep 01 11:33:01 AM UTC 24 |
359966043 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.1571996300 |
|
|
Sep 01 11:32:20 AM UTC 24 |
Sep 01 11:33:40 AM UTC 24 |
809567028 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.2087675640 |
|
|
Sep 01 11:22:42 AM UTC 24 |
Sep 01 11:33:45 AM UTC 24 |
16713453454 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.4190746009 |
|
|
Sep 01 11:26:58 AM UTC 24 |
Sep 01 11:34:04 AM UTC 24 |
37528545018 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_executable.2289713428 |
|
|
Sep 01 11:30:02 AM UTC 24 |
Sep 01 11:34:19 AM UTC 24 |
22958184439 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_alert_test.1334248849 |
|
|
Sep 01 11:34:21 AM UTC 24 |
Sep 01 11:34:23 AM UTC 24 |
14955195 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.312235713 |
|
|
Sep 01 11:23:08 AM UTC 24 |
Sep 01 11:34:24 AM UTC 24 |
79720438135 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.806352138 |
|
|
Sep 01 11:32:28 AM UTC 24 |
Sep 01 11:34:34 AM UTC 24 |
51487007573 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_smoke.2271938591 |
|
|
Sep 01 11:34:24 AM UTC 24 |
Sep 01 11:34:41 AM UTC 24 |
1937048579 ps |
| T48 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3410344736 |
|
|
Sep 01 11:33:46 AM UTC 24 |
Sep 01 11:34:50 AM UTC 24 |
6380799189 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access.1823296361 |
|
|
Sep 01 11:34:50 AM UTC 24 |
Sep 01 11:35:04 AM UTC 24 |
590834935 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.3138674006 |
|
|
Sep 01 11:29:37 AM UTC 24 |
Sep 01 11:35:28 AM UTC 24 |
25102880974 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.3387266087 |
|
|
Sep 01 11:26:40 AM UTC 24 |
Sep 01 11:35:34 AM UTC 24 |
18296818122 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.409037041 |
|
|
Sep 01 11:35:30 AM UTC 24 |
Sep 01 11:35:55 AM UTC 24 |
5785944023 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.1874002858 |
|
|
Sep 01 11:35:35 AM UTC 24 |
Sep 01 11:36:05 AM UTC 24 |
717407198 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.3679932306 |
|
|
Sep 01 11:30:57 AM UTC 24 |
Sep 01 11:36:37 AM UTC 24 |
47724175655 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.3828596144 |
|
|
Sep 01 11:27:30 AM UTC 24 |
Sep 01 11:36:38 AM UTC 24 |
36956275327 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.551435632 |
|
|
Sep 01 11:32:07 AM UTC 24 |
Sep 01 11:36:44 AM UTC 24 |
9289516814 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.3946709142 |
|
|
Sep 01 11:36:44 AM UTC 24 |
Sep 01 11:36:50 AM UTC 24 |
360599804 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.4022073138 |
|
|
Sep 01 11:33:02 AM UTC 24 |
Sep 01 11:36:52 AM UTC 24 |
27690991790 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.2396756983 |
|
|
Sep 01 11:33:41 AM UTC 24 |
Sep 01 11:37:02 AM UTC 24 |
11157148673 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all.1517169415 |
|
|
Sep 01 10:46:33 AM UTC 24 |
Sep 01 11:37:44 AM UTC 24 |
43457028466 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.2195448519 |
|
|
Sep 01 11:35:56 AM UTC 24 |
Sep 01 11:38:02 AM UTC 24 |
121280995624 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_alert_test.1815937681 |
|
|
Sep 01 11:38:03 AM UTC 24 |
Sep 01 11:38:05 AM UTC 24 |
27700497 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_smoke.565947271 |
|
|
Sep 01 11:38:06 AM UTC 24 |
Sep 01 11:38:24 AM UTC 24 |
2843418845 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.2367886038 |
|
|
Sep 01 11:37:03 AM UTC 24 |
Sep 01 11:38:30 AM UTC 24 |
5031208304 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_regwen.3028002839 |
|
|
Sep 01 11:30:30 AM UTC 24 |
Sep 01 11:38:36 AM UTC 24 |
36322113649 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.2993982442 |
|
|
Sep 01 11:34:42 AM UTC 24 |
Sep 01 11:38:38 AM UTC 24 |
16105270957 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_regwen.3736597294 |
|
|
Sep 01 11:21:31 AM UTC 24 |
Sep 01 11:38:38 AM UTC 24 |
221023987749 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.3767864200 |
|
|
Sep 01 10:16:40 AM UTC 24 |
Sep 01 11:38:52 AM UTC 24 |
1258499285043 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access.4270442316 |
|
|
Sep 01 11:38:39 AM UTC 24 |
Sep 01 11:39:01 AM UTC 24 |
5594558150 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_executable.703956507 |
|
|
Sep 01 11:27:00 AM UTC 24 |
Sep 01 11:39:33 AM UTC 24 |
17774350324 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_regwen.550941314 |
|
|
Sep 01 11:32:53 AM UTC 24 |
Sep 01 11:39:40 AM UTC 24 |
24467083101 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.1223382873 |
|
|
Sep 01 11:38:53 AM UTC 24 |
Sep 01 11:39:52 AM UTC 24 |
1492879829 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_regwen.2090195810 |
|
|
Sep 01 11:25:08 AM UTC 24 |
Sep 01 11:39:53 AM UTC 24 |
16454972581 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.2117901552 |
|
|
Sep 01 11:39:34 AM UTC 24 |
Sep 01 11:39:59 AM UTC 24 |
6119132186 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.3982544610 |
|
|
Sep 01 11:40:01 AM UTC 24 |
Sep 01 11:40:08 AM UTC 24 |
1525843916 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.1776796698 |
|
|
Sep 01 11:36:51 AM UTC 24 |
Sep 01 11:40:13 AM UTC 24 |
14709047184 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.1989997169 |
|
|
Sep 01 11:18:28 AM UTC 24 |
Sep 01 11:40:17 AM UTC 24 |
27835956785 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.1398618441 |
|
|
Sep 01 11:32:39 AM UTC 24 |
Sep 01 11:40:22 AM UTC 24 |
45495311096 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.993287119 |
|
|
Sep 01 11:29:16 AM UTC 24 |
Sep 01 11:40:24 AM UTC 24 |
42183613224 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all.385296187 |
|
|
Sep 01 10:26:10 AM UTC 24 |
Sep 01 11:40:26 AM UTC 24 |
152710721851 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_alert_test.3409156996 |
|
|
Sep 01 11:40:25 AM UTC 24 |
Sep 01 11:40:27 AM UTC 24 |
42838592 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_executable.939128930 |
|
|
Sep 01 11:39:53 AM UTC 24 |
Sep 01 11:40:35 AM UTC 24 |
2750300429 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_executable.2817200328 |
|
|
Sep 01 11:32:42 AM UTC 24 |
Sep 01 11:40:41 AM UTC 24 |
32705370967 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.4255107126 |
|
|
Sep 01 11:36:54 AM UTC 24 |
Sep 01 11:40:41 AM UTC 24 |
55789418593 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_smoke.3485888237 |
|
|
Sep 01 11:40:26 AM UTC 24 |
Sep 01 11:40:53 AM UTC 24 |
542550072 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.4249064176 |
|
|
Sep 01 11:39:02 AM UTC 24 |
Sep 01 11:40:57 AM UTC 24 |
1631859618 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.1183074882 |
|
|
Sep 01 11:29:55 AM UTC 24 |
Sep 01 11:41:01 AM UTC 24 |
12476793172 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access.744533107 |
|
|
Sep 01 11:40:42 AM UTC 24 |
Sep 01 11:41:05 AM UTC 24 |
3423897498 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.3166906719 |
|
|
Sep 01 11:41:05 AM UTC 24 |
Sep 01 11:41:18 AM UTC 24 |
1627020833 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.360094880 |
|
|
Sep 01 11:32:19 AM UTC 24 |
Sep 01 11:41:21 AM UTC 24 |
171097779745 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_bijection.2937666442 |
|
|
Sep 01 10:52:52 AM UTC 24 |
Sep 01 11:41:21 AM UTC 24 |
132427988460 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3584368464 |
|
|
Sep 01 11:40:18 AM UTC 24 |
Sep 01 11:41:44 AM UTC 24 |
8615862783 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.939712387 |
|
|
Sep 01 11:41:01 AM UTC 24 |
Sep 01 11:41:51 AM UTC 24 |
769651902 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.3136123883 |
|
|
Sep 01 11:41:45 AM UTC 24 |
Sep 01 11:41:51 AM UTC 24 |
1413203432 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.2743557610 |
|
|
Sep 01 11:40:14 AM UTC 24 |
Sep 01 11:42:32 AM UTC 24 |
1658611611 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.2111137176 |
|
|
Sep 01 11:35:04 AM UTC 24 |
Sep 01 11:42:37 AM UTC 24 |
26640892362 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1263074736 |
|
|
Sep 01 11:42:34 AM UTC 24 |
Sep 01 11:42:49 AM UTC 24 |
1958974585 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_alert_test.4009302159 |
|
|
Sep 01 11:42:50 AM UTC 24 |
Sep 01 11:42:52 AM UTC 24 |
72661530 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.513303733 |
|
|
Sep 01 11:40:58 AM UTC 24 |
Sep 01 11:42:54 AM UTC 24 |
3059468714 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_smoke.3903880167 |
|
|
Sep 01 11:42:53 AM UTC 24 |
Sep 01 11:43:09 AM UTC 24 |
1073088197 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_regwen.3783623178 |
|
|
Sep 01 11:27:20 AM UTC 24 |
Sep 01 11:43:44 AM UTC 24 |
13057809273 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.4037986738 |
|
|
Sep 01 11:41:52 AM UTC 24 |
Sep 01 11:43:53 AM UTC 24 |
1668463885 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.2165167172 |
|
|
Sep 01 11:34:25 AM UTC 24 |
Sep 01 11:44:00 AM UTC 24 |
62769166096 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.188104052 |
|
|
Sep 01 11:40:42 AM UTC 24 |
Sep 01 11:44:08 AM UTC 24 |
12757517247 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.3295091039 |
|
|
Sep 01 11:41:52 AM UTC 24 |
Sep 01 11:44:09 AM UTC 24 |
1976490596 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.2069578855 |
|
|
Sep 01 11:38:39 AM UTC 24 |
Sep 01 11:44:23 AM UTC 24 |
5650479249 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.1962326362 |
|
|
Sep 01 11:44:10 AM UTC 24 |
Sep 01 11:44:23 AM UTC 24 |
2477088448 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_executable.319553624 |
|
|
Sep 01 11:36:38 AM UTC 24 |
Sep 01 11:44:26 AM UTC 24 |
11075525701 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.4207938924 |
|
|
Sep 01 11:44:09 AM UTC 24 |
Sep 01 11:44:27 AM UTC 24 |
2847517818 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access.505089902 |
|
|
Sep 01 11:43:55 AM UTC 24 |
Sep 01 11:44:55 AM UTC 24 |
4397944509 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.413998312 |
|
|
Sep 01 11:44:56 AM UTC 24 |
Sep 01 11:45:01 AM UTC 24 |
709230820 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.2701724592 |
|
|
Sep 01 11:44:23 AM UTC 24 |
Sep 01 11:46:13 AM UTC 24 |
9479761541 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_bijection.1656072717 |
|
|
Sep 01 11:29:06 AM UTC 24 |
Sep 01 11:46:13 AM UTC 24 |
26889593603 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_regwen.469555336 |
|
|
Sep 01 11:41:22 AM UTC 24 |
Sep 01 11:46:14 AM UTC 24 |
1598968849 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_executable.3848934745 |
|
|
Sep 01 11:41:22 AM UTC 24 |
Sep 01 11:46:28 AM UTC 24 |
9894696084 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_alert_test.912734993 |
|
|
Sep 01 11:46:28 AM UTC 24 |
Sep 01 11:46:30 AM UTC 24 |
47861034 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.4035684872 |
|
|
Sep 01 11:39:41 AM UTC 24 |
Sep 01 11:46:45 AM UTC 24 |
23878633049 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.3220778755 |
|
|
Sep 01 11:31:52 AM UTC 24 |
Sep 01 11:46:55 AM UTC 24 |
7902343173 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.138768965 |
|
|
Sep 01 11:36:06 AM UTC 24 |
Sep 01 11:46:58 AM UTC 24 |
36104093987 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_smoke.1067107163 |
|
|
Sep 01 11:46:32 AM UTC 24 |
Sep 01 11:47:01 AM UTC 24 |
10913207428 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_bijection.114130448 |
|
|
Sep 01 11:22:43 AM UTC 24 |
Sep 01 11:47:16 AM UTC 24 |
31515057089 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.4229273134 |
|
|
Sep 01 11:40:09 AM UTC 24 |
Sep 01 11:47:25 AM UTC 24 |
82790530857 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access.3206468773 |
|
|
Sep 01 11:47:02 AM UTC 24 |
Sep 01 11:47:38 AM UTC 24 |
7831548563 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.2208450619 |
|
|
Sep 01 11:47:26 AM UTC 24 |
Sep 01 11:47:42 AM UTC 24 |
3242711039 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.3385319652 |
|
|
Sep 01 11:45:02 AM UTC 24 |
Sep 01 11:48:33 AM UTC 24 |
7070313621 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.689664874 |
|
|
Sep 01 11:38:37 AM UTC 24 |
Sep 01 11:48:39 AM UTC 24 |
6845362650 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.3175207740 |
|
|
Sep 01 11:47:38 AM UTC 24 |
Sep 01 11:48:43 AM UTC 24 |
1484507518 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3360162632 |
|
|
Sep 01 11:46:14 AM UTC 24 |
Sep 01 11:49:12 AM UTC 24 |
23491281703 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_regwen.700035731 |
|
|
Sep 01 11:44:27 AM UTC 24 |
Sep 01 11:51:54 AM UTC 24 |
25778788408 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.2639768560 |
|
|
Sep 01 11:46:14 AM UTC 24 |
Sep 01 11:49:15 AM UTC 24 |
5545777359 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.71226082 |
|
|
Sep 01 11:49:13 AM UTC 24 |
Sep 01 11:49:18 AM UTC 24 |
684253564 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.1234022386 |
|
|
Sep 01 11:44:02 AM UTC 24 |
Sep 01 11:49:38 AM UTC 24 |
9817114201 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_regwen.3537929188 |
|
|
Sep 01 11:36:39 AM UTC 24 |
Sep 01 11:49:42 AM UTC 24 |
14451885642 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.3615023835 |
|
|
Sep 01 11:47:42 AM UTC 24 |
Sep 01 11:49:51 AM UTC 24 |
26596039061 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1876066739 |
|
|
Sep 01 11:49:39 AM UTC 24 |
Sep 01 11:49:53 AM UTC 24 |
1140258296 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_alert_test.3706059825 |
|
|
Sep 01 11:49:52 AM UTC 24 |
Sep 01 11:49:54 AM UTC 24 |
15016614 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all.3833440841 |
|
|
Sep 01 10:31:10 AM UTC 24 |
Sep 01 11:50:08 AM UTC 24 |
134620264247 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_smoke.1954806728 |
|
|
Sep 01 11:49:54 AM UTC 24 |
Sep 01 11:50:08 AM UTC 24 |
2680636702 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.2590858859 |
|
|
Sep 01 11:43:44 AM UTC 24 |
Sep 01 11:50:21 AM UTC 24 |
11911379632 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_regwen.3167692979 |
|
|
Sep 01 11:48:44 AM UTC 24 |
Sep 01 11:50:41 AM UTC 24 |
6888264792 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access.194486962 |
|
|
Sep 01 11:50:22 AM UTC 24 |
Sep 01 11:50:53 AM UTC 24 |
3883454221 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.2414886658 |
|
|
Sep 01 11:46:59 AM UTC 24 |
Sep 01 11:51:02 AM UTC 24 |
40777439302 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.2586173489 |
|
|
Sep 01 11:42:55 AM UTC 24 |
Sep 01 11:51:10 AM UTC 24 |
154985385510 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.611291499 |
|
|
Sep 01 11:50:55 AM UTC 24 |
Sep 01 11:51:18 AM UTC 24 |
1549482590 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.1926202566 |
|
|
Sep 01 11:51:03 AM UTC 24 |
Sep 01 11:51:31 AM UTC 24 |
765518036 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_regwen.1502682564 |
|
|
Sep 01 11:39:54 AM UTC 24 |
Sep 01 11:51:55 AM UTC 24 |
3559601687 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.1558395135 |
|
|
Sep 01 11:49:55 AM UTC 24 |
Sep 01 11:51:56 AM UTC 24 |
3173492231 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.2256319311 |
|
|
Sep 01 11:51:57 AM UTC 24 |
Sep 01 11:52:02 AM UTC 24 |
358732549 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.2940243146 |
|
|
Sep 01 11:51:11 AM UTC 24 |
Sep 01 11:52:13 AM UTC 24 |
14819499299 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.3246355436 |
|
|
Sep 01 11:41:18 AM UTC 24 |
Sep 01 11:52:24 AM UTC 24 |
27683642200 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.743471231 |
|
|
Sep 01 11:52:14 AM UTC 24 |
Sep 01 11:52:41 AM UTC 24 |
597067241 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_alert_test.464786162 |
|
|
Sep 01 11:52:42 AM UTC 24 |
Sep 01 11:52:44 AM UTC 24 |
80736563 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_bijection.518762411 |
|
|
Sep 01 11:26:19 AM UTC 24 |
Sep 01 11:52:59 AM UTC 24 |
101042357485 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_executable.3030126239 |
|
|
Sep 01 11:48:40 AM UTC 24 |
Sep 01 11:53:11 AM UTC 24 |
1883691680 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.3884132143 |
|
|
Sep 01 11:40:53 AM UTC 24 |
Sep 01 11:53:35 AM UTC 24 |
143259427080 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_smoke.707262331 |
|
|
Sep 01 11:52:45 AM UTC 24 |
Sep 01 11:53:37 AM UTC 24 |
1652873588 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.483303913 |
|
|
Sep 01 11:49:15 AM UTC 24 |
Sep 01 11:53:40 AM UTC 24 |
20699868610 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.3815034803 |
|
|
Sep 01 11:49:18 AM UTC 24 |
Sep 01 11:53:45 AM UTC 24 |
71774386876 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.266535868 |
|
|
Sep 01 11:52:03 AM UTC 24 |
Sep 01 11:53:51 AM UTC 24 |
3072828892 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.1726242217 |
|
|
Sep 01 11:53:45 AM UTC 24 |
Sep 01 11:54:03 AM UTC 24 |
1459221042 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access.292895509 |
|
|
Sep 01 11:53:38 AM UTC 24 |
Sep 01 11:54:24 AM UTC 24 |
1091304347 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_executable.1909098063 |
|
|
Sep 01 11:44:27 AM UTC 24 |
Sep 01 11:54:39 AM UTC 24 |
50658910078 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_bijection.1605452921 |
|
|
Sep 01 11:32:07 AM UTC 24 |
Sep 01 11:55:19 AM UTC 24 |
66991099658 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.1593031509 |
|
|
Sep 01 11:48:35 AM UTC 24 |
Sep 01 11:55:39 AM UTC 24 |
8265767302 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_regwen.346098632 |
|
|
Sep 01 11:51:56 AM UTC 24 |
Sep 01 11:55:42 AM UTC 24 |
2858499312 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.3928347280 |
|
|
Sep 01 11:51:57 AM UTC 24 |
Sep 01 11:55:44 AM UTC 24 |
4111082881 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.3341853791 |
|
|
Sep 01 11:55:39 AM UTC 24 |
Sep 01 11:55:45 AM UTC 24 |
1409108421 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.551268390 |
|
|
Sep 01 11:53:52 AM UTC 24 |
Sep 01 11:55:46 AM UTC 24 |
3265399629 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.554807161 |
|
|
Sep 01 11:54:03 AM UTC 24 |
Sep 01 11:55:55 AM UTC 24 |
8715303859 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_alert_test.243317630 |
|
|
Sep 01 11:55:56 AM UTC 24 |
Sep 01 11:55:58 AM UTC 24 |
29695151 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_smoke.259099716 |
|
|
Sep 01 11:55:59 AM UTC 24 |
Sep 01 11:56:08 AM UTC 24 |
1519213057 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.2910871199 |
|
|
Sep 01 11:50:43 AM UTC 24 |
Sep 01 11:56:41 AM UTC 24 |
23195950865 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all.4286322438 |
|
|
Sep 01 11:31:15 AM UTC 24 |
Sep 01 11:57:11 AM UTC 24 |
68966431918 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_executable.2190089700 |
|
|
Sep 01 11:51:32 AM UTC 24 |
Sep 01 11:57:21 AM UTC 24 |
26356998059 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.3467554622 |
|
|
Sep 01 11:53:36 AM UTC 24 |
Sep 01 11:57:39 AM UTC 24 |
3252657802 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access.4118607512 |
|
|
Sep 01 11:57:21 AM UTC 24 |
Sep 01 11:57:51 AM UTC 24 |
3448859183 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all.2326112341 |
|
|
Sep 01 10:43:04 AM UTC 24 |
Sep 01 11:58:07 AM UTC 24 |
842143279094 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.1576264109 |
|
|
Sep 01 11:55:43 AM UTC 24 |
Sep 01 11:58:09 AM UTC 24 |
8582869656 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.1149215942 |
|
|
Sep 01 11:57:53 AM UTC 24 |
Sep 01 11:58:13 AM UTC 24 |
2870033737 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.4040794878 |
|
|
Sep 01 11:50:09 AM UTC 24 |
Sep 01 11:58:27 AM UTC 24 |
40173356313 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.509901092 |
|
|
Sep 01 11:47:16 AM UTC 24 |
Sep 01 11:58:31 AM UTC 24 |
37213460933 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.3514471210 |
|
|
Sep 01 11:55:44 AM UTC 24 |
Sep 01 11:58:49 AM UTC 24 |
20239057189 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.982871705 |
|
|
Sep 01 11:53:41 AM UTC 24 |
Sep 01 11:58:57 AM UTC 24 |
38252032753 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.3294927821 |
|
|
Sep 01 11:58:50 AM UTC 24 |
Sep 01 11:58:58 AM UTC 24 |
3342158874 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_bijection.4025620224 |
|
|
Sep 01 11:40:37 AM UTC 24 |
Sep 01 11:59:02 AM UTC 24 |
64060724068 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1346992932 |
|
|
Sep 01 11:55:47 AM UTC 24 |
Sep 01 11:59:11 AM UTC 24 |
10649598451 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.2457251584 |
|
|
Sep 01 11:58:10 AM UTC 24 |
Sep 01 11:59:15 AM UTC 24 |
47176111325 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_alert_test.3179238201 |
|
|
Sep 01 11:59:16 AM UTC 24 |
Sep 01 11:59:18 AM UTC 24 |
62699633 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.671889568 |
|
|
Sep 01 11:59:03 AM UTC 24 |
Sep 01 11:59:22 AM UTC 24 |
336380170 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.3092622438 |
|
|
Sep 01 11:38:24 AM UTC 24 |
Sep 01 11:59:31 AM UTC 24 |
199304533624 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_smoke.791878772 |
|
|
Sep 01 11:59:19 AM UTC 24 |
Sep 01 11:59:32 AM UTC 24 |
1383272347 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.1848502724 |
|
|
Sep 01 11:58:08 AM UTC 24 |
Sep 01 12:00:03 PM UTC 24 |
4142930148 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_bijection.1764026746 |
|
|
Sep 01 11:06:26 AM UTC 24 |
Sep 01 12:00:03 PM UTC 24 |
337678796549 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.3780479844 |
|
|
Sep 01 11:46:46 AM UTC 24 |
Sep 01 12:00:12 PM UTC 24 |
38590957500 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access.154601182 |
|
|
Sep 01 12:00:07 PM UTC 24 |
Sep 01 12:00:34 PM UTC 24 |
7090870026 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.677972326 |
|
|
Sep 01 11:56:09 AM UTC 24 |
Sep 01 12:00:39 PM UTC 24 |
4321301734 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.768023523 |
|
|
Sep 01 12:00:13 PM UTC 24 |
Sep 01 12:00:48 PM UTC 24 |
5914239890 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.3314542761 |
|
|
Sep 01 12:00:24 PM UTC 24 |
Sep 01 12:01:08 PM UTC 24 |
1402243350 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.422105329 |
|
|
Sep 01 12:00:35 PM UTC 24 |
Sep 01 12:01:46 PM UTC 24 |
5098736062 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.3081326918 |
|
|
Sep 01 11:58:59 AM UTC 24 |
Sep 01 12:01:49 PM UTC 24 |
57330107605 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.3445465059 |
|
|
Sep 01 12:01:47 PM UTC 24 |
Sep 01 12:01:53 PM UTC 24 |
353216153 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_regwen.1076816615 |
|
|
Sep 01 11:58:31 AM UTC 24 |
Sep 01 12:02:07 PM UTC 24 |
1250114587 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2585365507 |
|
|
Sep 01 12:02:07 PM UTC 24 |
Sep 01 12:02:21 PM UTC 24 |
421713536 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.1203020113 |
|
|
Sep 01 11:44:23 AM UTC 24 |
Sep 01 12:02:21 PM UTC 24 |
122626989800 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_alert_test.343722044 |
|
|
Sep 01 12:02:22 PM UTC 24 |
Sep 01 12:02:24 PM UTC 24 |
16244498 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.3964497722 |
|
|
Sep 01 11:57:11 AM UTC 24 |
Sep 01 12:02:32 PM UTC 24 |
4489143812 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.4207731925 |
|
|
Sep 01 11:58:59 AM UTC 24 |
Sep 01 12:02:40 PM UTC 24 |
10457999227 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_regwen.2928814002 |
|
|
Sep 01 11:55:20 AM UTC 24 |
Sep 01 12:02:44 PM UTC 24 |
7164383973 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_smoke.898114203 |
|
|
Sep 01 12:02:26 PM UTC 24 |
Sep 01 12:02:50 PM UTC 24 |
14544587578 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.41146273 |
|
|
Sep 01 10:10:57 AM UTC 24 |
Sep 01 12:03:01 PM UTC 24 |
677906068691 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.499326936 |
|
|
Sep 01 11:54:25 AM UTC 24 |
Sep 01 12:03:02 PM UTC 24 |
8409923008 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.1994761450 |
|
|
Sep 01 11:40:28 AM UTC 24 |
Sep 01 12:03:02 PM UTC 24 |
19519212829 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_executable.2191398401 |
|
|
Sep 01 12:00:49 PM UTC 24 |
Sep 01 12:03:13 PM UTC 24 |
6888863162 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access.551062190 |
|
|
Sep 01 12:02:51 PM UTC 24 |
Sep 01 12:03:17 PM UTC 24 |
1513894079 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.1223493364 |
|
|
Sep 01 12:03:03 PM UTC 24 |
Sep 01 12:03:20 PM UTC 24 |
1381722271 ps |