| T303 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1356905115 |
|
|
Sep 04 03:30:18 AM UTC 24 |
Sep 04 03:31:01 AM UTC 24 |
4027657110 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_smoke.2501224369 |
|
|
Sep 04 03:30:38 AM UTC 24 |
Sep 04 03:31:08 AM UTC 24 |
3249375588 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.817606732 |
|
|
Sep 04 03:27:08 AM UTC 24 |
Sep 04 03:31:09 AM UTC 24 |
3260993028 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.1716175811 |
|
|
Sep 04 03:26:12 AM UTC 24 |
Sep 04 03:31:09 AM UTC 24 |
13975781272 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.2601362630 |
|
|
Sep 04 03:25:20 AM UTC 24 |
Sep 04 03:31:15 AM UTC 24 |
32029908856 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.186591852 |
|
|
Sep 04 03:29:41 AM UTC 24 |
Sep 04 03:31:18 AM UTC 24 |
8903195963 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_bijection.1070739599 |
|
|
Sep 04 03:15:54 AM UTC 24 |
Sep 04 03:31:30 AM UTC 24 |
54521229381 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_bijection.1375385767 |
|
|
Sep 04 03:17:37 AM UTC 24 |
Sep 04 03:31:38 AM UTC 24 |
50527353388 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.2420157124 |
|
|
Sep 04 03:31:15 AM UTC 24 |
Sep 04 03:31:49 AM UTC 24 |
1498793376 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.3022237618 |
|
|
Sep 04 03:31:19 AM UTC 24 |
Sep 04 03:32:05 AM UTC 24 |
743631529 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.1459663818 |
|
|
Sep 04 03:09:45 AM UTC 24 |
Sep 04 03:32:07 AM UTC 24 |
4638403908 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.4269825761 |
|
|
Sep 04 03:32:06 AM UTC 24 |
Sep 04 03:32:12 AM UTC 24 |
350372202 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.3345900629 |
|
|
Sep 04 03:23:18 AM UTC 24 |
Sep 04 03:32:22 AM UTC 24 |
17509180154 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access.3134129337 |
|
|
Sep 04 03:31:10 AM UTC 24 |
Sep 04 03:32:27 AM UTC 24 |
4751672048 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.1348402121 |
|
|
Sep 04 03:21:33 AM UTC 24 |
Sep 04 03:32:46 AM UTC 24 |
46992342028 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_alert_test.1729850596 |
|
|
Sep 04 03:32:48 AM UTC 24 |
Sep 04 03:32:50 AM UTC 24 |
18324466 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.3332451523 |
|
|
Sep 04 03:30:10 AM UTC 24 |
Sep 04 03:32:50 AM UTC 24 |
3140075380 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_smoke.3350379952 |
|
|
Sep 04 03:32:51 AM UTC 24 |
Sep 04 03:33:08 AM UTC 24 |
494878601 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.3417532238 |
|
|
Sep 04 03:32:22 AM UTC 24 |
Sep 04 03:33:27 AM UTC 24 |
4828884194 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.1509727196 |
|
|
Sep 04 03:30:08 AM UTC 24 |
Sep 04 03:33:32 AM UTC 24 |
60910626909 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.2944075321 |
|
|
Sep 04 03:31:31 AM UTC 24 |
Sep 04 03:33:32 AM UTC 24 |
49771538171 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_executable.1297522977 |
|
|
Sep 04 03:21:39 AM UTC 24 |
Sep 04 03:33:34 AM UTC 24 |
13133484739 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.1706566244 |
|
|
Sep 04 03:20:48 AM UTC 24 |
Sep 04 03:33:43 AM UTC 24 |
27242194438 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.3179583124 |
|
|
Sep 04 03:32:12 AM UTC 24 |
Sep 04 03:33:50 AM UTC 24 |
1457722309 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access.1134929932 |
|
|
Sep 04 03:33:33 AM UTC 24 |
Sep 04 03:33:56 AM UTC 24 |
3909299399 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.3465072344 |
|
|
Sep 04 03:33:34 AM UTC 24 |
Sep 04 03:33:59 AM UTC 24 |
2896401245 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.2773277032 |
|
|
Sep 04 03:33:44 AM UTC 24 |
Sep 04 03:34:04 AM UTC 24 |
2781355191 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_regwen.4233300777 |
|
|
Sep 04 03:16:41 AM UTC 24 |
Sep 04 03:34:09 AM UTC 24 |
86351938179 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.2455804442 |
|
|
Sep 04 03:34:10 AM UTC 24 |
Sep 04 03:34:17 AM UTC 24 |
422542151 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.3866476007 |
|
|
Sep 04 03:25:48 AM UTC 24 |
Sep 04 03:34:24 AM UTC 24 |
28170107316 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.2650966848 |
|
|
Sep 04 03:28:41 AM UTC 24 |
Sep 04 03:34:35 AM UTC 24 |
17934601159 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.2893710615 |
|
|
Sep 04 03:33:57 AM UTC 24 |
Sep 04 03:34:52 AM UTC 24 |
4435669184 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.2799849659 |
|
|
Sep 04 03:27:26 AM UTC 24 |
Sep 04 03:34:56 AM UTC 24 |
6323772199 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_alert_test.3456765165 |
|
|
Sep 04 03:34:56 AM UTC 24 |
Sep 04 03:34:58 AM UTC 24 |
34192883 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_bijection.2980299618 |
|
|
Sep 04 03:02:35 AM UTC 24 |
Sep 04 03:35:20 AM UTC 24 |
34198924453 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3569702773 |
|
|
Sep 04 03:34:36 AM UTC 24 |
Sep 04 03:35:27 AM UTC 24 |
1271556726 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.3179227008 |
|
|
Sep 04 03:31:09 AM UTC 24 |
Sep 04 03:35:40 AM UTC 24 |
13915150850 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_regwen.1416995669 |
|
|
Sep 04 03:31:58 AM UTC 24 |
Sep 04 03:36:16 AM UTC 24 |
2227037131 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.3567651487 |
|
|
Sep 04 03:29:27 AM UTC 24 |
Sep 04 03:36:23 AM UTC 24 |
5180660563 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_executable.4262190588 |
|
|
Sep 04 03:24:01 AM UTC 24 |
Sep 04 03:36:24 AM UTC 24 |
36843032793 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.2853598378 |
|
|
Sep 04 03:34:25 AM UTC 24 |
Sep 04 03:36:25 AM UTC 24 |
5041553828 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access.2118658926 |
|
|
Sep 04 03:36:17 AM UTC 24 |
Sep 04 03:36:26 AM UTC 24 |
828182696 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_smoke.1307024406 |
|
|
Sep 04 03:34:59 AM UTC 24 |
Sep 04 03:36:33 AM UTC 24 |
2958671253 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_bijection.947582828 |
|
|
Sep 04 03:20:33 AM UTC 24 |
Sep 04 03:36:54 AM UTC 24 |
15066705904 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.1368281877 |
|
|
Sep 04 03:36:26 AM UTC 24 |
Sep 04 03:37:10 AM UTC 24 |
891110005 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.3317949175 |
|
|
Sep 04 03:16:33 AM UTC 24 |
Sep 04 03:37:18 AM UTC 24 |
15331217883 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.313187988 |
|
|
Sep 04 03:32:08 AM UTC 24 |
Sep 04 03:37:24 AM UTC 24 |
13953748149 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.1679898939 |
|
|
Sep 04 03:37:19 AM UTC 24 |
Sep 04 03:37:27 AM UTC 24 |
358504502 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.3830190584 |
|
|
Sep 04 03:36:26 AM UTC 24 |
Sep 04 03:37:32 AM UTC 24 |
5879910355 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.1943087808 |
|
|
Sep 04 03:29:29 AM UTC 24 |
Sep 04 03:37:34 AM UTC 24 |
36832232305 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1905569305 |
|
|
Sep 04 03:37:33 AM UTC 24 |
Sep 04 03:37:51 AM UTC 24 |
689190412 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_alert_test.3184533735 |
|
|
Sep 04 03:37:52 AM UTC 24 |
Sep 04 03:37:54 AM UTC 24 |
24742808 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.1839789119 |
|
|
Sep 04 03:36:25 AM UTC 24 |
Sep 04 03:37:54 AM UTC 24 |
3053723309 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_smoke.384975302 |
|
|
Sep 04 03:59:28 AM UTC 24 |
Sep 04 03:59:51 AM UTC 24 |
4090233457 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.1754668575 |
|
|
Sep 04 03:23:48 AM UTC 24 |
Sep 04 03:38:44 AM UTC 24 |
25777593907 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.3481062785 |
|
|
Sep 04 03:34:18 AM UTC 24 |
Sep 04 03:38:50 AM UTC 24 |
5419672692 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.3524306274 |
|
|
Sep 04 03:33:33 AM UTC 24 |
Sep 04 03:38:52 AM UTC 24 |
9750875126 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.946124744 |
|
|
Sep 04 03:33:28 AM UTC 24 |
Sep 04 03:38:59 AM UTC 24 |
10524221251 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access.3893305386 |
|
|
Sep 04 03:38:52 AM UTC 24 |
Sep 04 03:39:05 AM UTC 24 |
2480415488 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.4144040377 |
|
|
Sep 04 03:38:59 AM UTC 24 |
Sep 04 03:39:12 AM UTC 24 |
1403622086 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.1292551366 |
|
|
Sep 04 03:39:06 AM UTC 24 |
Sep 04 03:39:20 AM UTC 24 |
2810826739 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.1462787119 |
|
|
Sep 04 03:39:13 AM UTC 24 |
Sep 04 03:39:33 AM UTC 24 |
3583960391 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.3051330473 |
|
|
Sep 04 03:13:33 AM UTC 24 |
Sep 04 03:39:35 AM UTC 24 |
692242863123 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_smoke.3852197558 |
|
|
Sep 04 03:37:57 AM UTC 24 |
Sep 04 03:39:46 AM UTC 24 |
4428690449 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.1005543467 |
|
|
Sep 04 03:39:47 AM UTC 24 |
Sep 04 03:39:53 AM UTC 24 |
349343647 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_bijection.1121757584 |
|
|
Sep 04 03:24:51 AM UTC 24 |
Sep 04 03:39:56 AM UTC 24 |
462699614556 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.1593840410 |
|
|
Sep 04 03:29:12 AM UTC 24 |
Sep 04 03:40:04 AM UTC 24 |
12677153011 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_executable.688154694 |
|
|
Sep 04 03:18:45 AM UTC 24 |
Sep 04 03:40:05 AM UTC 24 |
80815802585 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.4080900775 |
|
|
Sep 04 03:37:28 AM UTC 24 |
Sep 04 03:40:10 AM UTC 24 |
10119939452 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_alert_test.296641778 |
|
|
Sep 04 03:40:10 AM UTC 24 |
Sep 04 03:40:12 AM UTC 24 |
13696511 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.823261707 |
|
|
Sep 04 03:31:10 AM UTC 24 |
Sep 04 03:40:16 AM UTC 24 |
63975535376 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.3895948216 |
|
|
Sep 04 03:33:51 AM UTC 24 |
Sep 04 03:40:34 AM UTC 24 |
305162537147 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.3279357363 |
|
|
Sep 04 03:29:46 AM UTC 24 |
Sep 04 03:40:54 AM UTC 24 |
295005659528 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_regwen.3527945227 |
|
|
Sep 04 03:37:11 AM UTC 24 |
Sep 04 03:41:10 AM UTC 24 |
15212599935 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.3569570403 |
|
|
Sep 04 03:39:57 AM UTC 24 |
Sep 04 03:41:20 AM UTC 24 |
2625090369 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_smoke.1615853961 |
|
|
Sep 04 03:40:13 AM UTC 24 |
Sep 04 03:41:21 AM UTC 24 |
3062525597 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access.1464873925 |
|
|
Sep 04 03:41:11 AM UTC 24 |
Sep 04 03:41:23 AM UTC 24 |
3506412720 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all.272034733 |
|
|
Sep 04 03:04:58 AM UTC 24 |
Sep 04 03:41:34 AM UTC 24 |
217550716206 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3274307030 |
|
|
Sep 04 03:40:04 AM UTC 24 |
Sep 04 03:41:47 AM UTC 24 |
3065501753 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.1058243527 |
|
|
Sep 04 03:30:59 AM UTC 24 |
Sep 04 03:42:00 AM UTC 24 |
15635190418 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.1709840845 |
|
|
Sep 04 03:41:23 AM UTC 24 |
Sep 04 03:42:07 AM UTC 24 |
865750468 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.1588926890 |
|
|
Sep 04 03:36:24 AM UTC 24 |
Sep 04 03:42:10 AM UTC 24 |
11876854590 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.215369991 |
|
|
Sep 04 03:42:11 AM UTC 24 |
Sep 04 03:42:22 AM UTC 24 |
6675815433 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.3336888066 |
|
|
Sep 04 03:41:34 AM UTC 24 |
Sep 04 03:42:24 AM UTC 24 |
7732999812 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.3062663877 |
|
|
Sep 04 03:41:22 AM UTC 24 |
Sep 04 03:42:31 AM UTC 24 |
1664433369 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.2749032247 |
|
|
Sep 04 03:35:41 AM UTC 24 |
Sep 04 03:42:36 AM UTC 24 |
5447397510 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.2904412740 |
|
|
Sep 04 03:37:25 AM UTC 24 |
Sep 04 03:42:45 AM UTC 24 |
3945085322 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_alert_test.2998025822 |
|
|
Sep 04 03:42:46 AM UTC 24 |
Sep 04 03:42:48 AM UTC 24 |
17659728 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_bijection.2751476468 |
|
|
Sep 04 03:05:04 AM UTC 24 |
Sep 04 03:42:57 AM UTC 24 |
132626596970 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all.1788578823 |
|
|
Sep 04 03:22:33 AM UTC 24 |
Sep 04 03:43:10 AM UTC 24 |
25465749675 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_smoke.1233331813 |
|
|
Sep 04 03:42:49 AM UTC 24 |
Sep 04 03:43:41 AM UTC 24 |
816935624 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_executable.2248285449 |
|
|
Sep 04 03:34:00 AM UTC 24 |
Sep 04 03:43:45 AM UTC 24 |
72872672269 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_executable.3256756903 |
|
|
Sep 04 03:25:56 AM UTC 24 |
Sep 04 03:43:59 AM UTC 24 |
23581553140 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access.17589345 |
|
|
Sep 04 03:43:47 AM UTC 24 |
Sep 04 03:44:04 AM UTC 24 |
711463504 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.2867497721 |
|
|
Sep 04 03:41:48 AM UTC 24 |
Sep 04 03:44:09 AM UTC 24 |
6680797997 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.541382458 |
|
|
Sep 04 03:38:51 AM UTC 24 |
Sep 04 03:44:09 AM UTC 24 |
3818086956 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.3578398991 |
|
|
Sep 04 03:44:05 AM UTC 24 |
Sep 04 03:44:28 AM UTC 24 |
2626629168 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.954731489 |
|
|
Sep 04 03:35:20 AM UTC 24 |
Sep 04 03:44:59 AM UTC 24 |
7240924464 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.2093944840 |
|
|
Sep 04 03:13:31 AM UTC 24 |
Sep 04 03:45:05 AM UTC 24 |
62722146816 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_bijection.47897266 |
|
|
Sep 04 03:03:35 AM UTC 24 |
Sep 04 03:45:18 AM UTC 24 |
606878859928 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.2038983215 |
|
|
Sep 04 03:44:10 AM UTC 24 |
Sep 04 03:45:20 AM UTC 24 |
3015828405 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.3391674200 |
|
|
Sep 04 03:44:10 AM UTC 24 |
Sep 04 03:45:21 AM UTC 24 |
27637549777 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.404492444 |
|
|
Sep 04 03:45:19 AM UTC 24 |
Sep 04 03:45:26 AM UTC 24 |
1411110167 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2347943208 |
|
|
Sep 04 03:42:32 AM UTC 24 |
Sep 04 03:45:27 AM UTC 24 |
2331045765 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.30939377 |
|
|
Sep 04 03:42:25 AM UTC 24 |
Sep 04 03:45:30 AM UTC 24 |
22351250959 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.3031204920 |
|
|
Sep 04 03:28:09 AM UTC 24 |
Sep 04 03:45:30 AM UTC 24 |
22696581221 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_alert_test.1354495715 |
|
|
Sep 04 03:45:31 AM UTC 24 |
Sep 04 03:45:33 AM UTC 24 |
14312343 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_smoke.3187049148 |
|
|
Sep 04 03:45:31 AM UTC 24 |
Sep 04 03:45:51 AM UTC 24 |
1033958059 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.2010979861 |
|
|
Sep 04 03:42:23 AM UTC 24 |
Sep 04 03:45:53 AM UTC 24 |
43156882977 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.366178731 |
|
|
Sep 04 03:45:27 AM UTC 24 |
Sep 04 03:46:00 AM UTC 24 |
3150556518 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.1217363118 |
|
|
Sep 04 03:32:52 AM UTC 24 |
Sep 04 03:46:16 AM UTC 24 |
37190496878 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_bijection.1411061667 |
|
|
Sep 04 03:31:02 AM UTC 24 |
Sep 04 03:46:22 AM UTC 24 |
32426423550 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access.2265385163 |
|
|
Sep 04 03:46:00 AM UTC 24 |
Sep 04 03:46:27 AM UTC 24 |
3663013639 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.3201235636 |
|
|
Sep 04 03:39:54 AM UTC 24 |
Sep 04 03:46:36 AM UTC 24 |
18435329078 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.3318972760 |
|
|
Sep 04 03:46:28 AM UTC 24 |
Sep 04 03:46:45 AM UTC 24 |
711621462 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_executable.2803210461 |
|
|
Sep 04 03:31:50 AM UTC 24 |
Sep 04 03:46:46 AM UTC 24 |
81225698761 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.3186939147 |
|
|
Sep 04 03:45:22 AM UTC 24 |
Sep 04 03:46:54 AM UTC 24 |
2490586063 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.677243616 |
|
|
Sep 04 03:38:52 AM UTC 24 |
Sep 04 03:46:54 AM UTC 24 |
73188578829 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_regwen.245443222 |
|
|
Sep 04 03:34:05 AM UTC 24 |
Sep 04 03:46:55 AM UTC 24 |
13767067706 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.1685878995 |
|
|
Sep 04 03:46:55 AM UTC 24 |
Sep 04 03:47:01 AM UTC 24 |
3356543728 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.1436584318 |
|
|
Sep 04 03:46:24 AM UTC 24 |
Sep 04 03:47:16 AM UTC 24 |
1466424390 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.3345231337 |
|
|
Sep 04 03:41:20 AM UTC 24 |
Sep 04 03:47:19 AM UTC 24 |
11415422004 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.110312097 |
|
|
Sep 04 03:09:00 AM UTC 24 |
Sep 04 03:47:32 AM UTC 24 |
77006246793 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_alert_test.1950943386 |
|
|
Sep 04 03:47:33 AM UTC 24 |
Sep 04 03:47:35 AM UTC 24 |
19801545 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.1160663920 |
|
|
Sep 04 03:44:00 AM UTC 24 |
Sep 04 03:47:42 AM UTC 24 |
11919889330 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.601892231 |
|
|
Sep 04 03:39:21 AM UTC 24 |
Sep 04 03:47:57 AM UTC 24 |
37114145358 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.1147343780 |
|
|
Sep 04 03:12:24 AM UTC 24 |
Sep 04 03:48:02 AM UTC 24 |
72631219371 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_regwen.3604305744 |
|
|
Sep 04 03:26:00 AM UTC 24 |
Sep 04 03:48:04 AM UTC 24 |
6880143346 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_smoke.3168223842 |
|
|
Sep 04 03:47:36 AM UTC 24 |
Sep 04 03:48:23 AM UTC 24 |
411343845 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access.1817814973 |
|
|
Sep 04 03:48:05 AM UTC 24 |
Sep 04 03:48:26 AM UTC 24 |
1086424831 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.3208529812 |
|
|
Sep 04 03:46:38 AM UTC 24 |
Sep 04 03:48:37 AM UTC 24 |
85380911926 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.1964038892 |
|
|
Sep 04 03:45:21 AM UTC 24 |
Sep 04 03:48:41 AM UTC 24 |
10806308754 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.933352796 |
|
|
Sep 04 03:40:55 AM UTC 24 |
Sep 04 03:48:41 AM UTC 24 |
23572129125 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_bijection.1259059608 |
|
|
Sep 04 03:29:24 AM UTC 24 |
Sep 04 03:48:47 AM UTC 24 |
66943737715 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.2303091461 |
|
|
Sep 04 03:47:02 AM UTC 24 |
Sep 04 03:48:47 AM UTC 24 |
10693239084 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.420817535 |
|
|
Sep 04 03:43:43 AM UTC 24 |
Sep 04 03:48:51 AM UTC 24 |
4158090216 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_bijection.1524368454 |
|
|
Sep 04 03:02:32 AM UTC 24 |
Sep 04 03:48:53 AM UTC 24 |
526698183340 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.253609790 |
|
|
Sep 04 03:45:54 AM UTC 24 |
Sep 04 03:48:54 AM UTC 24 |
5902495899 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_bijection.512569968 |
|
|
Sep 04 03:27:00 AM UTC 24 |
Sep 04 03:48:56 AM UTC 24 |
133481443402 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.1820629041 |
|
|
Sep 04 03:48:52 AM UTC 24 |
Sep 04 03:48:59 AM UTC 24 |
526017931 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.1266967377 |
|
|
Sep 04 03:40:18 AM UTC 24 |
Sep 04 03:49:03 AM UTC 24 |
18198865315 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.4050385119 |
|
|
Sep 04 03:48:41 AM UTC 24 |
Sep 04 03:49:04 AM UTC 24 |
4507022845 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_alert_test.3232119625 |
|
|
Sep 04 03:49:03 AM UTC 24 |
Sep 04 03:49:05 AM UTC 24 |
19185914 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.1655343746 |
|
|
Sep 04 03:48:37 AM UTC 24 |
Sep 04 03:49:11 AM UTC 24 |
3122499549 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.790130772 |
|
|
Sep 04 03:46:46 AM UTC 24 |
Sep 04 03:49:12 AM UTC 24 |
7160310058 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.942554182 |
|
|
Sep 04 03:48:57 AM UTC 24 |
Sep 04 03:49:13 AM UTC 24 |
2975027143 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.3966983501 |
|
|
Sep 04 03:31:40 AM UTC 24 |
Sep 04 03:49:32 AM UTC 24 |
20985528153 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_smoke.2851701508 |
|
|
Sep 04 03:49:05 AM UTC 24 |
Sep 04 03:49:33 AM UTC 24 |
3462733818 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.1231774719 |
|
|
Sep 04 03:48:27 AM UTC 24 |
Sep 04 03:49:39 AM UTC 24 |
791439628 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_executable.3769852224 |
|
|
Sep 04 03:39:35 AM UTC 24 |
Sep 04 03:49:41 AM UTC 24 |
27265539041 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access.3158844205 |
|
|
Sep 04 03:49:14 AM UTC 24 |
Sep 04 03:49:43 AM UTC 24 |
3654553622 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.2416836490 |
|
|
Sep 04 03:49:34 AM UTC 24 |
Sep 04 03:49:47 AM UTC 24 |
686727552 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_executable.1834540315 |
|
|
Sep 04 03:42:00 AM UTC 24 |
Sep 04 03:49:54 AM UTC 24 |
4985323823 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.959465295 |
|
|
Sep 04 03:49:40 AM UTC 24 |
Sep 04 03:50:01 AM UTC 24 |
1603425532 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.1955943475 |
|
|
Sep 04 03:49:55 AM UTC 24 |
Sep 04 03:50:02 AM UTC 24 |
1095672094 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_executable.3839579131 |
|
|
Sep 04 03:28:26 AM UTC 24 |
Sep 04 03:50:14 AM UTC 24 |
10803509170 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.4140582642 |
|
|
Sep 04 03:49:33 AM UTC 24 |
Sep 04 03:50:26 AM UTC 24 |
794632377 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.2715206932 |
|
|
Sep 04 03:42:58 AM UTC 24 |
Sep 04 03:50:56 AM UTC 24 |
33909587970 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_regwen.1272391968 |
|
|
Sep 04 03:39:36 AM UTC 24 |
Sep 04 03:50:57 AM UTC 24 |
4999809535 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_alert_test.2150121572 |
|
|
Sep 04 03:50:57 AM UTC 24 |
Sep 04 03:50:59 AM UTC 24 |
20865556 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.550427498 |
|
|
Sep 04 03:48:54 AM UTC 24 |
Sep 04 03:51:32 AM UTC 24 |
6922158609 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_smoke.3617620228 |
|
|
Sep 04 03:50:58 AM UTC 24 |
Sep 04 03:51:39 AM UTC 24 |
738943246 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.3198302211 |
|
|
Sep 04 03:50:03 AM UTC 24 |
Sep 04 03:51:46 AM UTC 24 |
1440953655 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.2804416482 |
|
|
Sep 04 03:48:03 AM UTC 24 |
Sep 04 03:52:05 AM UTC 24 |
2955357390 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access.3404884281 |
|
|
Sep 04 03:51:47 AM UTC 24 |
Sep 04 03:52:10 AM UTC 24 |
849306476 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3137129363 |
|
|
Sep 04 03:50:15 AM UTC 24 |
Sep 04 03:52:10 AM UTC 24 |
22351513794 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.2076974244 |
|
|
Sep 04 03:46:56 AM UTC 24 |
Sep 04 03:52:10 AM UTC 24 |
10723084669 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.1655041952 |
|
|
Sep 04 03:48:55 AM UTC 24 |
Sep 04 03:52:30 AM UTC 24 |
10218175202 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.3531298337 |
|
|
Sep 04 03:49:14 AM UTC 24 |
Sep 04 03:52:30 AM UTC 24 |
8427361144 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.3931615675 |
|
|
Sep 04 03:52:10 AM UTC 24 |
Sep 04 03:52:35 AM UTC 24 |
2900606796 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_executable.1825984864 |
|
|
Sep 04 03:36:54 AM UTC 24 |
Sep 04 03:53:10 AM UTC 24 |
24031170748 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.538742997 |
|
|
Sep 04 03:46:17 AM UTC 24 |
Sep 04 03:53:14 AM UTC 24 |
21035239913 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.3865777011 |
|
|
Sep 04 03:53:11 AM UTC 24 |
Sep 04 03:53:17 AM UTC 24 |
1366961856 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.2068651640 |
|
|
Sep 04 03:52:11 AM UTC 24 |
Sep 04 03:53:18 AM UTC 24 |
34075743480 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.1534929959 |
|
|
Sep 04 03:52:11 AM UTC 24 |
Sep 04 03:53:32 AM UTC 24 |
766597962 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_regwen.410818269 |
|
|
Sep 04 03:42:08 AM UTC 24 |
Sep 04 03:53:40 AM UTC 24 |
176787372691 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_alert_test.2955199859 |
|
|
Sep 04 03:53:41 AM UTC 24 |
Sep 04 03:53:43 AM UTC 24 |
44513421 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1112886873 |
|
|
Sep 04 03:53:19 AM UTC 24 |
Sep 04 03:53:59 AM UTC 24 |
946078812 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_smoke.1721086059 |
|
|
Sep 04 03:53:44 AM UTC 24 |
Sep 04 03:54:14 AM UTC 24 |
4817847566 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_regwen.1134623063 |
|
|
Sep 04 03:45:06 AM UTC 24 |
Sep 04 03:54:18 AM UTC 24 |
14429581125 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.1910424467 |
|
|
Sep 04 03:36:34 AM UTC 24 |
Sep 04 03:54:39 AM UTC 24 |
14106718290 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access.1661892600 |
|
|
Sep 04 03:54:40 AM UTC 24 |
Sep 04 03:54:49 AM UTC 24 |
1749710918 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.2299142743 |
|
|
Sep 04 03:49:17 AM UTC 24 |
Sep 04 03:54:57 AM UTC 24 |
5069917606 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all.2136164596 |
|
|
Sep 04 03:02:35 AM UTC 24 |
Sep 04 03:55:17 AM UTC 24 |
81968951585 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_bijection.2500224799 |
|
|
Sep 04 03:45:52 AM UTC 24 |
Sep 04 03:55:23 AM UTC 24 |
6964900102 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.669300210 |
|
|
Sep 04 03:55:18 AM UTC 24 |
Sep 04 03:55:31 AM UTC 24 |
2818544295 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.1563924110 |
|
|
Sep 04 03:48:23 AM UTC 24 |
Sep 04 03:55:35 AM UTC 24 |
5892873542 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_executable.2021494933 |
|
|
Sep 04 03:52:31 AM UTC 24 |
Sep 04 03:55:35 AM UTC 24 |
6764756215 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_bijection.1476563729 |
|
|
Sep 04 03:40:36 AM UTC 24 |
Sep 04 03:55:49 AM UTC 24 |
26446274421 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.605872234 |
|
|
Sep 04 03:55:50 AM UTC 24 |
Sep 04 03:55:56 AM UTC 24 |
1415940654 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.700815854 |
|
|
Sep 04 03:37:57 AM UTC 24 |
Sep 04 03:55:57 AM UTC 24 |
71854150479 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.4061370554 |
|
|
Sep 04 03:54:57 AM UTC 24 |
Sep 04 03:56:00 AM UTC 24 |
2138593658 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.2611183401 |
|
|
Sep 04 03:50:03 AM UTC 24 |
Sep 04 03:56:09 AM UTC 24 |
55286476382 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.2801855297 |
|
|
Sep 04 03:53:18 AM UTC 24 |
Sep 04 03:56:16 AM UTC 24 |
5453136183 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3805707009 |
|
|
Sep 04 03:56:00 AM UTC 24 |
Sep 04 03:56:17 AM UTC 24 |
2032781413 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_alert_test.3674616713 |
|
|
Sep 04 03:56:17 AM UTC 24 |
Sep 04 03:56:19 AM UTC 24 |
39512590 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.3062291804 |
|
|
Sep 04 03:52:31 AM UTC 24 |
Sep 04 03:56:23 AM UTC 24 |
13646531831 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.466109994 |
|
|
Sep 04 03:53:15 AM UTC 24 |
Sep 04 03:56:24 AM UTC 24 |
7206281115 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_smoke.1492357511 |
|
|
Sep 04 03:56:18 AM UTC 24 |
Sep 04 03:56:26 AM UTC 24 |
369757571 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.3096185741 |
|
|
Sep 04 03:51:40 AM UTC 24 |
Sep 04 03:57:01 AM UTC 24 |
4843525127 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.170926135 |
|
|
Sep 04 03:55:25 AM UTC 24 |
Sep 04 03:57:06 AM UTC 24 |
11000264770 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access.3189656020 |
|
|
Sep 04 03:56:27 AM UTC 24 |
Sep 04 03:57:07 AM UTC 24 |
6894446634 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.1385095831 |
|
|
Sep 04 03:57:07 AM UTC 24 |
Sep 04 03:58:03 AM UTC 24 |
3872411115 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.1472514434 |
|
|
Sep 04 03:52:05 AM UTC 24 |
Sep 04 03:58:06 AM UTC 24 |
115969229579 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.3313800558 |
|
|
Sep 04 03:55:58 AM UTC 24 |
Sep 04 03:58:19 AM UTC 24 |
4474965594 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.1432493293 |
|
|
Sep 04 03:57:07 AM UTC 24 |
Sep 04 03:58:21 AM UTC 24 |
7544990823 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_regwen.3129303928 |
|
|
Sep 04 03:55:36 AM UTC 24 |
Sep 04 03:58:34 AM UTC 24 |
4865548697 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.1250795424 |
|
|
Sep 04 03:58:04 AM UTC 24 |
Sep 04 03:58:38 AM UTC 24 |
13016253403 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.1733382882 |
|
|
Sep 04 03:58:34 AM UTC 24 |
Sep 04 03:58:40 AM UTC 24 |
346467350 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.368940887 |
|
|
Sep 04 03:44:28 AM UTC 24 |
Sep 04 03:58:56 AM UTC 24 |
12549428306 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2215264525 |
|
|
Sep 04 03:58:58 AM UTC 24 |
Sep 04 03:59:21 AM UTC 24 |
365844908 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.1589616380 |
|
|
Sep 04 03:55:57 AM UTC 24 |
Sep 04 03:59:25 AM UTC 24 |
10354931503 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_alert_test.640881781 |
|
|
Sep 04 03:59:25 AM UTC 24 |
Sep 04 03:59:27 AM UTC 24 |
13226491 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.1308887653 |
|
|
Sep 04 03:55:32 AM UTC 24 |
Sep 04 03:59:35 AM UTC 24 |
19050175812 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.2052357562 |
|
|
Sep 04 03:54:19 AM UTC 24 |
Sep 04 04:00:13 AM UTC 24 |
9376578055 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_bijection.1782680310 |
|
|
Sep 04 03:51:33 AM UTC 24 |
Sep 04 04:00:31 AM UTC 24 |
23999140665 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.3785784699 |
|
|
Sep 04 03:45:34 AM UTC 24 |
Sep 04 04:00:52 AM UTC 24 |
64134062966 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_executable.1130792253 |
|
|
Sep 04 03:49:44 AM UTC 24 |
Sep 04 04:01:02 AM UTC 24 |
12571088110 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access.2855185142 |
|
|
Sep 04 04:00:32 AM UTC 24 |
Sep 04 04:01:06 AM UTC 24 |
2043419152 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.2431749639 |
|
|
Sep 04 03:56:24 AM UTC 24 |
Sep 04 04:01:39 AM UTC 24 |
8557814654 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.1592444293 |
|
|
Sep 04 03:54:50 AM UTC 24 |
Sep 04 04:01:57 AM UTC 24 |
12604328556 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.3159502135 |
|
|
Sep 04 03:58:41 AM UTC 24 |
Sep 04 04:02:13 AM UTC 24 |
24211144545 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.3497636646 |
|
|
Sep 04 04:01:03 AM UTC 24 |
Sep 04 04:02:15 AM UTC 24 |
844248992 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_regwen.1161970897 |
|
|
Sep 04 03:46:55 AM UTC 24 |
Sep 04 04:02:37 AM UTC 24 |
82438730925 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.992795369 |
|
|
Sep 04 04:02:38 AM UTC 24 |
Sep 04 04:02:44 AM UTC 24 |
575472992 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.2374600709 |
|
|
Sep 04 04:01:07 AM UTC 24 |
Sep 04 04:02:48 AM UTC 24 |
785981756 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_executable.2938013040 |
|
|
Sep 04 03:45:00 AM UTC 24 |
Sep 04 04:02:56 AM UTC 24 |
83109635950 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.888088675 |
|
|
Sep 04 04:00:13 AM UTC 24 |
Sep 04 04:02:58 AM UTC 24 |
3672299791 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.893652391 |
|
|
Sep 04 04:02:56 AM UTC 24 |
Sep 04 04:03:09 AM UTC 24 |
984660602 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_alert_test.774682480 |
|
|
Sep 04 04:03:10 AM UTC 24 |
Sep 04 04:03:11 AM UTC 24 |
10827856 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.1637224012 |
|
|
Sep 04 03:58:38 AM UTC 24 |
Sep 04 04:03:11 AM UTC 24 |
4068539476 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_executable.2727025178 |
|
|
Sep 04 03:58:19 AM UTC 24 |
Sep 04 04:03:13 AM UTC 24 |
4498376972 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_smoke.3686883121 |
|
|
Sep 04 04:03:13 AM UTC 24 |
Sep 04 04:03:27 AM UTC 24 |
846108176 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_bijection.4161027879 |
|
|
Sep 04 03:22:46 AM UTC 24 |
Sep 04 04:03:28 AM UTC 24 |
473039016053 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_executable.635976495 |
|
|
Sep 04 03:48:48 AM UTC 24 |
Sep 04 04:03:32 AM UTC 24 |
14542181815 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access.2996868871 |
|
|
Sep 04 04:03:29 AM UTC 24 |
Sep 04 04:03:47 AM UTC 24 |
1700824451 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_executable.4070482479 |
|
|
Sep 04 03:46:47 AM UTC 24 |
Sep 04 04:03:58 AM UTC 24 |
27472242329 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.2146940092 |
|
|
Sep 04 04:03:47 AM UTC 24 |
Sep 04 04:04:06 AM UTC 24 |
6192397420 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.614324034 |
|
|
Sep 04 04:03:59 AM UTC 24 |
Sep 04 04:04:11 AM UTC 24 |
2778984217 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.1483870518 |
|
|
Sep 04 04:01:41 AM UTC 24 |
Sep 04 04:04:15 AM UTC 24 |
14357567025 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_executable.3706952176 |
|
|
Sep 04 03:55:36 AM UTC 24 |
Sep 04 04:04:20 AM UTC 24 |
11088329254 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.512544834 |
|
|
Sep 04 04:01:59 AM UTC 24 |
Sep 04 04:04:32 AM UTC 24 |
6049581147 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.2717731322 |
|
|
Sep 04 03:57:01 AM UTC 24 |
Sep 04 04:04:33 AM UTC 24 |
26524298515 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.700222575 |
|
|
Sep 04 04:04:33 AM UTC 24 |
Sep 04 04:04:39 AM UTC 24 |
353326985 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.2850504626 |
|
|
Sep 04 04:02:48 AM UTC 24 |
Sep 04 04:04:39 AM UTC 24 |
9817065436 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.439855075 |
|
|
Sep 04 03:49:06 AM UTC 24 |
Sep 04 04:04:52 AM UTC 24 |
45788082963 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_regwen.3507540873 |
|
|
Sep 04 03:48:49 AM UTC 24 |
Sep 04 04:04:53 AM UTC 24 |
14113962442 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_regwen.2150457769 |
|
|
Sep 04 03:58:21 AM UTC 24 |
Sep 04 04:04:54 AM UTC 24 |
12418230107 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_alert_test.3724039461 |
|
|
Sep 04 04:04:53 AM UTC 24 |
Sep 04 04:04:55 AM UTC 24 |
61111555 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.3698178925 |
|
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Sep 04 04:04:07 AM UTC 24 |
Sep 04 04:05:06 AM UTC 24 |
10031481619 ps |