| T549 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_smoke.2101286924 |
|
|
Sep 04 04:04:55 AM UTC 24 |
Sep 04 04:05:16 AM UTC 24 |
1925923620 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_bijection.1321174365 |
|
|
Sep 04 03:54:15 AM UTC 24 |
Sep 04 04:05:19 AM UTC 24 |
58586776027 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access.3251435226 |
|
|
Sep 04 04:05:20 AM UTC 24 |
Sep 04 04:05:38 AM UTC 24 |
1420285478 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.2914328332 |
|
|
Sep 04 04:02:44 AM UTC 24 |
Sep 04 04:06:15 AM UTC 24 |
14398658519 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.4033738563 |
|
|
Sep 04 04:04:40 AM UTC 24 |
Sep 04 04:06:29 AM UTC 24 |
2736470303 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.2221388598 |
|
|
Sep 04 03:48:43 AM UTC 24 |
Sep 04 04:06:30 AM UTC 24 |
142490018201 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.487088945 |
|
|
Sep 04 04:06:29 AM UTC 24 |
Sep 04 04:06:42 AM UTC 24 |
2775705057 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.2502878726 |
|
|
Sep 04 03:47:43 AM UTC 24 |
Sep 04 04:06:50 AM UTC 24 |
15122224238 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2156231922 |
|
|
Sep 04 04:04:40 AM UTC 24 |
Sep 04 04:06:52 AM UTC 24 |
1365377402 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.340415025 |
|
|
Sep 04 04:04:33 AM UTC 24 |
Sep 04 04:07:05 AM UTC 24 |
5732126060 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.2939358847 |
|
|
Sep 04 04:06:16 AM UTC 24 |
Sep 04 04:07:10 AM UTC 24 |
754614459 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.3899877019 |
|
|
Sep 04 04:07:05 AM UTC 24 |
Sep 04 04:07:11 AM UTC 24 |
1474331256 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.2351127397 |
|
|
Sep 04 04:03:32 AM UTC 24 |
Sep 04 04:07:36 AM UTC 24 |
34669591685 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.3771338388 |
|
|
Sep 04 03:15:35 AM UTC 24 |
Sep 04 04:07:53 AM UTC 24 |
32249556923 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3045138765 |
|
|
Sep 04 04:07:37 AM UTC 24 |
Sep 04 04:07:56 AM UTC 24 |
2093116456 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_regwen.1120679041 |
|
|
Sep 04 03:49:47 AM UTC 24 |
Sep 04 04:07:58 AM UTC 24 |
66728141851 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_alert_test.3495838447 |
|
|
Sep 04 04:07:58 AM UTC 24 |
Sep 04 04:07:59 AM UTC 24 |
36074295 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_smoke.1768332608 |
|
|
Sep 04 04:07:59 AM UTC 24 |
Sep 04 04:08:15 AM UTC 24 |
716154721 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.1476458991 |
|
|
Sep 04 04:00:54 AM UTC 24 |
Sep 04 04:08:20 AM UTC 24 |
15138559331 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.1803617225 |
|
|
Sep 04 03:56:20 AM UTC 24 |
Sep 04 04:08:23 AM UTC 24 |
62916607848 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.1504112992 |
|
|
Sep 04 04:03:28 AM UTC 24 |
Sep 04 04:08:28 AM UTC 24 |
7902199331 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.2414761040 |
|
|
Sep 04 03:49:42 AM UTC 24 |
Sep 04 04:08:36 AM UTC 24 |
26145235433 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.770903213 |
|
|
Sep 04 04:07:11 AM UTC 24 |
Sep 04 04:08:41 AM UTC 24 |
5379951156 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access.4023172432 |
|
|
Sep 04 04:08:24 AM UTC 24 |
Sep 04 04:08:45 AM UTC 24 |
2323545644 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.2179701960 |
|
|
Sep 04 04:08:42 AM UTC 24 |
Sep 04 04:08:54 AM UTC 24 |
2785768153 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.2865554867 |
|
|
Sep 04 03:58:06 AM UTC 24 |
Sep 04 04:09:01 AM UTC 24 |
43352604087 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.3987180854 |
|
|
Sep 04 04:06:31 AM UTC 24 |
Sep 04 04:09:06 AM UTC 24 |
69129898417 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.3236454128 |
|
|
Sep 04 03:59:36 AM UTC 24 |
Sep 04 04:09:11 AM UTC 24 |
5819670751 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.1901980480 |
|
|
Sep 04 04:09:12 AM UTC 24 |
Sep 04 04:09:18 AM UTC 24 |
351174209 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all.2581588023 |
|
|
Sep 04 03:59:22 AM UTC 24 |
Sep 04 04:09:22 AM UTC 24 |
105023236845 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.41767196 |
|
|
Sep 04 04:08:37 AM UTC 24 |
Sep 04 04:09:38 AM UTC 24 |
3068252426 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_regwen.4202078574 |
|
|
Sep 04 03:52:36 AM UTC 24 |
Sep 04 04:09:49 AM UTC 24 |
12895181721 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1443793360 |
|
|
Sep 04 04:09:39 AM UTC 24 |
Sep 04 04:09:56 AM UTC 24 |
2064247308 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_alert_test.4221081955 |
|
|
Sep 04 04:09:57 AM UTC 24 |
Sep 04 04:09:59 AM UTC 24 |
20065415 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_smoke.1826190543 |
|
|
Sep 04 04:10:00 AM UTC 24 |
Sep 04 04:10:15 AM UTC 24 |
744536041 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_regwen.859653084 |
|
|
Sep 04 04:02:16 AM UTC 24 |
Sep 04 04:10:16 AM UTC 24 |
33075557844 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.1679866930 |
|
|
Sep 04 04:09:23 AM UTC 24 |
Sep 04 04:10:29 AM UTC 24 |
971225683 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.1788846278 |
|
|
Sep 04 04:08:47 AM UTC 24 |
Sep 04 04:10:38 AM UTC 24 |
9268064573 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_bijection.182601964 |
|
|
Sep 04 03:33:09 AM UTC 24 |
Sep 04 04:10:40 AM UTC 24 |
488769075442 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_bijection.2902105657 |
|
|
Sep 04 03:47:58 AM UTC 24 |
Sep 04 04:11:02 AM UTC 24 |
373762812473 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access.3468379302 |
|
|
Sep 04 04:10:39 AM UTC 24 |
Sep 04 04:11:08 AM UTC 24 |
3928288828 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_executable.718948769 |
|
|
Sep 04 04:06:51 AM UTC 24 |
Sep 04 04:11:12 AM UTC 24 |
4195512994 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.1968269848 |
|
|
Sep 04 03:51:01 AM UTC 24 |
Sep 04 04:11:39 AM UTC 24 |
59608200105 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.3613679231 |
|
|
Sep 04 04:11:02 AM UTC 24 |
Sep 04 04:11:47 AM UTC 24 |
770896050 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.458800907 |
|
|
Sep 04 04:05:17 AM UTC 24 |
Sep 04 04:12:15 AM UTC 24 |
5673884041 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.3258018589 |
|
|
Sep 04 04:11:13 AM UTC 24 |
Sep 04 04:12:31 AM UTC 24 |
42371134429 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.2426500382 |
|
|
Sep 04 04:05:39 AM UTC 24 |
Sep 04 04:12:37 AM UTC 24 |
21817450623 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.2302480000 |
|
|
Sep 04 04:12:32 AM UTC 24 |
Sep 04 04:12:39 AM UTC 24 |
1294802085 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.253042541 |
|
|
Sep 04 04:07:11 AM UTC 24 |
Sep 04 04:12:40 AM UTC 24 |
21884331976 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.295814955 |
|
|
Sep 04 04:04:12 AM UTC 24 |
Sep 04 04:12:50 AM UTC 24 |
22114221297 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.2496491221 |
|
|
Sep 04 04:11:09 AM UTC 24 |
Sep 04 04:12:57 AM UTC 24 |
1563057048 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1487571383 |
|
|
Sep 04 04:12:42 AM UTC 24 |
Sep 04 04:13:00 AM UTC 24 |
2254526291 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_alert_test.2762937837 |
|
|
Sep 04 04:12:58 AM UTC 24 |
Sep 04 04:13:00 AM UTC 24 |
36616960 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.2800574355 |
|
|
Sep 04 04:09:19 AM UTC 24 |
Sep 04 04:13:10 AM UTC 24 |
10358924614 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_executable.2997488332 |
|
|
Sep 04 04:11:48 AM UTC 24 |
Sep 04 04:13:12 AM UTC 24 |
1795375455 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_smoke.1517266062 |
|
|
Sep 04 04:13:00 AM UTC 24 |
Sep 04 04:13:20 AM UTC 24 |
4940872663 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access.2632019029 |
|
|
Sep 04 04:13:20 AM UTC 24 |
Sep 04 04:13:54 AM UTC 24 |
1067856626 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.58259488 |
|
|
Sep 04 04:10:29 AM UTC 24 |
Sep 04 04:13:56 AM UTC 24 |
26032073744 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.3579726881 |
|
|
Sep 04 03:13:07 AM UTC 24 |
Sep 04 04:14:08 AM UTC 24 |
270583831116 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_bijection.2154428192 |
|
|
Sep 04 03:56:24 AM UTC 24 |
Sep 04 04:14:10 AM UTC 24 |
101121908205 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.3978145977 |
|
|
Sep 04 04:08:29 AM UTC 24 |
Sep 04 04:14:21 AM UTC 24 |
12058341168 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.1233238855 |
|
|
Sep 04 04:14:09 AM UTC 24 |
Sep 04 04:14:34 AM UTC 24 |
736596163 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.1563095308 |
|
|
Sep 04 04:04:57 AM UTC 24 |
Sep 04 04:14:38 AM UTC 24 |
17844689158 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.2965270923 |
|
|
Sep 04 04:08:20 AM UTC 24 |
Sep 04 04:15:11 AM UTC 24 |
5006212361 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.3707579228 |
|
|
Sep 04 04:15:12 AM UTC 24 |
Sep 04 04:15:17 AM UTC 24 |
683743256 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.3438701012 |
|
|
Sep 04 04:14:11 AM UTC 24 |
Sep 04 04:15:28 AM UTC 24 |
40312156378 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.2575579493 |
|
|
Sep 04 04:13:57 AM UTC 24 |
Sep 04 04:15:30 AM UTC 24 |
3625120561 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2874596749 |
|
|
Sep 04 04:15:31 AM UTC 24 |
Sep 04 04:15:57 AM UTC 24 |
552043835 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.2089014686 |
|
|
Sep 04 04:12:41 AM UTC 24 |
Sep 04 04:16:01 AM UTC 24 |
19562202587 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_alert_test.1474872666 |
|
|
Sep 04 04:16:02 AM UTC 24 |
Sep 04 04:16:04 AM UTC 24 |
43586535 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_executable.3681596503 |
|
|
Sep 04 04:02:14 AM UTC 24 |
Sep 04 04:16:12 AM UTC 24 |
100299975290 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_executable.3693460366 |
|
|
Sep 04 04:14:34 AM UTC 24 |
Sep 04 04:16:15 AM UTC 24 |
4057074146 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.2729061358 |
|
|
Sep 04 04:12:37 AM UTC 24 |
Sep 04 04:16:19 AM UTC 24 |
25710595553 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.3576415301 |
|
|
Sep 04 04:10:40 AM UTC 24 |
Sep 04 04:17:08 AM UTC 24 |
25640345836 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.586556068 |
|
|
Sep 04 04:13:12 AM UTC 24 |
Sep 04 04:17:18 AM UTC 24 |
8793944977 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_executable.2435572177 |
|
|
Sep 04 04:04:16 AM UTC 24 |
Sep 04 04:17:27 AM UTC 24 |
74415738500 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.3343289321 |
|
|
Sep 04 04:15:30 AM UTC 24 |
Sep 04 04:17:31 AM UTC 24 |
5902496769 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.2981226066 |
|
|
Sep 04 04:11:41 AM UTC 24 |
Sep 04 04:17:31 AM UTC 24 |
20925547050 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.2950217296 |
|
|
Sep 04 04:17:28 AM UTC 24 |
Sep 04 04:17:39 AM UTC 24 |
702637521 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access.1939618160 |
|
|
Sep 04 04:17:09 AM UTC 24 |
Sep 04 04:17:44 AM UTC 24 |
1404937402 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.106148194 |
|
|
Sep 04 04:15:19 AM UTC 24 |
Sep 04 04:17:51 AM UTC 24 |
5485975296 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_bijection.43522238 |
|
|
Sep 04 04:08:16 AM UTC 24 |
Sep 04 04:17:52 AM UTC 24 |
24269199554 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_smoke.3397132464 |
|
|
Sep 04 04:16:05 AM UTC 24 |
Sep 04 04:17:58 AM UTC 24 |
2042821466 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.297314168 |
|
|
Sep 04 04:17:52 AM UTC 24 |
Sep 04 04:17:58 AM UTC 24 |
364908224 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_regwen.1265807075 |
|
|
Sep 04 04:14:39 AM UTC 24 |
Sep 04 04:18:12 AM UTC 24 |
9022130127 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.1465959806 |
|
|
Sep 04 04:17:32 AM UTC 24 |
Sep 04 04:18:28 AM UTC 24 |
6349105521 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_bijection.2943228925 |
|
|
Sep 04 03:35:28 AM UTC 24 |
Sep 04 04:18:29 AM UTC 24 |
261377670420 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_alert_test.993871996 |
|
|
Sep 04 04:18:29 AM UTC 24 |
Sep 04 04:18:31 AM UTC 24 |
45145025 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.2731943872 |
|
|
Sep 04 04:17:58 AM UTC 24 |
Sep 04 04:18:41 AM UTC 24 |
2843398193 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.1820379400 |
|
|
Sep 04 04:17:32 AM UTC 24 |
Sep 04 04:18:41 AM UTC 24 |
796570285 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_smoke.3730185782 |
|
|
Sep 04 04:18:30 AM UTC 24 |
Sep 04 04:18:48 AM UTC 24 |
872547444 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_bijection.997541626 |
|
|
Sep 04 03:49:12 AM UTC 24 |
Sep 04 04:18:50 AM UTC 24 |
84657944470 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.2826124057 |
|
|
Sep 04 03:54:00 AM UTC 24 |
Sep 04 04:19:06 AM UTC 24 |
51685078428 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.1572674569 |
|
|
Sep 04 04:17:58 AM UTC 24 |
Sep 04 04:19:27 AM UTC 24 |
12288809264 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.3370332576 |
|
|
Sep 04 04:19:06 AM UTC 24 |
Sep 04 04:19:27 AM UTC 24 |
764496205 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access.2093261942 |
|
|
Sep 04 04:18:49 AM UTC 24 |
Sep 04 04:19:55 AM UTC 24 |
1897801236 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.2740750889 |
|
|
Sep 04 04:13:56 AM UTC 24 |
Sep 04 04:20:32 AM UTC 24 |
26296348909 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.683091674 |
|
|
Sep 04 04:19:29 AM UTC 24 |
Sep 04 04:20:43 AM UTC 24 |
8266698628 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.2647297198 |
|
|
Sep 04 04:19:28 AM UTC 24 |
Sep 04 04:21:01 AM UTC 24 |
1556660236 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.2472544629 |
|
|
Sep 04 04:21:02 AM UTC 24 |
Sep 04 04:21:09 AM UTC 24 |
358425035 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.1929331281 |
|
|
Sep 04 04:13:01 AM UTC 24 |
Sep 04 04:21:18 AM UTC 24 |
64244083609 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_bijection.1516252215 |
|
|
Sep 04 03:43:10 AM UTC 24 |
Sep 04 04:21:19 AM UTC 24 |
469084113835 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.3849022045 |
|
|
Sep 04 04:16:20 AM UTC 24 |
Sep 04 04:21:25 AM UTC 24 |
4173679315 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_regwen.88460540 |
|
|
Sep 04 04:04:20 AM UTC 24 |
Sep 04 04:21:28 AM UTC 24 |
12581863082 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_alert_test.1906096246 |
|
|
Sep 04 04:21:29 AM UTC 24 |
Sep 04 04:21:31 AM UTC 24 |
40896551 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3709161568 |
|
|
Sep 04 04:21:20 AM UTC 24 |
Sep 04 04:21:32 AM UTC 24 |
684328704 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.4189545152 |
|
|
Sep 04 04:17:35 AM UTC 24 |
Sep 04 04:22:00 AM UTC 24 |
4232723177 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_smoke.515513953 |
|
|
Sep 04 04:21:32 AM UTC 24 |
Sep 04 04:22:01 AM UTC 24 |
4930972962 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all.2732101777 |
|
|
Sep 04 03:20:13 AM UTC 24 |
Sep 04 04:22:05 AM UTC 24 |
254859554284 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.3459458862 |
|
|
Sep 04 04:17:19 AM UTC 24 |
Sep 04 04:22:10 AM UTC 24 |
4996446879 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all.3079171230 |
|
|
Sep 04 03:50:27 AM UTC 24 |
Sep 04 04:22:20 AM UTC 24 |
30754271591 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access.339245310 |
|
|
Sep 04 04:22:05 AM UTC 24 |
Sep 04 04:22:23 AM UTC 24 |
5211420320 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.3689320188 |
|
|
Sep 04 04:18:42 AM UTC 24 |
Sep 04 04:22:29 AM UTC 24 |
16192932943 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.794419652 |
|
|
Sep 04 04:22:24 AM UTC 24 |
Sep 04 04:22:47 AM UTC 24 |
1352729172 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_executable.2631452997 |
|
|
Sep 04 04:20:33 AM UTC 24 |
Sep 04 04:23:01 AM UTC 24 |
17495768170 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_regwen.3827408722 |
|
|
Sep 04 04:06:53 AM UTC 24 |
Sep 04 04:23:31 AM UTC 24 |
93424657677 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.2148598195 |
|
|
Sep 04 04:22:21 AM UTC 24 |
Sep 04 04:23:39 AM UTC 24 |
1567450162 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.1949143754 |
|
|
Sep 04 04:08:01 AM UTC 24 |
Sep 04 04:23:41 AM UTC 24 |
61091508617 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.230797782 |
|
|
Sep 04 04:23:40 AM UTC 24 |
Sep 04 04:23:47 AM UTC 24 |
353208628 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.767130635 |
|
|
Sep 04 04:22:30 AM UTC 24 |
Sep 04 04:23:48 AM UTC 24 |
10568737197 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1891029200 |
|
|
Sep 04 04:23:49 AM UTC 24 |
Sep 04 04:24:18 AM UTC 24 |
774140137 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.2660902526 |
|
|
Sep 04 04:21:19 AM UTC 24 |
Sep 04 04:25:05 AM UTC 24 |
17578389818 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_alert_test.1948127346 |
|
|
Sep 04 04:25:06 AM UTC 24 |
Sep 04 04:25:08 AM UTC 24 |
12944965 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.3595537167 |
|
|
Sep 04 04:23:48 AM UTC 24 |
Sep 04 04:25:35 AM UTC 24 |
2629663074 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.2505811297 |
|
|
Sep 04 04:22:02 AM UTC 24 |
Sep 04 04:25:41 AM UTC 24 |
12897061574 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.578693305 |
|
|
Sep 04 04:18:51 AM UTC 24 |
Sep 04 04:25:54 AM UTC 24 |
29741137090 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.2616748004 |
|
|
Sep 04 04:17:52 AM UTC 24 |
Sep 04 04:26:21 AM UTC 24 |
173007554270 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_smoke.4285463311 |
|
|
Sep 04 04:25:09 AM UTC 24 |
Sep 04 04:26:33 AM UTC 24 |
2417089352 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access.1578465429 |
|
|
Sep 04 04:26:22 AM UTC 24 |
Sep 04 04:26:36 AM UTC 24 |
1480082409 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.2753831278 |
|
|
Sep 04 04:19:56 AM UTC 24 |
Sep 04 04:27:27 AM UTC 24 |
28172871395 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.419097855 |
|
|
Sep 04 04:26:37 AM UTC 24 |
Sep 04 04:27:33 AM UTC 24 |
3078283443 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_executable.2905629267 |
|
|
Sep 04 04:09:02 AM UTC 24 |
Sep 04 04:27:34 AM UTC 24 |
9250812638 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.4236156681 |
|
|
Sep 04 04:21:11 AM UTC 24 |
Sep 04 04:28:05 AM UTC 24 |
115155436500 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.2772860757 |
|
|
Sep 04 04:22:11 AM UTC 24 |
Sep 04 04:28:12 AM UTC 24 |
5132308692 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.282607511 |
|
|
Sep 04 04:27:27 AM UTC 24 |
Sep 04 04:28:24 AM UTC 24 |
3056497658 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.1884211620 |
|
|
Sep 04 04:28:25 AM UTC 24 |
Sep 04 04:28:31 AM UTC 24 |
685305480 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.2766081628 |
|
|
Sep 04 04:27:34 AM UTC 24 |
Sep 04 04:28:31 AM UTC 24 |
6327936258 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_regwen.1889767779 |
|
|
Sep 04 04:20:43 AM UTC 24 |
Sep 04 04:28:55 AM UTC 24 |
27020708286 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.1604044163 |
|
|
Sep 04 04:16:13 AM UTC 24 |
Sep 04 04:29:01 AM UTC 24 |
15541046022 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.2993730150 |
|
|
Sep 04 04:22:47 AM UTC 24 |
Sep 04 04:29:03 AM UTC 24 |
34921153268 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_alert_test.1073707109 |
|
|
Sep 04 04:29:03 AM UTC 24 |
Sep 04 04:29:05 AM UTC 24 |
45188694 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all.1363458329 |
|
|
Sep 04 03:17:08 AM UTC 24 |
Sep 04 04:29:14 AM UTC 24 |
422958188500 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3341990582 |
|
|
Sep 04 04:28:56 AM UTC 24 |
Sep 04 04:29:26 AM UTC 24 |
740936969 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_smoke.1153480224 |
|
|
Sep 04 04:29:06 AM UTC 24 |
Sep 04 04:29:40 AM UTC 24 |
2210751646 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.1649648491 |
|
|
Sep 04 04:28:32 AM UTC 24 |
Sep 04 04:29:46 AM UTC 24 |
2369533229 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access.1139143707 |
|
|
Sep 04 04:29:47 AM UTC 24 |
Sep 04 04:30:00 AM UTC 24 |
2949666169 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.310867013 |
|
|
Sep 04 04:06:44 AM UTC 24 |
Sep 04 04:30:10 AM UTC 24 |
23534683915 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.1785246556 |
|
|
Sep 04 04:10:16 AM UTC 24 |
Sep 04 04:30:15 AM UTC 24 |
34710060763 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.1426732337 |
|
|
Sep 04 04:25:56 AM UTC 24 |
Sep 04 04:30:23 AM UTC 24 |
12934956820 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.2133761742 |
|
|
Sep 04 04:14:22 AM UTC 24 |
Sep 04 04:30:25 AM UTC 24 |
12622353965 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.2973902762 |
|
|
Sep 04 04:23:42 AM UTC 24 |
Sep 04 04:30:27 AM UTC 24 |
106399763534 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.661783080 |
|
|
Sep 04 04:30:16 AM UTC 24 |
Sep 04 04:30:27 AM UTC 24 |
1423870755 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.2636687660 |
|
|
Sep 04 04:30:10 AM UTC 24 |
Sep 04 04:30:47 AM UTC 24 |
14218579456 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.264883171 |
|
|
Sep 04 04:30:48 AM UTC 24 |
Sep 04 04:30:55 AM UTC 24 |
357499666 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all.2785673092 |
|
|
Sep 04 03:32:27 AM UTC 24 |
Sep 04 04:30:56 AM UTC 24 |
243515828859 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.2334110436 |
|
|
Sep 04 04:26:34 AM UTC 24 |
Sep 04 04:31:22 AM UTC 24 |
28584247397 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.4157408777 |
|
|
Sep 04 04:28:32 AM UTC 24 |
Sep 04 04:31:23 AM UTC 24 |
6971312385 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_executable.1983652104 |
|
|
Sep 04 04:17:40 AM UTC 24 |
Sep 04 04:31:32 AM UTC 24 |
9580162656 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_alert_test.3949082226 |
|
|
Sep 04 04:31:33 AM UTC 24 |
Sep 04 04:31:36 AM UTC 24 |
20531572 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.1311509742 |
|
|
Sep 04 04:30:24 AM UTC 24 |
Sep 04 04:31:42 AM UTC 24 |
20596524545 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1387039186 |
|
|
Sep 04 04:31:22 AM UTC 24 |
Sep 04 04:31:43 AM UTC 24 |
1240504655 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_regwen.584187605 |
|
|
Sep 04 04:09:07 AM UTC 24 |
Sep 04 04:31:45 AM UTC 24 |
20171638165 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all.1278339407 |
|
|
Sep 04 03:28:59 AM UTC 24 |
Sep 04 04:32:29 AM UTC 24 |
182281673073 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access.2054189882 |
|
|
Sep 04 04:31:58 AM UTC 24 |
Sep 04 04:32:29 AM UTC 24 |
1421208631 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.2513869954 |
|
|
Sep 04 04:08:55 AM UTC 24 |
Sep 04 04:32:30 AM UTC 24 |
64927496164 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_smoke.2039250642 |
|
|
Sep 04 04:31:37 AM UTC 24 |
Sep 04 04:32:31 AM UTC 24 |
749865021 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_regwen.1733595345 |
|
|
Sep 04 04:28:13 AM UTC 24 |
Sep 04 04:32:43 AM UTC 24 |
8825749771 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.159262676 |
|
|
Sep 04 04:32:30 AM UTC 24 |
Sep 04 04:32:59 AM UTC 24 |
1493118308 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_regwen.3312302053 |
|
|
Sep 04 04:17:45 AM UTC 24 |
Sep 04 04:33:21 AM UTC 24 |
6017192978 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.74505832 |
|
|
Sep 04 04:33:22 AM UTC 24 |
Sep 04 04:33:28 AM UTC 24 |
346762511 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.2844881535 |
|
|
Sep 04 04:32:30 AM UTC 24 |
Sep 04 04:33:29 AM UTC 24 |
753973887 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.80035818 |
|
|
Sep 04 04:30:56 AM UTC 24 |
Sep 04 04:33:38 AM UTC 24 |
4756290236 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_bijection.1549351288 |
|
|
Sep 04 04:10:17 AM UTC 24 |
Sep 04 04:33:40 AM UTC 24 |
41809394668 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.2664520195 |
|
|
Sep 04 04:30:55 AM UTC 24 |
Sep 04 04:33:57 AM UTC 24 |
20718184143 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_alert_test.60402434 |
|
|
Sep 04 04:33:58 AM UTC 24 |
Sep 04 04:33:59 AM UTC 24 |
32330062 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all.3581104758 |
|
|
Sep 04 04:07:53 AM UTC 24 |
Sep 04 04:34:01 AM UTC 24 |
28734082994 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_smoke.307543988 |
|
|
Sep 04 04:34:01 AM UTC 24 |
Sep 04 04:34:08 AM UTC 24 |
1416980701 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_bijection.135042706 |
|
|
Sep 04 04:13:11 AM UTC 24 |
Sep 04 04:34:12 AM UTC 24 |
51857092130 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.3107733031 |
|
|
Sep 04 04:31:43 AM UTC 24 |
Sep 04 04:34:15 AM UTC 24 |
24752495741 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.2931112161 |
|
|
Sep 04 04:18:32 AM UTC 24 |
Sep 04 04:34:22 AM UTC 24 |
72558193885 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access.1045679363 |
|
|
Sep 04 04:34:16 AM UTC 24 |
Sep 04 04:34:25 AM UTC 24 |
773875000 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.4024845713 |
|
|
Sep 04 04:33:38 AM UTC 24 |
Sep 04 04:34:29 AM UTC 24 |
1150812952 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.2646607849 |
|
|
Sep 04 04:32:31 AM UTC 24 |
Sep 04 04:34:40 AM UTC 24 |
15342371124 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_regwen.1993521382 |
|
|
Sep 04 04:30:28 AM UTC 24 |
Sep 04 04:34:41 AM UTC 24 |
4891814038 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.546366119 |
|
|
Sep 04 04:34:25 AM UTC 24 |
Sep 04 04:35:01 AM UTC 24 |
10062009636 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.301143876 |
|
|
Sep 04 04:29:41 AM UTC 24 |
Sep 04 04:35:32 AM UTC 24 |
23363524406 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.1295798481 |
|
|
Sep 04 04:33:29 AM UTC 24 |
Sep 04 04:35:56 AM UTC 24 |
5150981031 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.2651828399 |
|
|
Sep 04 04:30:26 AM UTC 24 |
Sep 04 04:35:59 AM UTC 24 |
7595075638 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.344634586 |
|
|
Sep 04 04:35:56 AM UTC 24 |
Sep 04 04:36:02 AM UTC 24 |
365541999 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.185672598 |
|
|
Sep 04 04:34:29 AM UTC 24 |
Sep 04 04:36:13 AM UTC 24 |
4618741320 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.413337132 |
|
|
Sep 04 04:34:42 AM UTC 24 |
Sep 04 04:36:22 AM UTC 24 |
27671508660 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.1302256269 |
|
|
Sep 04 04:33:29 AM UTC 24 |
Sep 04 04:36:26 AM UTC 24 |
8254124071 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.2700745969 |
|
|
Sep 04 04:31:46 AM UTC 24 |
Sep 04 04:36:29 AM UTC 24 |
88862849806 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_alert_test.3287312073 |
|
|
Sep 04 04:36:27 AM UTC 24 |
Sep 04 04:36:29 AM UTC 24 |
36135385 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.3563999773 |
|
|
Sep 04 03:12:02 AM UTC 24 |
Sep 04 04:36:38 AM UTC 24 |
72628184035 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_regwen.117401494 |
|
|
Sep 04 04:33:00 AM UTC 24 |
Sep 04 04:36:45 AM UTC 24 |
1449967465 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_smoke.3902767022 |
|
|
Sep 04 04:36:30 AM UTC 24 |
Sep 04 04:36:46 AM UTC 24 |
536012508 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access.4018954920 |
|
|
Sep 04 04:36:46 AM UTC 24 |
Sep 04 04:36:57 AM UTC 24 |
1526981754 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all.3858753831 |
|
|
Sep 04 03:34:53 AM UTC 24 |
Sep 04 04:37:01 AM UTC 24 |
235474265392 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.418810425 |
|
|
Sep 04 04:37:03 AM UTC 24 |
Sep 04 04:37:16 AM UTC 24 |
2776843753 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.913843525 |
|
|
Sep 04 04:37:18 AM UTC 24 |
Sep 04 04:37:28 AM UTC 24 |
692513176 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.3344159186 |
|
|
Sep 04 03:09:54 AM UTC 24 |
Sep 04 04:37:28 AM UTC 24 |
597197500960 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_bijection.938276263 |
|
|
Sep 04 04:25:42 AM UTC 24 |
Sep 04 04:37:38 AM UTC 24 |
129788176231 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_regwen.547100437 |
|
|
Sep 04 04:23:32 AM UTC 24 |
Sep 04 04:37:47 AM UTC 24 |
165400886706 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3243237881 |
|
|
Sep 04 04:36:14 AM UTC 24 |
Sep 04 04:37:50 AM UTC 24 |
11433639852 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.54718149 |
|
|
Sep 04 04:32:21 AM UTC 24 |
Sep 04 04:37:52 AM UTC 24 |
12814460363 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.2577882897 |
|
|
Sep 04 04:37:51 AM UTC 24 |
Sep 04 04:37:58 AM UTC 24 |
710599636 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_bijection.1606516039 |
|
|
Sep 04 04:18:42 AM UTC 24 |
Sep 04 04:38:09 AM UTC 24 |
124558305342 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.585031908 |
|
|
Sep 04 04:36:03 AM UTC 24 |
Sep 04 04:38:53 AM UTC 24 |
1808737306 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.2948925668 |
|
|
Sep 04 04:03:13 AM UTC 24 |
Sep 04 04:39:01 AM UTC 24 |
117844176852 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_alert_test.2674133817 |
|
|
Sep 04 04:39:02 AM UTC 24 |
Sep 04 04:39:04 AM UTC 24 |
21725038 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_smoke.944042548 |
|
|
Sep 04 04:39:05 AM UTC 24 |
Sep 04 04:39:13 AM UTC 24 |
1866126817 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.234410876 |
|
|
Sep 04 04:37:29 AM UTC 24 |
Sep 04 04:39:27 AM UTC 24 |
17623693138 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_executable.423431516 |
|
|
Sep 04 04:23:02 AM UTC 24 |
Sep 04 04:39:38 AM UTC 24 |
18867344500 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.3747544756 |
|
|
Sep 04 04:37:59 AM UTC 24 |
Sep 04 04:39:42 AM UTC 24 |
12823869940 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access.3477575634 |
|
|
Sep 04 04:39:43 AM UTC 24 |
Sep 04 04:39:53 AM UTC 24 |
2691369200 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2782663282 |
|
|
Sep 04 04:38:10 AM UTC 24 |
Sep 04 04:39:56 AM UTC 24 |
1930370384 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.2137924084 |
|
|
Sep 04 04:34:13 AM UTC 24 |
Sep 04 04:40:00 AM UTC 24 |
15946934257 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_bijection.63795357 |
|
|
Sep 04 03:59:52 AM UTC 24 |
Sep 04 04:40:01 AM UTC 24 |
516880828674 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.1993593803 |
|
|
Sep 04 04:32:33 AM UTC 24 |
Sep 04 04:40:08 AM UTC 24 |
27345422600 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.782707558 |
|
|
Sep 04 04:30:01 AM UTC 24 |
Sep 04 04:40:21 AM UTC 24 |
39917267674 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.3746379386 |
|
|
Sep 04 04:39:57 AM UTC 24 |
Sep 04 04:40:49 AM UTC 24 |
3218814703 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.1740488646 |
|
|
Sep 04 04:37:53 AM UTC 24 |
Sep 04 04:40:57 AM UTC 24 |
2741496185 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.1875216145 |
|
|
Sep 04 04:40:59 AM UTC 24 |
Sep 04 04:41:04 AM UTC 24 |
344236000 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_executable.2943141322 |
|
|
Sep 04 04:32:44 AM UTC 24 |
Sep 04 04:41:20 AM UTC 24 |
47377777640 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.2420419028 |
|
|
Sep 04 04:40:01 AM UTC 24 |
Sep 04 04:41:29 AM UTC 24 |
796519573 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.4225778229 |
|
|
Sep 04 04:40:02 AM UTC 24 |
Sep 04 04:41:33 AM UTC 24 |
11044731829 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.2828825501 |
|
|
Sep 04 04:34:23 AM UTC 24 |
Sep 04 04:41:38 AM UTC 24 |
29139748356 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_alert_test.3144920246 |
|
|
Sep 04 04:41:39 AM UTC 24 |
Sep 04 04:41:41 AM UTC 24 |
27132930 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all.2378321250 |
|
|
Sep 04 04:02:59 AM UTC 24 |
Sep 04 04:41:43 AM UTC 24 |
39890757998 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all.589102528 |
|
|
Sep 04 03:40:05 AM UTC 24 |
Sep 04 04:41:44 AM UTC 24 |
520635975436 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.4145084858 |
|
|
Sep 04 04:36:57 AM UTC 24 |
Sep 04 04:41:55 AM UTC 24 |
5503475239 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.1016079148 |
|
|
Sep 04 04:35:59 AM UTC 24 |
Sep 04 04:42:02 AM UTC 24 |
10719186354 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_bijection.3301718672 |
|
|
Sep 04 04:16:16 AM UTC 24 |
Sep 04 04:42:13 AM UTC 24 |
20029402761 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_bijection.1275785840 |
|
|
Sep 04 04:05:08 AM UTC 24 |
Sep 04 04:42:24 AM UTC 24 |
291793466186 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access.2263675539 |
|
|
Sep 04 04:42:03 AM UTC 24 |
Sep 04 04:42:31 AM UTC 24 |
2379397865 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_smoke.3041232572 |
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Sep 04 04:41:42 AM UTC 24 |
Sep 04 04:42:47 AM UTC 24 |
794551410 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3901816214 |
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Sep 04 04:41:30 AM UTC 24 |
Sep 04 04:43:19 AM UTC 24 |
2234260594 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all.1152030042 |
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|
Sep 04 03:30:31 AM UTC 24 |
Sep 04 04:43:25 AM UTC 24 |
454983969450 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.4176140383 |
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Sep 04 04:42:32 AM UTC 24 |
Sep 04 04:43:39 AM UTC 24 |
3136042190 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.1219114934 |
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Sep 04 04:42:48 AM UTC 24 |
Sep 04 04:43:43 AM UTC 24 |
23119068905 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.2246765220 |
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Sep 04 04:43:44 AM UTC 24 |
Sep 04 04:43:50 AM UTC 24 |
584711572 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.3162599707 |
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Sep 04 04:42:25 AM UTC 24 |
Sep 04 04:44:02 AM UTC 24 |
757804857 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.3404192317 |
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Sep 04 04:39:38 AM UTC 24 |
Sep 04 04:44:10 AM UTC 24 |
3737566655 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.1959986966 |
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Sep 04 04:41:21 AM UTC 24 |
Sep 04 04:44:13 AM UTC 24 |
5054260408 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.3466568000 |
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Sep 04 04:41:06 AM UTC 24 |
Sep 04 04:44:29 AM UTC 24 |
43060166456 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all.4062985100 |
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Sep 04 03:03:25 AM UTC 24 |
Sep 04 04:44:30 AM UTC 24 |
1063347737534 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_alert_test.1702679748 |
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Sep 04 04:44:29 AM UTC 24 |
Sep 04 04:44:31 AM UTC 24 |
15209318 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.3589192184 |
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Sep 04 04:29:15 AM UTC 24 |
Sep 04 04:44:36 AM UTC 24 |
33057767987 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3286018873 |
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Sep 04 04:44:11 AM UTC 24 |
Sep 04 04:44:38 AM UTC 24 |
537775742 ps |