| T797 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.1817686043 |
|
|
Sep 04 04:36:45 AM UTC 24 |
Sep 04 04:44:39 AM UTC 24 |
4846619614 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_executable.2938731310 |
|
|
Sep 04 04:30:28 AM UTC 24 |
Sep 04 04:44:44 AM UTC 24 |
51013749005 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all.5991994 |
|
|
Sep 04 04:12:51 AM UTC 24 |
Sep 04 04:44:55 AM UTC 24 |
55558557966 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_bijection.3386326737 |
|
|
Sep 04 04:34:08 AM UTC 24 |
Sep 04 04:45:00 AM UTC 24 |
34716612950 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.3561505483 |
|
|
Sep 04 04:53:28 AM UTC 24 |
Sep 04 04:55:29 AM UTC 24 |
7892322266 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access.769908620 |
|
|
Sep 04 04:44:40 AM UTC 24 |
Sep 04 04:45:03 AM UTC 24 |
881590588 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.2775953549 |
|
|
Sep 04 04:39:54 AM UTC 24 |
Sep 04 04:45:08 AM UTC 24 |
17815561861 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_smoke.1936108938 |
|
|
Sep 04 04:44:31 AM UTC 24 |
Sep 04 04:45:11 AM UTC 24 |
1520828565 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_executable.750705063 |
|
|
Sep 04 04:28:06 AM UTC 24 |
Sep 04 04:45:17 AM UTC 24 |
9970213652 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.2404844218 |
|
|
Sep 04 04:45:01 AM UTC 24 |
Sep 04 04:45:37 AM UTC 24 |
3279960640 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.3417023106 |
|
|
Sep 04 04:45:39 AM UTC 24 |
Sep 04 04:45:46 AM UTC 24 |
366318334 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_regwen.2584168306 |
|
|
Sep 04 04:43:41 AM UTC 24 |
Sep 04 04:45:57 AM UTC 24 |
4107569575 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.3972509507 |
|
|
Sep 04 04:37:29 AM UTC 24 |
Sep 04 04:45:59 AM UTC 24 |
19334138660 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_executable.3740967008 |
|
|
Sep 04 04:37:39 AM UTC 24 |
Sep 04 04:46:07 AM UTC 24 |
8176114325 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1531297656 |
|
|
Sep 04 04:46:00 AM UTC 24 |
Sep 04 04:46:13 AM UTC 24 |
473063586 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_alert_test.20829931 |
|
|
Sep 04 04:46:14 AM UTC 24 |
Sep 04 04:46:16 AM UTC 24 |
28607143 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_smoke.2304592081 |
|
|
Sep 04 04:46:17 AM UTC 24 |
Sep 04 04:46:29 AM UTC 24 |
515968881 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.2333878248 |
|
|
Sep 04 04:27:35 AM UTC 24 |
Sep 04 04:46:34 AM UTC 24 |
17104693158 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.4169829859 |
|
|
Sep 04 04:43:52 AM UTC 24 |
Sep 04 04:46:34 AM UTC 24 |
5264934228 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.3776672341 |
|
|
Sep 04 04:44:56 AM UTC 24 |
Sep 04 04:46:48 AM UTC 24 |
5116799815 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.2775801982 |
|
|
Sep 04 04:45:04 AM UTC 24 |
Sep 04 04:46:53 AM UTC 24 |
134923474709 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_regwen.3120674863 |
|
|
Sep 04 04:35:33 AM UTC 24 |
Sep 04 04:47:18 AM UTC 24 |
12902822156 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.2980656191 |
|
|
Sep 04 04:45:58 AM UTC 24 |
Sep 04 04:47:30 AM UTC 24 |
2175376350 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.440677548 |
|
|
Sep 04 04:44:03 AM UTC 24 |
Sep 04 04:47:31 AM UTC 24 |
44616923019 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access.3482433584 |
|
|
Sep 04 04:46:49 AM UTC 24 |
Sep 04 04:47:38 AM UTC 24 |
784366941 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.2251329403 |
|
|
Sep 04 04:47:19 AM UTC 24 |
Sep 04 04:47:40 AM UTC 24 |
1457340880 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.2260451749 |
|
|
Sep 04 04:47:30 AM UTC 24 |
Sep 04 04:47:45 AM UTC 24 |
745184941 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.3015812156 |
|
|
Sep 04 04:34:02 AM UTC 24 |
Sep 04 04:47:47 AM UTC 24 |
23470742284 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.3975375951 |
|
|
Sep 04 04:47:48 AM UTC 24 |
Sep 04 04:47:54 AM UTC 24 |
350133395 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_regwen.1030540127 |
|
|
Sep 04 04:40:49 AM UTC 24 |
Sep 04 04:48:14 AM UTC 24 |
4524973364 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all.954920808 |
|
|
Sep 04 04:15:58 AM UTC 24 |
Sep 04 04:48:31 AM UTC 24 |
76836697806 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.1983686157 |
|
|
Sep 04 04:47:31 AM UTC 24 |
Sep 04 04:48:35 AM UTC 24 |
25586296337 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.655385233 |
|
|
Sep 04 04:21:32 AM UTC 24 |
Sep 04 04:48:57 AM UTC 24 |
21359448111 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_alert_test.1154818998 |
|
|
Sep 04 04:48:57 AM UTC 24 |
Sep 04 04:48:59 AM UTC 24 |
35530889 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.4156896680 |
|
|
Sep 04 04:48:32 AM UTC 24 |
Sep 04 04:49:08 AM UTC 24 |
509909204 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_executable.534772624 |
|
|
Sep 04 04:40:22 AM UTC 24 |
Sep 04 04:49:15 AM UTC 24 |
13895857951 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.719478473 |
|
|
Sep 04 04:41:55 AM UTC 24 |
Sep 04 04:49:24 AM UTC 24 |
10532815893 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_smoke.2008778799 |
|
|
Sep 04 04:49:00 AM UTC 24 |
Sep 04 04:49:24 AM UTC 24 |
2556237362 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_regwen.3284069463 |
|
|
Sep 04 04:37:48 AM UTC 24 |
Sep 04 04:49:28 AM UTC 24 |
13065822548 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.441236882 |
|
|
Sep 04 04:45:47 AM UTC 24 |
Sep 04 04:49:30 AM UTC 24 |
10370104269 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.837953677 |
|
|
Sep 04 04:34:42 AM UTC 24 |
Sep 04 04:49:35 AM UTC 24 |
55797142875 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.3140565675 |
|
|
Sep 04 04:48:15 AM UTC 24 |
Sep 04 04:49:49 AM UTC 24 |
3173453441 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.1110402026 |
|
|
Sep 04 04:49:36 AM UTC 24 |
Sep 04 04:49:53 AM UTC 24 |
2912446870 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.2190275245 |
|
|
Sep 04 04:44:39 AM UTC 24 |
Sep 04 04:50:11 AM UTC 24 |
17749414233 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.3083592632 |
|
|
Sep 04 04:49:31 AM UTC 24 |
Sep 04 04:50:13 AM UTC 24 |
781916103 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.1397304124 |
|
|
Sep 04 04:42:14 AM UTC 24 |
Sep 04 04:50:22 AM UTC 24 |
34037287646 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.707491575 |
|
|
Sep 04 04:50:23 AM UTC 24 |
Sep 04 04:50:29 AM UTC 24 |
358749659 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.1663567742 |
|
|
Sep 04 04:39:14 AM UTC 24 |
Sep 04 04:50:47 AM UTC 24 |
79621503492 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.3813444947 |
|
|
Sep 04 04:25:35 AM UTC 24 |
Sep 04 04:50:56 AM UTC 24 |
23978477829 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access.4105076228 |
|
|
Sep 04 04:49:25 AM UTC 24 |
Sep 04 04:51:01 AM UTC 24 |
871950307 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.2381750358 |
|
|
Sep 04 04:49:50 AM UTC 24 |
Sep 04 04:51:19 AM UTC 24 |
19285426697 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_alert_test.247732204 |
|
|
Sep 04 04:51:20 AM UTC 24 |
Sep 04 04:51:22 AM UTC 24 |
33876193 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1679291450 |
|
|
Sep 04 04:50:57 AM UTC 24 |
Sep 04 04:51:32 AM UTC 24 |
847258146 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_executable.619012396 |
|
|
Sep 04 04:43:26 AM UTC 24 |
Sep 04 04:51:40 AM UTC 24 |
13284068175 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_smoke.1160750944 |
|
|
Sep 04 04:51:23 AM UTC 24 |
Sep 04 04:51:45 AM UTC 24 |
1952990774 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.1799533157 |
|
|
Sep 04 04:36:30 AM UTC 24 |
Sep 04 04:51:50 AM UTC 24 |
11046796462 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_executable.3118492885 |
|
|
Sep 04 04:50:12 AM UTC 24 |
Sep 04 04:52:12 AM UTC 24 |
6970026232 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_regwen.3620829402 |
|
|
Sep 04 04:47:45 AM UTC 24 |
Sep 04 04:52:13 AM UTC 24 |
5763175204 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access.2630505956 |
|
|
Sep 04 04:51:51 AM UTC 24 |
Sep 04 04:52:21 AM UTC 24 |
1910990342 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.2881372808 |
|
|
Sep 04 04:46:36 AM UTC 24 |
Sep 04 04:52:48 AM UTC 24 |
26609675275 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.100253564 |
|
|
Sep 04 04:44:45 AM UTC 24 |
Sep 04 04:53:00 AM UTC 24 |
73630729551 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.1319315668 |
|
|
Sep 04 04:52:22 AM UTC 24 |
Sep 04 04:53:04 AM UTC 24 |
752526303 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all.854790394 |
|
|
Sep 04 03:56:10 AM UTC 24 |
Sep 04 04:53:14 AM UTC 24 |
73856809120 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.66880208 |
|
|
Sep 04 04:40:09 AM UTC 24 |
Sep 04 04:53:26 AM UTC 24 |
58653251778 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.1187149982 |
|
|
Sep 04 04:52:48 AM UTC 24 |
Sep 04 04:53:27 AM UTC 24 |
3795272354 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.200648028 |
|
|
Sep 04 04:53:27 AM UTC 24 |
Sep 04 04:53:32 AM UTC 24 |
365931278 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.4037463079 |
|
|
Sep 04 04:47:55 AM UTC 24 |
Sep 04 04:53:32 AM UTC 24 |
32824459926 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.1216508852 |
|
|
Sep 04 04:52:14 AM UTC 24 |
Sep 04 04:53:58 AM UTC 24 |
1624384330 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.209553042 |
|
|
Sep 04 04:50:48 AM UTC 24 |
Sep 04 04:54:01 AM UTC 24 |
29505544471 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_alert_test.3813789349 |
|
|
Sep 04 04:54:01 AM UTC 24 |
Sep 04 04:54:03 AM UTC 24 |
21489380 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.2979805388 |
|
|
Sep 04 04:50:31 AM UTC 24 |
Sep 04 04:54:07 AM UTC 24 |
14432753708 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.3268752266 |
|
|
Sep 04 04:53:00 AM UTC 24 |
Sep 04 04:54:20 AM UTC 24 |
3253012906 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_executable.1686743241 |
|
|
Sep 04 04:35:02 AM UTC 24 |
Sep 04 04:54:24 AM UTC 24 |
68927702481 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.2314809198 |
|
|
Sep 04 04:49:25 AM UTC 24 |
Sep 04 04:54:34 AM UTC 24 |
6701709193 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.2383103571 |
|
|
Sep 04 04:49:54 AM UTC 24 |
Sep 04 04:54:51 AM UTC 24 |
6817581243 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.648908890 |
|
|
Sep 04 04:53:33 AM UTC 24 |
Sep 04 04:54:55 AM UTC 24 |
1655791391 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access.3833394409 |
|
|
Sep 04 04:54:36 AM UTC 24 |
Sep 04 04:55:06 AM UTC 24 |
895469575 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_smoke.3164719382 |
|
|
Sep 04 04:54:04 AM UTC 24 |
Sep 04 04:55:16 AM UTC 24 |
951230447 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.3502498573 |
|
|
Sep 04 04:55:06 AM UTC 24 |
Sep 04 04:55:23 AM UTC 24 |
1395330360 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_bijection.2846427563 |
|
|
Sep 04 04:41:45 AM UTC 24 |
Sep 04 04:55:35 AM UTC 24 |
24267175311 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.2704673818 |
|
|
Sep 04 04:55:17 AM UTC 24 |
Sep 04 04:55:51 AM UTC 24 |
4601676978 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_regwen.146783841 |
|
|
Sep 04 04:45:18 AM UTC 24 |
Sep 04 04:55:51 AM UTC 24 |
20299674158 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.1898709590 |
|
|
Sep 04 04:55:52 AM UTC 24 |
Sep 04 04:55:59 AM UTC 24 |
1401485818 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.2633793057 |
|
|
Sep 04 04:54:56 AM UTC 24 |
Sep 04 04:56:01 AM UTC 24 |
789074236 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.3351957494 |
|
|
Sep 04 04:53:32 AM UTC 24 |
Sep 04 04:56:12 AM UTC 24 |
18173719927 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2254559438 |
|
|
Sep 04 04:56:02 AM UTC 24 |
Sep 04 04:56:27 AM UTC 24 |
706872220 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_alert_test.410727487 |
|
|
Sep 04 04:56:28 AM UTC 24 |
Sep 04 04:56:30 AM UTC 24 |
23401304 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_bijection.1947396151 |
|
|
Sep 04 04:36:39 AM UTC 24 |
Sep 04 04:56:32 AM UTC 24 |
18120659331 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all.376204122 |
|
|
Sep 04 03:02:42 AM UTC 24 |
Sep 04 04:56:42 AM UTC 24 |
340686117374 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all.1001634339 |
|
|
Sep 04 04:44:13 AM UTC 24 |
Sep 04 04:57:03 AM UTC 24 |
291905944411 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_regwen.1703995976 |
|
|
Sep 04 04:55:35 AM UTC 24 |
Sep 04 04:57:39 AM UTC 24 |
2809355432 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.2274598738 |
|
|
Sep 04 04:52:13 AM UTC 24 |
Sep 04 04:57:44 AM UTC 24 |
13380927967 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all.4247673896 |
|
|
Sep 04 03:26:30 AM UTC 24 |
Sep 04 04:57:50 AM UTC 24 |
1350765057471 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.2409941304 |
|
|
Sep 04 04:41:43 AM UTC 24 |
Sep 04 04:58:11 AM UTC 24 |
20633694239 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.1597397961 |
|
|
Sep 04 04:51:46 AM UTC 24 |
Sep 04 04:58:15 AM UTC 24 |
4992881765 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.2462557073 |
|
|
Sep 04 04:44:32 AM UTC 24 |
Sep 04 04:58:17 AM UTC 24 |
27761428228 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.2294968729 |
|
|
Sep 04 04:46:29 AM UTC 24 |
Sep 04 04:58:19 AM UTC 24 |
55080963261 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.266768056 |
|
|
Sep 04 04:49:08 AM UTC 24 |
Sep 04 04:58:52 AM UTC 24 |
5754359111 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.999358326 |
|
|
Sep 04 04:56:00 AM UTC 24 |
Sep 04 04:58:54 AM UTC 24 |
1595096224 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_bijection.2769640276 |
|
|
Sep 04 04:22:01 AM UTC 24 |
Sep 04 04:58:56 AM UTC 24 |
58054092085 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.3231393300 |
|
|
Sep 04 04:46:54 AM UTC 24 |
Sep 04 04:58:56 AM UTC 24 |
94412476834 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.3731046704 |
|
|
Sep 04 04:47:38 AM UTC 24 |
Sep 04 04:58:59 AM UTC 24 |
37444907178 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.1200711118 |
|
|
Sep 04 04:49:29 AM UTC 24 |
Sep 04 04:59:12 AM UTC 24 |
171299981177 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.3082494056 |
|
|
Sep 04 04:43:19 AM UTC 24 |
Sep 04 05:01:00 AM UTC 24 |
17290712552 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.4287653031 |
|
|
Sep 04 04:54:26 AM UTC 24 |
Sep 04 05:01:18 AM UTC 24 |
11643122517 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.2174356439 |
|
|
Sep 04 04:55:53 AM UTC 24 |
Sep 04 05:01:19 AM UTC 24 |
20623866314 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.3770508815 |
|
|
Sep 04 04:54:52 AM UTC 24 |
Sep 04 05:02:04 AM UTC 24 |
88573284856 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_bijection.1269039188 |
|
|
Sep 04 04:29:27 AM UTC 24 |
Sep 04 05:02:38 AM UTC 24 |
225651819537 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_bijection.256318309 |
|
|
Sep 04 04:31:44 AM UTC 24 |
Sep 04 05:02:45 AM UTC 24 |
460398047497 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_regwen.2392722255 |
|
|
Sep 04 04:53:15 AM UTC 24 |
Sep 04 05:03:14 AM UTC 24 |
12944268307 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.1668803381 |
|
|
Sep 04 04:45:09 AM UTC 24 |
Sep 04 05:03:36 AM UTC 24 |
17779681248 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_executable.1459236989 |
|
|
Sep 04 04:45:12 AM UTC 24 |
Sep 04 05:03:53 AM UTC 24 |
58177046494 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_regwen.2232876543 |
|
|
Sep 04 04:50:14 AM UTC 24 |
Sep 04 05:04:43 AM UTC 24 |
23656529408 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.4009070081 |
|
|
Sep 04 04:51:32 AM UTC 24 |
Sep 04 05:04:50 AM UTC 24 |
47892224665 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_executable.1848687865 |
|
|
Sep 04 04:55:29 AM UTC 24 |
Sep 04 05:05:24 AM UTC 24 |
6354240969 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_executable.3994441307 |
|
|
Sep 04 04:47:40 AM UTC 24 |
Sep 04 05:05:35 AM UTC 24 |
94845381051 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all.2759867760 |
|
|
Sep 04 04:41:34 AM UTC 24 |
Sep 04 05:06:10 AM UTC 24 |
141440477629 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_executable.2081374935 |
|
|
Sep 04 04:53:05 AM UTC 24 |
Sep 04 05:06:38 AM UTC 24 |
39529308449 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.2621733678 |
|
|
Sep 04 04:54:07 AM UTC 24 |
Sep 04 05:07:03 AM UTC 24 |
15732067431 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.1681441227 |
|
|
Sep 04 03:08:44 AM UTC 24 |
Sep 04 05:09:32 AM UTC 24 |
299366004437 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.1088851405 |
|
|
Sep 04 04:55:23 AM UTC 24 |
Sep 04 05:09:42 AM UTC 24 |
14401254282 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_bijection.793317729 |
|
|
Sep 04 04:44:38 AM UTC 24 |
Sep 04 05:09:57 AM UTC 24 |
47143658738 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all.2975082129 |
|
|
Sep 04 04:33:40 AM UTC 24 |
Sep 04 05:10:19 AM UTC 24 |
65604780211 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all.1693359499 |
|
|
Sep 04 04:24:19 AM UTC 24 |
Sep 04 05:10:45 AM UTC 24 |
75081918601 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all.483914313 |
|
|
Sep 04 03:42:37 AM UTC 24 |
Sep 04 05:11:39 AM UTC 24 |
744155087268 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_bijection.2374075314 |
|
|
Sep 04 04:39:27 AM UTC 24 |
Sep 04 05:11:48 AM UTC 24 |
199029921734 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_bijection.165239903 |
|
|
Sep 04 04:54:22 AM UTC 24 |
Sep 04 05:12:08 AM UTC 24 |
30140705139 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all.1903949478 |
|
|
Sep 04 03:47:19 AM UTC 24 |
Sep 04 05:18:04 AM UTC 24 |
772659028028 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all.1391411677 |
|
|
Sep 04 03:53:32 AM UTC 24 |
Sep 04 05:18:27 AM UTC 24 |
243089531589 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all.1954386917 |
|
|
Sep 04 04:21:26 AM UTC 24 |
Sep 04 05:19:24 AM UTC 24 |
47165630539 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all.2279649066 |
|
|
Sep 04 04:38:54 AM UTC 24 |
Sep 04 05:21:32 AM UTC 24 |
194098872989 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all.1695469710 |
|
|
Sep 04 04:46:08 AM UTC 24 |
Sep 04 05:22:50 AM UTC 24 |
54212004619 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all.1457810200 |
|
|
Sep 04 03:37:35 AM UTC 24 |
Sep 04 05:23:18 AM UTC 24 |
2319341131119 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_bijection.3948096921 |
|
|
Sep 04 04:51:41 AM UTC 24 |
Sep 04 05:23:22 AM UTC 24 |
51546918691 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_bijection.3340742899 |
|
|
Sep 04 04:46:34 AM UTC 24 |
Sep 04 05:27:12 AM UTC 24 |
161473300947 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all.706163888 |
|
|
Sep 04 04:51:02 AM UTC 24 |
Sep 04 05:27:13 AM UTC 24 |
41702746328 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all.2308376964 |
|
|
Sep 04 03:49:00 AM UTC 24 |
Sep 04 05:28:13 AM UTC 24 |
194056674251 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_bijection.1080419846 |
|
|
Sep 04 04:49:16 AM UTC 24 |
Sep 04 05:31:26 AM UTC 24 |
145370491793 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all.740069630 |
|
|
Sep 04 03:24:25 AM UTC 24 |
Sep 04 05:34:26 AM UTC 24 |
927902548354 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all.1389573529 |
|
|
Sep 04 03:45:28 AM UTC 24 |
Sep 04 05:37:21 AM UTC 24 |
76573974582 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all.2847924036 |
|
|
Sep 04 04:29:01 AM UTC 24 |
Sep 04 05:48:23 AM UTC 24 |
151722519729 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all.1750782408 |
|
|
Sep 04 04:09:49 AM UTC 24 |
Sep 04 05:52:39 AM UTC 24 |
275641832934 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all.556552797 |
|
|
Sep 04 03:06:29 AM UTC 24 |
Sep 04 05:54:03 AM UTC 24 |
439188386962 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all.2766310705 |
|
|
Sep 04 04:36:23 AM UTC 24 |
Sep 04 06:01:54 AM UTC 24 |
469448625449 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all.1218483158 |
|
|
Sep 04 04:48:36 AM UTC 24 |
Sep 04 06:09:19 AM UTC 24 |
150976720922 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all.2061830034 |
|
|
Sep 04 04:53:59 AM UTC 24 |
Sep 04 06:17:55 AM UTC 24 |
548938656945 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all.708040057 |
|
|
Sep 04 04:31:23 AM UTC 24 |
Sep 04 06:39:41 AM UTC 24 |
388633696932 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all.180140695 |
|
|
Sep 04 04:18:13 AM UTC 24 |
Sep 04 07:16:50 AM UTC 24 |
1897064528752 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1544672846 |
|
|
Sep 04 04:56:33 AM UTC 24 |
Sep 04 04:56:38 AM UTC 24 |
290179413 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3403050972 |
|
|
Sep 04 04:56:39 AM UTC 24 |
Sep 04 04:56:43 AM UTC 24 |
331928137 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3689555990 |
|
|
Sep 04 04:56:43 AM UTC 24 |
Sep 04 04:56:45 AM UTC 24 |
29135529 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3222049349 |
|
|
Sep 04 04:56:43 AM UTC 24 |
Sep 04 04:56:45 AM UTC 24 |
22328303 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2429947502 |
|
|
Sep 04 04:56:47 AM UTC 24 |
Sep 04 04:56:48 AM UTC 24 |
15576849 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1747448192 |
|
|
Sep 04 04:56:47 AM UTC 24 |
Sep 04 04:56:49 AM UTC 24 |
100215430 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.310037561 |
|
|
Sep 04 04:56:50 AM UTC 24 |
Sep 04 04:56:52 AM UTC 24 |
17187507 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2886654748 |
|
|
Sep 04 04:56:51 AM UTC 24 |
Sep 04 04:56:59 AM UTC 24 |
350277888 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.77364743 |
|
|
Sep 04 04:56:31 AM UTC 24 |
Sep 04 04:57:04 AM UTC 24 |
8392598645 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2210492797 |
|
|
Sep 04 04:56:59 AM UTC 24 |
Sep 04 04:57:06 AM UTC 24 |
116593489 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1809271872 |
|
|
Sep 04 04:57:04 AM UTC 24 |
Sep 04 04:57:07 AM UTC 24 |
245152879 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.237848871 |
|
|
Sep 04 04:57:05 AM UTC 24 |
Sep 04 04:57:07 AM UTC 24 |
85126034 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3604519669 |
|
|
Sep 04 04:57:07 AM UTC 24 |
Sep 04 04:57:09 AM UTC 24 |
33782719 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3723267354 |
|
|
Sep 04 04:57:07 AM UTC 24 |
Sep 04 04:57:10 AM UTC 24 |
85934094 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.355457903 |
|
|
Sep 04 04:57:08 AM UTC 24 |
Sep 04 04:57:10 AM UTC 24 |
21333453 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1620637999 |
|
|
Sep 04 04:57:10 AM UTC 24 |
Sep 04 04:57:13 AM UTC 24 |
21474483 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2564438303 |
|
|
Sep 04 04:57:14 AM UTC 24 |
Sep 04 04:57:21 AM UTC 24 |
616052533 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1489599624 |
|
|
Sep 04 04:57:12 AM UTC 24 |
Sep 04 04:57:23 AM UTC 24 |
4930760448 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3033707757 |
|
|
Sep 04 04:57:22 AM UTC 24 |
Sep 04 04:57:25 AM UTC 24 |
436937125 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3010922484 |
|
|
Sep 04 04:57:24 AM UTC 24 |
Sep 04 04:57:26 AM UTC 24 |
247520892 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.31401120 |
|
|
Sep 04 04:57:26 AM UTC 24 |
Sep 04 04:57:28 AM UTC 24 |
15993549 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.800348358 |
|
|
Sep 04 04:57:27 AM UTC 24 |
Sep 04 04:57:32 AM UTC 24 |
1445025059 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1667609155 |
|
|
Sep 04 04:57:29 AM UTC 24 |
Sep 04 04:57:32 AM UTC 24 |
13178785 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3759468951 |
|
|
Sep 04 04:57:32 AM UTC 24 |
Sep 04 04:57:35 AM UTC 24 |
20565240 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.959903383 |
|
|
Sep 04 04:57:33 AM UTC 24 |
Sep 04 04:57:41 AM UTC 24 |
350444576 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3596636783 |
|
|
Sep 04 04:57:42 AM UTC 24 |
Sep 04 04:57:47 AM UTC 24 |
245029398 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3143657077 |
|
|
Sep 04 04:57:45 AM UTC 24 |
Sep 04 04:57:47 AM UTC 24 |
33494901 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.4117296581 |
|
|
Sep 04 04:57:41 AM UTC 24 |
Sep 04 04:57:49 AM UTC 24 |
52043259 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1794666123 |
|
|
Sep 04 04:57:48 AM UTC 24 |
Sep 04 04:57:50 AM UTC 24 |
44837160 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2561926837 |
|
|
Sep 04 04:57:49 AM UTC 24 |
Sep 04 04:57:52 AM UTC 24 |
51452419 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3988441711 |
|
|
Sep 04 04:57:48 AM UTC 24 |
Sep 04 04:57:52 AM UTC 24 |
45835169 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3298428952 |
|
|
Sep 04 04:57:51 AM UTC 24 |
Sep 04 04:57:53 AM UTC 24 |
16473427 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2062924309 |
|
|
Sep 04 04:57:51 AM UTC 24 |
Sep 04 04:57:59 AM UTC 24 |
1369126742 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4159322316 |
|
|
Sep 04 04:57:55 AM UTC 24 |
Sep 04 04:58:00 AM UTC 24 |
360146327 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1195981075 |
|
|
Sep 04 04:57:54 AM UTC 24 |
Sep 04 04:58:02 AM UTC 24 |
131676816 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1805349526 |
|
|
Sep 04 04:58:00 AM UTC 24 |
Sep 04 04:58:02 AM UTC 24 |
45130840 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2428072201 |
|
|
Sep 04 04:58:01 AM UTC 24 |
Sep 04 04:58:03 AM UTC 24 |
13748502 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2835301476 |
|
|
Sep 04 04:58:03 AM UTC 24 |
Sep 04 04:58:05 AM UTC 24 |
15002227 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2701300197 |
|
|
Sep 04 04:58:04 AM UTC 24 |
Sep 04 04:58:06 AM UTC 24 |
54866163 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.655284865 |
|
|
Sep 04 04:58:02 AM UTC 24 |
Sep 04 04:58:07 AM UTC 24 |
873205505 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2012695588 |
|
|
Sep 04 04:58:06 AM UTC 24 |
Sep 04 04:58:12 AM UTC 24 |
369201591 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1734384322 |
|
|
Sep 04 04:58:07 AM UTC 24 |
Sep 04 04:58:13 AM UTC 24 |
114285333 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1287443491 |
|
|
Sep 04 04:58:12 AM UTC 24 |
Sep 04 04:58:15 AM UTC 24 |
276586918 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2438710635 |
|
|
Sep 04 04:58:14 AM UTC 24 |
Sep 04 04:58:16 AM UTC 24 |
40169147 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1448921437 |
|
|
Sep 04 04:58:14 AM UTC 24 |
Sep 04 04:58:16 AM UTC 24 |
21453744 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.853043943 |
|
|
Sep 04 04:58:17 AM UTC 24 |
Sep 04 04:58:19 AM UTC 24 |
15658207 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2542328146 |
|
|
Sep 04 04:58:16 AM UTC 24 |
Sep 04 04:58:20 AM UTC 24 |
110164591 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1132357837 |
|
|
Sep 04 04:58:16 AM UTC 24 |
Sep 04 04:58:20 AM UTC 24 |
31409005 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.315025505 |
|
|
Sep 04 04:58:19 AM UTC 24 |
Sep 04 04:58:21 AM UTC 24 |
27762019 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2846596529 |
|
|
Sep 04 04:58:16 AM UTC 24 |
Sep 04 04:58:25 AM UTC 24 |
698327146 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2665357202 |
|
|
Sep 04 04:56:53 AM UTC 24 |
Sep 04 04:58:26 AM UTC 24 |
7340399577 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3033946288 |
|
|
Sep 04 04:58:21 AM UTC 24 |
Sep 04 04:58:27 AM UTC 24 |
36765747 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1696517471 |
|
|
Sep 04 04:58:21 AM UTC 24 |
Sep 04 04:58:27 AM UTC 24 |
373481578 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2691244805 |
|
|
Sep 04 04:58:23 AM UTC 24 |
Sep 04 04:58:27 AM UTC 24 |
799971622 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.503333318 |
|
|
Sep 04 04:58:26 AM UTC 24 |
Sep 04 04:58:28 AM UTC 24 |
15680409 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3220061611 |
|
|
Sep 04 04:58:27 AM UTC 24 |
Sep 04 04:58:29 AM UTC 24 |
46989757 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.89222370 |
|
|
Sep 04 04:57:36 AM UTC 24 |
Sep 04 04:58:31 AM UTC 24 |
30558516523 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2595609874 |
|
|
Sep 04 04:58:30 AM UTC 24 |
Sep 04 04:58:32 AM UTC 24 |
19929120 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.65426075 |
|
|
Sep 04 04:58:28 AM UTC 24 |
Sep 04 04:58:32 AM UTC 24 |
279526591 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3634089517 |
|
|
Sep 04 04:58:31 AM UTC 24 |
Sep 04 04:58:33 AM UTC 24 |
64730750 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1185386490 |
|
|
Sep 04 04:58:29 AM UTC 24 |
Sep 04 04:58:35 AM UTC 24 |
1007031979 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1089895348 |
|
|
Sep 04 04:58:27 AM UTC 24 |
Sep 04 04:58:37 AM UTC 24 |
2905425746 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3663065349 |
|
|
Sep 04 04:58:35 AM UTC 24 |
Sep 04 04:58:37 AM UTC 24 |
38239063 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3810778846 |
|
|
Sep 04 04:58:32 AM UTC 24 |
Sep 04 04:58:38 AM UTC 24 |
742463382 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2298764480 |
|
|
Sep 04 04:58:33 AM UTC 24 |
Sep 04 04:58:39 AM UTC 24 |
421934628 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.649105549 |
|
|
Sep 04 04:58:34 AM UTC 24 |
Sep 04 04:58:39 AM UTC 24 |
344746897 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1000209376 |
|
|
Sep 04 04:58:37 AM UTC 24 |
Sep 04 04:58:40 AM UTC 24 |
85831716 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.186227633 |
|
|
Sep 04 04:57:12 AM UTC 24 |
Sep 04 04:58:41 AM UTC 24 |
28214188672 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.561803925 |
|
|
Sep 04 04:58:41 AM UTC 24 |
Sep 04 04:58:43 AM UTC 24 |
57887674 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.349208027 |
|
|
Sep 04 04:58:40 AM UTC 24 |
Sep 04 04:58:44 AM UTC 24 |
165882758 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2951982496 |
|
|
Sep 04 04:58:42 AM UTC 24 |
Sep 04 04:58:44 AM UTC 24 |
26159490 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.301746927 |
|
|
Sep 04 04:58:40 AM UTC 24 |
Sep 04 04:58:44 AM UTC 24 |
488684202 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.549491837 |
|
|
Sep 04 04:58:38 AM UTC 24 |
Sep 04 04:58:46 AM UTC 24 |
1595590713 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2531194070 |
|
|
Sep 04 04:58:47 AM UTC 24 |
Sep 04 04:58:49 AM UTC 24 |
12736555 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1684550396 |
|
|
Sep 04 04:58:45 AM UTC 24 |
Sep 04 04:58:50 AM UTC 24 |
121062536 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3351098376 |
|
|
Sep 04 04:58:44 AM UTC 24 |
Sep 04 04:58:50 AM UTC 24 |
1395190270 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.424390394 |
|
|
Sep 04 04:58:45 AM UTC 24 |
Sep 04 04:58:52 AM UTC 24 |
1125367935 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1676161915 |
|
|
Sep 04 04:58:50 AM UTC 24 |
Sep 04 04:58:52 AM UTC 24 |
25979156 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3040032243 |
|
|
Sep 04 04:58:53 AM UTC 24 |
Sep 04 04:58:56 AM UTC 24 |
38326085 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1414451396 |
|
|
Sep 04 04:58:51 AM UTC 24 |
Sep 04 04:58:57 AM UTC 24 |
1718439774 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1341311654 |
|
|
Sep 04 04:58:54 AM UTC 24 |
Sep 04 04:58:57 AM UTC 24 |
48424881 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1802079895 |
|
|
Sep 04 04:58:53 AM UTC 24 |
Sep 04 04:58:58 AM UTC 24 |
476718657 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3209250328 |
|
|
Sep 04 04:58:53 AM UTC 24 |
Sep 04 04:58:59 AM UTC 24 |
83003052 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4176661859 |
|
|
Sep 04 04:58:58 AM UTC 24 |
Sep 04 04:59:00 AM UTC 24 |
15595895 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2714370863 |
|
|
Sep 04 04:58:59 AM UTC 24 |
Sep 04 04:59:01 AM UTC 24 |
36480811 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1391866207 |
|
|
Sep 04 04:58:58 AM UTC 24 |
Sep 04 04:59:02 AM UTC 24 |
193013340 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3034125987 |
|
|
Sep 04 04:58:57 AM UTC 24 |
Sep 04 04:59:03 AM UTC 24 |
78780229 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.825863429 |
|
|
Sep 04 04:57:52 AM UTC 24 |
Sep 04 04:59:04 AM UTC 24 |
29387791737 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.325985846 |
|
|
Sep 04 04:59:03 AM UTC 24 |
Sep 04 04:59:05 AM UTC 24 |
26982588 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2070291506 |
|
|
Sep 04 04:58:21 AM UTC 24 |
Sep 04 04:59:05 AM UTC 24 |
3786019165 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1446633864 |
|
|
Sep 04 04:58:57 AM UTC 24 |
Sep 04 04:59:06 AM UTC 24 |
424774528 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1971227222 |
|
|
Sep 04 04:59:04 AM UTC 24 |
Sep 04 04:59:06 AM UTC 24 |
48795910 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2583388069 |
|
|
Sep 04 04:59:00 AM UTC 24 |
Sep 04 04:59:06 AM UTC 24 |
147742646 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3396308768 |
|
|
Sep 04 04:58:33 AM UTC 24 |
Sep 04 04:59:07 AM UTC 24 |
14818185300 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1405772128 |
|
|
Sep 04 04:59:03 AM UTC 24 |
Sep 04 04:59:07 AM UTC 24 |
201552626 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3366105717 |
|
|
Sep 04 04:59:00 AM UTC 24 |
Sep 04 04:59:07 AM UTC 24 |
370178985 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.920739150 |
|
|
Sep 04 04:59:06 AM UTC 24 |
Sep 04 04:59:09 AM UTC 24 |
12956690 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2625626281 |
|
|
Sep 04 04:59:08 AM UTC 24 |
Sep 04 04:59:10 AM UTC 24 |
55268919 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3168215820 |
|
|
Sep 04 04:59:06 AM UTC 24 |
Sep 04 04:59:11 AM UTC 24 |
343272333 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1212427361 |
|
|
Sep 04 04:59:06 AM UTC 24 |
Sep 04 04:59:11 AM UTC 24 |
1804527616 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.488412185 |
|
|
Sep 04 04:59:05 AM UTC 24 |
Sep 04 04:59:11 AM UTC 24 |
351502993 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2814487248 |
|
|
Sep 04 04:59:09 AM UTC 24 |
Sep 04 04:59:13 AM UTC 24 |
425969855 ps |