| T306 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.4144244611 |
|
|
Sep 11 06:41:00 AM UTC 24 |
Sep 11 06:43:40 AM UTC 24 |
16444118045 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.3468587847 |
|
|
Sep 11 06:40:04 AM UTC 24 |
Sep 11 06:44:04 AM UTC 24 |
3895847929 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.1049109842 |
|
|
Sep 11 06:43:05 AM UTC 24 |
Sep 11 06:44:22 AM UTC 24 |
5368022167 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.4044741787 |
|
|
Sep 11 06:44:23 AM UTC 24 |
Sep 11 06:44:35 AM UTC 24 |
1032882656 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.3594517319 |
|
|
Sep 11 06:29:09 AM UTC 24 |
Sep 11 06:44:38 AM UTC 24 |
21243047305 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access.2161099660 |
|
|
Sep 11 06:43:40 AM UTC 24 |
Sep 11 06:44:47 AM UTC 24 |
955975575 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.1725124569 |
|
|
Sep 11 06:44:36 AM UTC 24 |
Sep 11 06:44:49 AM UTC 24 |
705127055 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.3832664927 |
|
|
Sep 11 06:44:39 AM UTC 24 |
Sep 11 06:45:04 AM UTC 24 |
2127357257 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_executable.3732118260 |
|
|
Sep 11 06:33:46 AM UTC 24 |
Sep 11 06:45:34 AM UTC 24 |
35088564755 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.53836200 |
|
|
Sep 11 06:29:23 AM UTC 24 |
Sep 11 06:45:36 AM UTC 24 |
41367655383 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.3050318197 |
|
|
Sep 11 06:45:35 AM UTC 24 |
Sep 11 06:45:42 AM UTC 24 |
1429364294 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.2691295873 |
|
|
Sep 11 06:40:25 AM UTC 24 |
Sep 11 06:45:49 AM UTC 24 |
10996837384 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.2060990093 |
|
|
Sep 11 06:36:54 AM UTC 24 |
Sep 11 06:45:54 AM UTC 24 |
66861264025 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_executable.1562889248 |
|
|
Sep 11 06:40:49 AM UTC 24 |
Sep 11 06:46:02 AM UTC 24 |
30542993456 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_alert_test.2344101779 |
|
|
Sep 11 06:46:02 AM UTC 24 |
Sep 11 06:46:04 AM UTC 24 |
11376070 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.557867292 |
|
|
Sep 11 06:45:50 AM UTC 24 |
Sep 11 06:46:10 AM UTC 24 |
462386118 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.2735896793 |
|
|
Sep 11 06:25:14 AM UTC 24 |
Sep 11 06:46:18 AM UTC 24 |
64607939981 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_smoke.2645615934 |
|
|
Sep 11 06:46:05 AM UTC 24 |
Sep 11 06:46:27 AM UTC 24 |
1441320664 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.1331612441 |
|
|
Sep 11 06:43:04 AM UTC 24 |
Sep 11 06:46:59 AM UTC 24 |
10573516374 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.3104113116 |
|
|
Sep 11 06:27:45 AM UTC 24 |
Sep 11 06:47:16 AM UTC 24 |
68424227509 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.1277263789 |
|
|
Sep 11 06:21:29 AM UTC 24 |
Sep 11 06:47:21 AM UTC 24 |
77116691478 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_bijection.3033223795 |
|
|
Sep 11 06:20:32 AM UTC 24 |
Sep 11 06:47:27 AM UTC 24 |
142864909207 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.1655551998 |
|
|
Sep 11 06:47:28 AM UTC 24 |
Sep 11 06:47:39 AM UTC 24 |
2848656419 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.767994520 |
|
|
Sep 11 06:30:25 AM UTC 24 |
Sep 11 06:47:41 AM UTC 24 |
13299636403 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.76322858 |
|
|
Sep 11 06:32:57 AM UTC 24 |
Sep 11 06:47:44 AM UTC 24 |
31037608186 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.588798710 |
|
|
Sep 11 06:31:48 AM UTC 24 |
Sep 11 06:47:46 AM UTC 24 |
48979011140 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.2534974965 |
|
|
Sep 11 06:35:29 AM UTC 24 |
Sep 11 06:47:49 AM UTC 24 |
55995735220 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_regwen.2914010852 |
|
|
Sep 11 06:33:50 AM UTC 24 |
Sep 11 06:47:52 AM UTC 24 |
8218038777 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.1913589601 |
|
|
Sep 11 06:47:47 AM UTC 24 |
Sep 11 06:47:53 AM UTC 24 |
354170946 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.3774749993 |
|
|
Sep 11 06:41:45 AM UTC 24 |
Sep 11 06:48:01 AM UTC 24 |
12326356041 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access.837090601 |
|
|
Sep 11 06:47:01 AM UTC 24 |
Sep 11 06:48:02 AM UTC 24 |
1230735499 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_alert_test.497446791 |
|
|
Sep 11 06:48:03 AM UTC 24 |
Sep 11 06:48:05 AM UTC 24 |
22927956 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_bijection.688227966 |
|
|
Sep 11 06:36:20 AM UTC 24 |
Sep 11 06:48:13 AM UTC 24 |
43374044253 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.2136191682 |
|
|
Sep 11 06:47:22 AM UTC 24 |
Sep 11 06:48:15 AM UTC 24 |
2966569497 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.2774786201 |
|
|
Sep 11 06:41:38 AM UTC 24 |
Sep 11 06:48:23 AM UTC 24 |
6561102529 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_smoke.4027436613 |
|
|
Sep 11 06:48:06 AM UTC 24 |
Sep 11 06:48:27 AM UTC 24 |
7040525759 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.2116041698 |
|
|
Sep 11 06:38:47 AM UTC 24 |
Sep 11 06:48:36 AM UTC 24 |
10902291565 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3081804582 |
|
|
Sep 11 06:47:54 AM UTC 24 |
Sep 11 06:48:38 AM UTC 24 |
1553420029 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.102785858 |
|
|
Sep 11 06:45:43 AM UTC 24 |
Sep 11 06:48:40 AM UTC 24 |
9408162581 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_regwen.3952414118 |
|
|
Sep 11 06:35:39 AM UTC 24 |
Sep 11 06:48:45 AM UTC 24 |
12816731771 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.2838479448 |
|
|
Sep 11 06:45:37 AM UTC 24 |
Sep 11 06:48:46 AM UTC 24 |
8991796899 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.2882067445 |
|
|
Sep 11 06:48:39 AM UTC 24 |
Sep 11 06:49:06 AM UTC 24 |
749584967 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.178242048 |
|
|
Sep 11 06:48:45 AM UTC 24 |
Sep 11 06:49:23 AM UTC 24 |
5340668573 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.1157350473 |
|
|
Sep 11 06:43:39 AM UTC 24 |
Sep 11 06:49:25 AM UTC 24 |
4502703055 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_regwen.2614764819 |
|
|
Sep 11 06:40:50 AM UTC 24 |
Sep 11 06:49:29 AM UTC 24 |
1633254152 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.4227598710 |
|
|
Sep 11 06:49:26 AM UTC 24 |
Sep 11 06:49:33 AM UTC 24 |
429423924 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.731861145 |
|
|
Sep 11 06:47:33 AM UTC 24 |
Sep 11 06:49:55 AM UTC 24 |
45264448937 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_bijection.1579283342 |
|
|
Sep 11 06:20:07 AM UTC 24 |
Sep 11 06:49:58 AM UTC 24 |
179589906317 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access.3289904383 |
|
|
Sep 11 06:48:28 AM UTC 24 |
Sep 11 06:50:05 AM UTC 24 |
829598869 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3480728332 |
|
|
Sep 11 06:49:56 AM UTC 24 |
Sep 11 06:50:07 AM UTC 24 |
986808178 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_alert_test.3763909416 |
|
|
Sep 11 06:50:06 AM UTC 24 |
Sep 11 06:50:08 AM UTC 24 |
18475465 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.4265063344 |
|
|
Sep 11 06:44:05 AM UTC 24 |
Sep 11 06:50:22 AM UTC 24 |
25602027652 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.1539363150 |
|
|
Sep 11 06:48:41 AM UTC 24 |
Sep 11 06:50:27 AM UTC 24 |
1598315962 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.2626140629 |
|
|
Sep 11 06:47:53 AM UTC 24 |
Sep 11 06:50:42 AM UTC 24 |
62647636576 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_executable.2484717249 |
|
|
Sep 11 06:31:49 AM UTC 24 |
Sep 11 06:50:42 AM UTC 24 |
26246115113 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_smoke.941662973 |
|
|
Sep 11 06:50:08 AM UTC 24 |
Sep 11 06:50:52 AM UTC 24 |
3152012393 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.567803014 |
|
|
Sep 11 06:40:40 AM UTC 24 |
Sep 11 06:51:07 AM UTC 24 |
129120070430 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access.2820647386 |
|
|
Sep 11 06:50:43 AM UTC 24 |
Sep 11 06:51:12 AM UTC 24 |
2760101970 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_executable.3754258998 |
|
|
Sep 11 06:42:29 AM UTC 24 |
Sep 11 06:51:21 AM UTC 24 |
10116428298 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.702140103 |
|
|
Sep 11 06:49:34 AM UTC 24 |
Sep 11 06:51:21 AM UTC 24 |
3613314397 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.3567170506 |
|
|
Sep 11 06:50:53 AM UTC 24 |
Sep 11 06:51:28 AM UTC 24 |
3002230175 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.3139081635 |
|
|
Sep 11 06:47:17 AM UTC 24 |
Sep 11 06:51:42 AM UTC 24 |
174764604931 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_regwen.2821889051 |
|
|
Sep 11 06:38:49 AM UTC 24 |
Sep 11 06:51:46 AM UTC 24 |
37484535486 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.3042545432 |
|
|
Sep 11 06:51:43 AM UTC 24 |
Sep 11 06:51:49 AM UTC 24 |
400859138 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_executable.195579519 |
|
|
Sep 11 06:49:07 AM UTC 24 |
Sep 11 06:51:54 AM UTC 24 |
8943939776 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.13493431 |
|
|
Sep 11 06:51:55 AM UTC 24 |
Sep 11 06:52:12 AM UTC 24 |
480376174 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.3947678672 |
|
|
Sep 11 06:33:45 AM UTC 24 |
Sep 11 06:52:19 AM UTC 24 |
60068498126 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_regwen.33531320 |
|
|
Sep 11 06:42:52 AM UTC 24 |
Sep 11 06:52:21 AM UTC 24 |
5253977618 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_alert_test.3147899163 |
|
|
Sep 11 06:52:19 AM UTC 24 |
Sep 11 06:52:21 AM UTC 24 |
15203360 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.917543187 |
|
|
Sep 11 06:48:24 AM UTC 24 |
Sep 11 06:52:31 AM UTC 24 |
4147543974 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.3669482403 |
|
|
Sep 11 06:51:13 AM UTC 24 |
Sep 11 06:52:35 AM UTC 24 |
12099172051 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_smoke.2992666731 |
|
|
Sep 11 06:52:22 AM UTC 24 |
Sep 11 06:52:42 AM UTC 24 |
2654711790 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.1656147824 |
|
|
Sep 11 06:28:19 AM UTC 24 |
Sep 11 06:52:45 AM UTC 24 |
69649323932 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.2966374705 |
|
|
Sep 11 06:46:29 AM UTC 24 |
Sep 11 06:52:46 AM UTC 24 |
33424744015 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_executable.2293123502 |
|
|
Sep 11 06:38:47 AM UTC 24 |
Sep 11 06:52:48 AM UTC 24 |
8555036379 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.45453922 |
|
|
Sep 11 06:51:07 AM UTC 24 |
Sep 11 06:52:54 AM UTC 24 |
817100005 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access.214902573 |
|
|
Sep 11 06:52:44 AM UTC 24 |
Sep 11 06:53:03 AM UTC 24 |
1294183076 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.1206548067 |
|
|
Sep 11 06:36:14 AM UTC 24 |
Sep 11 06:53:03 AM UTC 24 |
32927413711 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.3406873706 |
|
|
Sep 11 06:52:55 AM UTC 24 |
Sep 11 06:53:08 AM UTC 24 |
6000353852 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.2813728412 |
|
|
Sep 11 06:48:37 AM UTC 24 |
Sep 11 06:53:10 AM UTC 24 |
9107577645 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.3606365605 |
|
|
Sep 11 06:52:47 AM UTC 24 |
Sep 11 06:53:13 AM UTC 24 |
1349197398 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.3246597910 |
|
|
Sep 11 06:53:10 AM UTC 24 |
Sep 11 06:53:18 AM UTC 24 |
1611959412 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.721579056 |
|
|
Sep 11 06:27:46 AM UTC 24 |
Sep 11 06:53:24 AM UTC 24 |
26667615214 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.2957097517 |
|
|
Sep 11 06:41:24 AM UTC 24 |
Sep 11 06:53:30 AM UTC 24 |
69505293517 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1321440843 |
|
|
Sep 11 06:53:25 AM UTC 24 |
Sep 11 06:53:34 AM UTC 24 |
616347986 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_bijection.231899327 |
|
|
Sep 11 06:20:22 AM UTC 24 |
Sep 11 06:53:36 AM UTC 24 |
413901321526 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_alert_test.1081973486 |
|
|
Sep 11 06:53:35 AM UTC 24 |
Sep 11 06:53:37 AM UTC 24 |
30035939 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_regwen.3309578817 |
|
|
Sep 11 06:45:05 AM UTC 24 |
Sep 11 06:53:42 AM UTC 24 |
16451460046 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_bijection.614072337 |
|
|
Sep 11 06:15:15 AM UTC 24 |
Sep 11 06:53:47 AM UTC 24 |
61528914358 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.1856808603 |
|
|
Sep 11 06:51:50 AM UTC 24 |
Sep 11 06:53:49 AM UTC 24 |
2685570100 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.190310314 |
|
|
Sep 11 06:52:48 AM UTC 24 |
Sep 11 06:53:59 AM UTC 24 |
3185993778 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.1949075734 |
|
|
Sep 11 06:24:48 AM UTC 24 |
Sep 11 06:54:06 AM UTC 24 |
20671848077 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access.2941551875 |
|
|
Sep 11 06:53:50 AM UTC 24 |
Sep 11 06:54:07 AM UTC 24 |
963560649 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.763884382 |
|
|
Sep 11 06:50:29 AM UTC 24 |
Sep 11 06:54:11 AM UTC 24 |
2953089373 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.889192919 |
|
|
Sep 11 06:54:08 AM UTC 24 |
Sep 11 06:54:19 AM UTC 24 |
2399966146 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_regwen.2083413136 |
|
|
Sep 11 06:47:44 AM UTC 24 |
Sep 11 06:54:22 AM UTC 24 |
3742729731 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.59550991 |
|
|
Sep 11 06:54:07 AM UTC 24 |
Sep 11 06:54:30 AM UTC 24 |
703099445 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.3630252025 |
|
|
Sep 11 06:54:12 AM UTC 24 |
Sep 11 06:54:44 AM UTC 24 |
2968446559 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.3649551818 |
|
|
Sep 11 06:54:45 AM UTC 24 |
Sep 11 06:54:51 AM UTC 24 |
1407618268 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.3907078580 |
|
|
Sep 11 06:47:50 AM UTC 24 |
Sep 11 06:54:51 AM UTC 24 |
22972750790 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.1438975729 |
|
|
Sep 11 06:53:20 AM UTC 24 |
Sep 11 06:54:59 AM UTC 24 |
5477047310 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.3265943657 |
|
|
Sep 11 06:53:38 AM UTC 24 |
Sep 11 06:55:01 AM UTC 24 |
1807352063 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.4226072748 |
|
|
Sep 11 06:55:00 AM UTC 24 |
Sep 11 06:55:12 AM UTC 24 |
1206407616 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_alert_test.1356467703 |
|
|
Sep 11 06:55:13 AM UTC 24 |
Sep 11 06:55:15 AM UTC 24 |
44450684 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_smoke.2324066101 |
|
|
Sep 11 06:53:36 AM UTC 24 |
Sep 11 06:55:17 AM UTC 24 |
1430618228 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.3507239131 |
|
|
Sep 11 06:42:28 AM UTC 24 |
Sep 11 06:55:53 AM UTC 24 |
12530410123 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_smoke.1014047136 |
|
|
Sep 11 06:55:16 AM UTC 24 |
Sep 11 06:56:03 AM UTC 24 |
14571366045 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.1054604473 |
|
|
Sep 11 06:51:22 AM UTC 24 |
Sep 11 06:56:08 AM UTC 24 |
30784593498 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.3213703460 |
|
|
Sep 11 06:53:04 AM UTC 24 |
Sep 11 06:56:30 AM UTC 24 |
3162977966 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.2153718815 |
|
|
Sep 11 06:50:43 AM UTC 24 |
Sep 11 06:56:39 AM UTC 24 |
15809769074 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_regwen.2754115066 |
|
|
Sep 11 06:53:08 AM UTC 24 |
Sep 11 06:56:40 AM UTC 24 |
3158037681 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.3633642678 |
|
|
Sep 11 06:51:47 AM UTC 24 |
Sep 11 06:56:50 AM UTC 24 |
3945604282 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.1205745691 |
|
|
Sep 11 06:52:22 AM UTC 24 |
Sep 11 06:56:52 AM UTC 24 |
51619132093 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_executable.3033842581 |
|
|
Sep 11 06:51:22 AM UTC 24 |
Sep 11 06:56:56 AM UTC 24 |
20038844812 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.2580341006 |
|
|
Sep 11 06:49:31 AM UTC 24 |
Sep 11 06:56:57 AM UTC 24 |
18720010582 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.3891339084 |
|
|
Sep 11 06:39:44 AM UTC 24 |
Sep 11 06:57:04 AM UTC 24 |
7400821916 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.2833127375 |
|
|
Sep 11 06:57:05 AM UTC 24 |
Sep 11 06:57:11 AM UTC 24 |
359864269 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.1585200053 |
|
|
Sep 11 06:56:40 AM UTC 24 |
Sep 11 06:57:18 AM UTC 24 |
799524869 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.579913462 |
|
|
Sep 11 06:56:40 AM UTC 24 |
Sep 11 06:57:35 AM UTC 24 |
1478519822 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access.971664025 |
|
|
Sep 11 06:56:09 AM UTC 24 |
Sep 11 06:57:41 AM UTC 24 |
971966301 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.604794040 |
|
|
Sep 11 06:57:37 AM UTC 24 |
Sep 11 06:58:02 AM UTC 24 |
438247704 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.1348375333 |
|
|
Sep 11 06:54:52 AM UTC 24 |
Sep 11 06:58:04 AM UTC 24 |
23456992180 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_alert_test.416660045 |
|
|
Sep 11 06:58:02 AM UTC 24 |
Sep 11 06:58:04 AM UTC 24 |
28510461 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.3609399437 |
|
|
Sep 11 06:56:53 AM UTC 24 |
Sep 11 06:58:15 AM UTC 24 |
5125859579 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.814204720 |
|
|
Sep 11 06:44:47 AM UTC 24 |
Sep 11 06:58:16 AM UTC 24 |
15622225342 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_executable.74608674 |
|
|
Sep 11 06:44:50 AM UTC 24 |
Sep 11 06:58:17 AM UTC 24 |
71939662798 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.2253944280 |
|
|
Sep 11 06:55:18 AM UTC 24 |
Sep 11 06:58:22 AM UTC 24 |
6378359222 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.569158796 |
|
|
Sep 11 06:52:37 AM UTC 24 |
Sep 11 06:58:23 AM UTC 24 |
4498440320 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_smoke.3168335010 |
|
|
Sep 11 06:58:04 AM UTC 24 |
Sep 11 06:58:23 AM UTC 24 |
930795024 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_regwen.718630699 |
|
|
Sep 11 06:51:28 AM UTC 24 |
Sep 11 06:58:50 AM UTC 24 |
33196992621 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.816002045 |
|
|
Sep 11 06:58:24 AM UTC 24 |
Sep 11 06:58:42 AM UTC 24 |
1469743645 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access.4115293993 |
|
|
Sep 11 06:58:18 AM UTC 24 |
Sep 11 06:58:44 AM UTC 24 |
3400585483 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.930715459 |
|
|
Sep 11 06:53:47 AM UTC 24 |
Sep 11 06:58:48 AM UTC 24 |
3326379948 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.1460992126 |
|
|
Sep 11 06:43:31 AM UTC 24 |
Sep 11 06:58:48 AM UTC 24 |
37670999380 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.2731351793 |
|
|
Sep 11 06:58:50 AM UTC 24 |
Sep 11 06:58:57 AM UTC 24 |
2242136009 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.1818425914 |
|
|
Sep 11 06:56:50 AM UTC 24 |
Sep 11 06:59:00 AM UTC 24 |
18846053077 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.132600415 |
|
|
Sep 11 06:50:09 AM UTC 24 |
Sep 11 06:59:07 AM UTC 24 |
15328237478 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.2919698047 |
|
|
Sep 11 06:58:24 AM UTC 24 |
Sep 11 06:59:11 AM UTC 24 |
2822498827 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.259474574 |
|
|
Sep 11 06:52:46 AM UTC 24 |
Sep 11 06:59:23 AM UTC 24 |
11440647470 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_alert_test.4236388654 |
|
|
Sep 11 06:59:24 AM UTC 24 |
Sep 11 06:59:26 AM UTC 24 |
34930152 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_smoke.2982557521 |
|
|
Sep 11 06:59:27 AM UTC 24 |
Sep 11 06:59:56 AM UTC 24 |
2256525629 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.2410329473 |
|
|
Sep 11 06:54:52 AM UTC 24 |
Sep 11 06:59:58 AM UTC 24 |
35828086696 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_regwen.2084791935 |
|
|
Sep 11 06:49:25 AM UTC 24 |
Sep 11 07:00:03 AM UTC 24 |
12957422406 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3316251613 |
|
|
Sep 11 06:59:08 AM UTC 24 |
Sep 11 07:00:14 AM UTC 24 |
1606964163 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.3962646235 |
|
|
Sep 11 06:53:14 AM UTC 24 |
Sep 11 07:00:22 AM UTC 24 |
15537107275 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.1388326290 |
|
|
Sep 11 06:58:43 AM UTC 24 |
Sep 11 07:00:29 AM UTC 24 |
45830547133 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access.213100812 |
|
|
Sep 11 07:00:15 AM UTC 24 |
Sep 11 07:00:45 AM UTC 24 |
5946077347 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.1080008510 |
|
|
Sep 11 07:00:30 AM UTC 24 |
Sep 11 07:00:50 AM UTC 24 |
727614778 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.3895201505 |
|
|
Sep 11 06:54:00 AM UTC 24 |
Sep 11 07:00:51 AM UTC 24 |
18563481521 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.837704194 |
|
|
Sep 11 07:00:46 AM UTC 24 |
Sep 11 07:01:08 AM UTC 24 |
737989321 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.4098273551 |
|
|
Sep 11 06:57:19 AM UTC 24 |
Sep 11 07:01:17 AM UTC 24 |
115873463411 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.3647767613 |
|
|
Sep 11 06:48:46 AM UTC 24 |
Sep 11 07:01:26 AM UTC 24 |
26555443853 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.2731335906 |
|
|
Sep 11 07:01:27 AM UTC 24 |
Sep 11 07:01:32 AM UTC 24 |
411473806 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.3314336004 |
|
|
Sep 11 06:59:01 AM UTC 24 |
Sep 11 07:01:41 AM UTC 24 |
6372695232 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.768077089 |
|
|
Sep 11 06:48:14 AM UTC 24 |
Sep 11 07:01:42 AM UTC 24 |
15583793800 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_bijection.1188476660 |
|
|
Sep 11 06:46:18 AM UTC 24 |
Sep 11 07:01:59 AM UTC 24 |
48634950600 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_bijection.266268900 |
|
|
Sep 11 06:48:15 AM UTC 24 |
Sep 11 07:01:59 AM UTC 24 |
151705692113 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.2931589081 |
|
|
Sep 11 07:00:51 AM UTC 24 |
Sep 11 07:02:01 AM UTC 24 |
11469862198 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_alert_test.1271570703 |
|
|
Sep 11 07:02:00 AM UTC 24 |
Sep 11 07:02:02 AM UTC 24 |
85558716 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.217132819 |
|
|
Sep 11 06:54:20 AM UTC 24 |
Sep 11 07:02:05 AM UTC 24 |
14597446032 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.3155412199 |
|
|
Sep 11 06:58:16 AM UTC 24 |
Sep 11 07:02:13 AM UTC 24 |
14060493969 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.614594129 |
|
|
Sep 11 06:56:04 AM UTC 24 |
Sep 11 07:02:16 AM UTC 24 |
76482563287 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all.3945350539 |
|
|
Sep 11 06:20:20 AM UTC 24 |
Sep 11 07:02:29 AM UTC 24 |
119674991401 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_smoke.358561403 |
|
|
Sep 11 07:02:02 AM UTC 24 |
Sep 11 07:02:40 AM UTC 24 |
16795611362 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.2971772731 |
|
|
Sep 11 06:58:59 AM UTC 24 |
Sep 11 07:02:50 AM UTC 24 |
38391213474 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_executable.2175599561 |
|
|
Sep 11 06:54:22 AM UTC 24 |
Sep 11 07:02:50 AM UTC 24 |
8858631309 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.3850593257 |
|
|
Sep 11 07:02:51 AM UTC 24 |
Sep 11 07:03:16 AM UTC 24 |
747396346 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_regwen.1838813349 |
|
|
Sep 11 06:54:31 AM UTC 24 |
Sep 11 07:03:20 AM UTC 24 |
8158717075 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.1824337467 |
|
|
Sep 11 06:58:23 AM UTC 24 |
Sep 11 07:03:21 AM UTC 24 |
22733394397 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.3603554206 |
|
|
Sep 11 07:01:42 AM UTC 24 |
Sep 11 07:03:26 AM UTC 24 |
2365678477 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.2958597302 |
|
|
Sep 11 07:03:26 AM UTC 24 |
Sep 11 07:03:32 AM UTC 24 |
1404998514 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.404453669 |
|
|
Sep 11 07:02:03 AM UTC 24 |
Sep 11 07:03:37 AM UTC 24 |
4164643331 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.14205351 |
|
|
Sep 11 07:01:43 AM UTC 24 |
Sep 11 07:03:51 AM UTC 24 |
1259382822 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.48823195 |
|
|
Sep 11 07:02:41 AM UTC 24 |
Sep 11 07:03:52 AM UTC 24 |
1488094494 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access.1897710899 |
|
|
Sep 11 07:02:17 AM UTC 24 |
Sep 11 07:03:58 AM UTC 24 |
3708936543 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_alert_test.276635968 |
|
|
Sep 11 07:03:59 AM UTC 24 |
Sep 11 07:04:01 AM UTC 24 |
18808398 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1596813895 |
|
|
Sep 11 07:03:52 AM UTC 24 |
Sep 11 07:04:05 AM UTC 24 |
989438981 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_smoke.2985459172 |
|
|
Sep 11 07:04:02 AM UTC 24 |
Sep 11 07:04:13 AM UTC 24 |
1613282127 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.2821902920 |
|
|
Sep 11 06:57:12 AM UTC 24 |
Sep 11 07:04:14 AM UTC 24 |
13992718558 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.238998350 |
|
|
Sep 11 06:47:40 AM UTC 24 |
Sep 11 07:04:32 AM UTC 24 |
46723884218 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.3610737220 |
|
|
Sep 11 06:56:31 AM UTC 24 |
Sep 11 07:04:34 AM UTC 24 |
8260990085 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.2765522680 |
|
|
Sep 11 07:01:33 AM UTC 24 |
Sep 11 07:04:42 AM UTC 24 |
12647704770 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access.3931927831 |
|
|
Sep 11 07:04:33 AM UTC 24 |
Sep 11 07:04:47 AM UTC 24 |
2892643966 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.1185692412 |
|
|
Sep 11 07:02:51 AM UTC 24 |
Sep 11 07:04:53 AM UTC 24 |
59226668734 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.48811708 |
|
|
Sep 11 07:03:38 AM UTC 24 |
Sep 11 07:04:58 AM UTC 24 |
9680499702 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.3364089080 |
|
|
Sep 11 07:04:48 AM UTC 24 |
Sep 11 07:04:59 AM UTC 24 |
698447084 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.2938437182 |
|
|
Sep 11 07:00:05 AM UTC 24 |
Sep 11 07:05:06 AM UTC 24 |
4791891580 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.405816758 |
|
|
Sep 11 07:02:14 AM UTC 24 |
Sep 11 07:05:10 AM UTC 24 |
4443670605 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.3244634425 |
|
|
Sep 11 07:05:11 AM UTC 24 |
Sep 11 07:05:19 AM UTC 24 |
1359001355 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.589555583 |
|
|
Sep 11 07:04:54 AM UTC 24 |
Sep 11 07:05:19 AM UTC 24 |
11598111945 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.885837711 |
|
|
Sep 11 07:04:43 AM UTC 24 |
Sep 11 07:05:24 AM UTC 24 |
744329831 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.2206994671 |
|
|
Sep 11 06:46:10 AM UTC 24 |
Sep 11 07:05:29 AM UTC 24 |
234642467860 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.880846542 |
|
|
Sep 11 07:05:25 AM UTC 24 |
Sep 11 07:05:40 AM UTC 24 |
265641132 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_alert_test.2079002930 |
|
|
Sep 11 07:05:41 AM UTC 24 |
Sep 11 07:05:43 AM UTC 24 |
51879112 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_regwen.2010443271 |
|
|
Sep 11 06:56:58 AM UTC 24 |
Sep 11 07:05:52 AM UTC 24 |
3683468720 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_bijection.2519714475 |
|
|
Sep 11 06:43:33 AM UTC 24 |
Sep 11 07:05:55 AM UTC 24 |
163481275706 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_smoke.3900687335 |
|
|
Sep 11 07:05:44 AM UTC 24 |
Sep 11 07:05:57 AM UTC 24 |
2774392739 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_regwen.3172321017 |
|
|
Sep 11 07:03:21 AM UTC 24 |
Sep 11 07:06:08 AM UTC 24 |
2725218520 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access.3627466090 |
|
|
Sep 11 07:06:09 AM UTC 24 |
Sep 11 07:06:43 AM UTC 24 |
7033920253 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.3761626980 |
|
|
Sep 11 07:05:20 AM UTC 24 |
Sep 11 07:06:50 AM UTC 24 |
2462200773 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_regwen.2848279434 |
|
|
Sep 11 06:58:49 AM UTC 24 |
Sep 11 07:07:05 AM UTC 24 |
3001175797 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.3408421145 |
|
|
Sep 11 07:06:51 AM UTC 24 |
Sep 11 07:07:07 AM UTC 24 |
2814249017 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.4259796362 |
|
|
Sep 11 07:04:06 AM UTC 24 |
Sep 11 07:07:23 AM UTC 24 |
1569065320 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.3629068921 |
|
|
Sep 11 07:07:08 AM UTC 24 |
Sep 11 07:07:36 AM UTC 24 |
11131438051 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.2035296407 |
|
|
Sep 11 06:58:44 AM UTC 24 |
Sep 11 07:08:04 AM UTC 24 |
44178925150 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.2318420640 |
|
|
Sep 11 07:02:31 AM UTC 24 |
Sep 11 07:08:05 AM UTC 24 |
10587523178 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.1542790886 |
|
|
Sep 11 07:08:06 AM UTC 24 |
Sep 11 07:08:12 AM UTC 24 |
1413584804 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.3544888908 |
|
|
Sep 11 07:07:06 AM UTC 24 |
Sep 11 07:08:35 AM UTC 24 |
1580230531 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.1036591094 |
|
|
Sep 11 07:04:14 AM UTC 24 |
Sep 11 07:08:37 AM UTC 24 |
3279438561 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_bijection.64584039 |
|
|
Sep 11 06:58:16 AM UTC 24 |
Sep 11 07:08:37 AM UTC 24 |
9617658284 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.3212127333 |
|
|
Sep 11 07:00:24 AM UTC 24 |
Sep 11 07:08:45 AM UTC 24 |
13496315931 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_alert_test.3160073590 |
|
|
Sep 11 07:08:45 AM UTC 24 |
Sep 11 07:08:47 AM UTC 24 |
13481816 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.3419627666 |
|
|
Sep 11 07:08:37 AM UTC 24 |
Sep 11 07:08:55 AM UTC 24 |
275610285 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.2089745656 |
|
|
Sep 11 07:03:17 AM UTC 24 |
Sep 11 07:08:59 AM UTC 24 |
24450130263 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_smoke.2874069779 |
|
|
Sep 11 07:08:48 AM UTC 24 |
Sep 11 07:09:23 AM UTC 24 |
11260192783 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_bijection.582718765 |
|
|
Sep 11 06:59:58 AM UTC 24 |
Sep 11 07:09:24 AM UTC 24 |
47434653347 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.2200470366 |
|
|
Sep 11 07:00:52 AM UTC 24 |
Sep 11 07:09:46 AM UTC 24 |
71561814801 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.1208046529 |
|
|
Sep 11 06:27:22 AM UTC 24 |
Sep 11 07:09:50 AM UTC 24 |
77895242263 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all.947431090 |
|
|
Sep 11 06:52:13 AM UTC 24 |
Sep 11 07:09:51 AM UTC 24 |
9163148299 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access.4162460791 |
|
|
Sep 11 07:09:25 AM UTC 24 |
Sep 11 07:09:55 AM UTC 24 |
1429250631 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.1332389910 |
|
|
Sep 11 06:59:56 AM UTC 24 |
Sep 11 07:10:06 AM UTC 24 |
31833072439 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.1166872379 |
|
|
Sep 11 07:04:36 AM UTC 24 |
Sep 11 07:10:07 AM UTC 24 |
18087279716 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.2618880374 |
|
|
Sep 11 07:16:51 AM UTC 24 |
Sep 11 07:17:49 AM UTC 24 |
2992047210 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.3957570697 |
|
|
Sep 11 07:09:51 AM UTC 24 |
Sep 11 07:10:09 AM UTC 24 |
2591829982 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.619116210 |
|
|
Sep 11 07:03:34 AM UTC 24 |
Sep 11 07:10:12 AM UTC 24 |
21328295801 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.2279204423 |
|
|
Sep 11 07:10:14 AM UTC 24 |
Sep 11 07:10:20 AM UTC 24 |
353281031 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.2188688875 |
|
|
Sep 11 07:08:13 AM UTC 24 |
Sep 11 07:10:57 AM UTC 24 |
18311944738 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_bijection.4243673118 |
|
|
Sep 11 06:41:32 AM UTC 24 |
Sep 11 07:10:58 AM UTC 24 |
95732855961 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.2603143625 |
|
|
Sep 11 07:09:52 AM UTC 24 |
Sep 11 07:11:11 AM UTC 24 |
3211367620 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.4258990245 |
|
|
Sep 11 07:09:56 AM UTC 24 |
Sep 11 07:11:11 AM UTC 24 |
18241566011 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_alert_test.2582214935 |
|
|
Sep 11 07:11:12 AM UTC 24 |
Sep 11 07:11:14 AM UTC 24 |
40174422 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.231379540 |
|
|
Sep 11 07:10:59 AM UTC 24 |
Sep 11 07:11:21 AM UTC 24 |
1453130153 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_smoke.260604671 |
|
|
Sep 11 07:11:15 AM UTC 24 |
Sep 11 07:11:45 AM UTC 24 |
4811890829 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_executable.2935414996 |
|
|
Sep 11 06:47:42 AM UTC 24 |
Sep 11 07:11:46 AM UTC 24 |
54654580475 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.2915488962 |
|
|
Sep 11 07:05:20 AM UTC 24 |
Sep 11 07:12:03 AM UTC 24 |
20691495715 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.3692943681 |
|
|
Sep 11 07:08:36 AM UTC 24 |
Sep 11 07:12:07 AM UTC 24 |
62840812432 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access.2691801200 |
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|
Sep 11 07:12:04 AM UTC 24 |
Sep 11 07:12:19 AM UTC 24 |
1587143913 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_bijection.4053975074 |
|
|
Sep 11 06:39:55 AM UTC 24 |
Sep 11 07:12:35 AM UTC 24 |
29301703309 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_executable.4221586836 |
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|
Sep 11 06:56:56 AM UTC 24 |
Sep 11 07:12:36 AM UTC 24 |
6684504417 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_regwen.3235053590 |
|
|
Sep 11 07:05:06 AM UTC 24 |
Sep 11 07:12:36 AM UTC 24 |
2361835460 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.2403647577 |
|
|
Sep 11 07:05:57 AM UTC 24 |
Sep 11 07:12:37 AM UTC 24 |
5041288469 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.1508222072 |
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|
Sep 11 07:05:52 AM UTC 24 |
Sep 11 07:12:38 AM UTC 24 |
7824923569 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.1081827738 |
|
|
Sep 11 07:12:20 AM UTC 24 |
Sep 11 07:12:48 AM UTC 24 |
1491444759 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.2120257410 |
|
|
Sep 11 07:12:49 AM UTC 24 |
Sep 11 07:12:53 AM UTC 24 |
564030434 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.3903194272 |
|
|
Sep 11 07:12:36 AM UTC 24 |
Sep 11 07:12:59 AM UTC 24 |
750988272 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_regwen.830156419 |
|
|
Sep 11 07:08:05 AM UTC 24 |
Sep 11 07:13:03 AM UTC 24 |
948620609 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.2654071490 |
|
|
Sep 11 07:10:58 AM UTC 24 |
Sep 11 07:13:07 AM UTC 24 |
6386871254 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.3115617095 |
|
|
Sep 11 07:10:21 AM UTC 24 |
Sep 11 07:13:26 AM UTC 24 |
10661077136 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.560224518 |
|
|
Sep 11 07:07:23 AM UTC 24 |
Sep 11 07:13:28 AM UTC 24 |
6971453555 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.3551236659 |
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Sep 11 07:09:24 AM UTC 24 |
Sep 11 07:13:28 AM UTC 24 |
46950538199 ps |