| T799 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_alert_test.1720843930 |
|
|
Sep 11 07:47:52 AM UTC 24 |
Sep 11 07:47:54 AM UTC 24 |
42719374 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access.1657344131 |
|
|
Sep 11 07:46:24 AM UTC 24 |
Sep 11 07:47:58 AM UTC 24 |
540499158 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.3754060486 |
|
|
Sep 11 07:42:05 AM UTC 24 |
Sep 11 07:48:02 AM UTC 24 |
5430003307 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.3042979279 |
|
|
Sep 11 07:45:05 AM UTC 24 |
Sep 11 07:48:05 AM UTC 24 |
2634990180 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.1712173625 |
|
|
Sep 11 07:42:54 AM UTC 24 |
Sep 11 07:48:10 AM UTC 24 |
35004895052 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_executable.187910413 |
|
|
Sep 11 07:42:31 AM UTC 24 |
Sep 11 07:48:13 AM UTC 24 |
18710688633 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.701771725 |
|
|
Sep 11 07:47:35 AM UTC 24 |
Sep 11 07:48:16 AM UTC 24 |
2648299872 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_smoke.1479639363 |
|
|
Sep 11 07:47:54 AM UTC 24 |
Sep 11 07:48:28 AM UTC 24 |
3636359160 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access.124790984 |
|
|
Sep 11 07:48:05 AM UTC 24 |
Sep 11 07:48:53 AM UTC 24 |
1039171942 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.1253382772 |
|
|
Sep 11 07:48:14 AM UTC 24 |
Sep 11 07:48:56 AM UTC 24 |
736564084 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.362353300 |
|
|
Sep 11 07:47:26 AM UTC 24 |
Sep 11 07:49:57 AM UTC 24 |
4389901403 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_regwen.814943558 |
|
|
Sep 11 07:42:33 AM UTC 24 |
Sep 11 07:50:00 AM UTC 24 |
16530338800 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_bijection.41685093 |
|
|
Sep 11 07:04:13 AM UTC 24 |
Sep 11 07:50:03 AM UTC 24 |
380939637752 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.959984505 |
|
|
Sep 11 07:48:17 AM UTC 24 |
Sep 11 07:50:05 AM UTC 24 |
3105882999 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.138843620 |
|
|
Sep 11 07:50:01 AM UTC 24 |
Sep 11 07:50:06 AM UTC 24 |
502690975 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.2085800013 |
|
|
Sep 11 07:47:24 AM UTC 24 |
Sep 11 07:50:12 AM UTC 24 |
28879580879 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_regwen.4291154445 |
|
|
Sep 11 07:33:30 AM UTC 24 |
Sep 11 07:50:36 AM UTC 24 |
11995662742 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_alert_test.3590199481 |
|
|
Sep 11 07:50:37 AM UTC 24 |
Sep 11 07:50:39 AM UTC 24 |
42504652 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.475268248 |
|
|
Sep 11 07:48:29 AM UTC 24 |
Sep 11 07:50:48 AM UTC 24 |
24093461328 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.206787169 |
|
|
Sep 11 07:50:07 AM UTC 24 |
Sep 11 07:50:48 AM UTC 24 |
3797565670 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.1187463943 |
|
|
Sep 11 07:48:54 AM UTC 24 |
Sep 11 07:50:58 AM UTC 24 |
4731811872 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_smoke.1486865652 |
|
|
Sep 11 07:50:40 AM UTC 24 |
Sep 11 07:51:02 AM UTC 24 |
2782262323 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.740970003 |
|
|
Sep 11 07:35:41 AM UTC 24 |
Sep 11 07:51:03 AM UTC 24 |
116361335014 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access.1464910451 |
|
|
Sep 11 07:51:03 AM UTC 24 |
Sep 11 07:51:33 AM UTC 24 |
4746761239 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.2380262998 |
|
|
Sep 11 07:43:42 AM UTC 24 |
Sep 11 07:51:44 AM UTC 24 |
75497411335 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_bijection.2692811036 |
|
|
Sep 11 07:34:41 AM UTC 24 |
Sep 11 07:51:54 AM UTC 24 |
112975589095 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.1475366008 |
|
|
Sep 11 07:36:31 AM UTC 24 |
Sep 11 07:51:56 AM UTC 24 |
44371371882 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.2623994928 |
|
|
Sep 11 07:50:04 AM UTC 24 |
Sep 11 07:52:13 AM UTC 24 |
3947500088 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.2297471453 |
|
|
Sep 11 07:46:05 AM UTC 24 |
Sep 11 07:52:20 AM UTC 24 |
9168701264 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.2072531533 |
|
|
Sep 11 07:44:34 AM UTC 24 |
Sep 11 07:52:32 AM UTC 24 |
36971687194 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.3889683727 |
|
|
Sep 11 07:52:34 AM UTC 24 |
Sep 11 07:52:40 AM UTC 24 |
1304836416 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.2264935262 |
|
|
Sep 11 07:51:45 AM UTC 24 |
Sep 11 07:52:49 AM UTC 24 |
789402037 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.3333930065 |
|
|
Sep 11 07:42:30 AM UTC 24 |
Sep 11 07:52:50 AM UTC 24 |
49577777686 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.1311824300 |
|
|
Sep 11 07:50:07 AM UTC 24 |
Sep 11 07:52:53 AM UTC 24 |
20888618023 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_executable.3962501775 |
|
|
Sep 11 07:27:17 AM UTC 24 |
Sep 11 07:53:00 AM UTC 24 |
22921832825 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.2979805586 |
|
|
Sep 11 07:51:34 AM UTC 24 |
Sep 11 07:53:01 AM UTC 24 |
1575592282 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_alert_test.2243568376 |
|
|
Sep 11 07:53:00 AM UTC 24 |
Sep 11 07:53:02 AM UTC 24 |
42235664 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.773797554 |
|
|
Sep 11 07:51:55 AM UTC 24 |
Sep 11 07:53:04 AM UTC 24 |
50662406434 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2728623923 |
|
|
Sep 11 07:52:51 AM UTC 24 |
Sep 11 07:53:11 AM UTC 24 |
428707457 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_executable.2750803644 |
|
|
Sep 11 07:40:15 AM UTC 24 |
Sep 11 07:53:18 AM UTC 24 |
49604697618 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_regwen.3862896296 |
|
|
Sep 11 07:47:12 AM UTC 24 |
Sep 11 07:53:47 AM UTC 24 |
13282009051 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.2487667879 |
|
|
Sep 11 07:51:04 AM UTC 24 |
Sep 11 07:53:51 AM UTC 24 |
11471927103 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.2135580663 |
|
|
Sep 11 07:48:03 AM UTC 24 |
Sep 11 07:53:55 AM UTC 24 |
4204354099 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.3593522832 |
|
|
Sep 11 07:47:55 AM UTC 24 |
Sep 11 07:54:26 AM UTC 24 |
54279762348 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_smoke.2706629947 |
|
|
Sep 11 07:53:02 AM UTC 24 |
Sep 11 07:54:34 AM UTC 24 |
894181120 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.1702585828 |
|
|
Sep 11 07:53:56 AM UTC 24 |
Sep 11 07:54:38 AM UTC 24 |
2428161438 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access.1138944644 |
|
|
Sep 11 07:53:19 AM UTC 24 |
Sep 11 07:54:48 AM UTC 24 |
1282707841 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.636576498 |
|
|
Sep 11 07:52:51 AM UTC 24 |
Sep 11 07:55:05 AM UTC 24 |
3418405731 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.2110917584 |
|
|
Sep 11 07:54:35 AM UTC 24 |
Sep 11 07:55:07 AM UTC 24 |
1651525027 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.435327215 |
|
|
Sep 11 07:55:06 AM UTC 24 |
Sep 11 07:55:12 AM UTC 24 |
1301934884 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_bijection.1186918706 |
|
|
Sep 11 07:05:55 AM UTC 24 |
Sep 11 07:55:29 AM UTC 24 |
304985536544 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_bijection.552079423 |
|
|
Sep 11 07:36:40 AM UTC 24 |
Sep 11 07:55:33 AM UTC 24 |
203128176162 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.790764765 |
|
|
Sep 11 07:54:26 AM UTC 24 |
Sep 11 07:55:34 AM UTC 24 |
8955546977 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_alert_test.1385117509 |
|
|
Sep 11 07:55:35 AM UTC 24 |
Sep 11 07:55:37 AM UTC 24 |
22421394 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_bijection.527536607 |
|
|
Sep 11 07:22:50 AM UTC 24 |
Sep 11 07:55:39 AM UTC 24 |
442105316341 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.404401876 |
|
|
Sep 11 07:52:41 AM UTC 24 |
Sep 11 07:58:32 AM UTC 24 |
57699680167 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.1158101705 |
|
|
Sep 11 07:53:52 AM UTC 24 |
Sep 11 07:55:40 AM UTC 24 |
809653709 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.267048715 |
|
|
Sep 11 07:46:56 AM UTC 24 |
Sep 11 07:55:43 AM UTC 24 |
15317433861 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_smoke.1336512583 |
|
|
Sep 11 07:55:38 AM UTC 24 |
Sep 11 07:55:53 AM UTC 24 |
815190225 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.1669442462 |
|
|
Sep 11 07:48:10 AM UTC 24 |
Sep 11 07:55:54 AM UTC 24 |
74044278194 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1061616330 |
|
|
Sep 11 07:55:30 AM UTC 24 |
Sep 11 07:55:57 AM UTC 24 |
3310523035 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.3303996578 |
|
|
Sep 11 07:51:00 AM UTC 24 |
Sep 11 07:56:04 AM UTC 24 |
14199955389 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.871694162 |
|
|
Sep 11 07:41:28 AM UTC 24 |
Sep 11 07:56:15 AM UTC 24 |
14587705779 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_executable.4220797040 |
|
|
Sep 11 07:47:11 AM UTC 24 |
Sep 11 07:56:17 AM UTC 24 |
5574881941 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all.3962325405 |
|
|
Sep 11 07:31:31 AM UTC 24 |
Sep 11 07:56:50 AM UTC 24 |
25520322382 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_executable.4166588596 |
|
|
Sep 11 07:44:50 AM UTC 24 |
Sep 11 07:56:52 AM UTC 24 |
14660024531 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access.2717319615 |
|
|
Sep 11 07:55:55 AM UTC 24 |
Sep 11 07:57:18 AM UTC 24 |
1097080562 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.339049301 |
|
|
Sep 11 07:56:05 AM UTC 24 |
Sep 11 07:57:23 AM UTC 24 |
9549046784 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.684648454 |
|
|
Sep 11 07:57:18 AM UTC 24 |
Sep 11 07:57:24 AM UTC 24 |
355845072 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.3974716364 |
|
|
Sep 11 07:46:32 AM UTC 24 |
Sep 11 07:57:28 AM UTC 24 |
22056605054 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.1016593723 |
|
|
Sep 11 07:25:34 AM UTC 24 |
Sep 11 07:57:41 AM UTC 24 |
189994478722 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.4251464536 |
|
|
Sep 11 07:55:08 AM UTC 24 |
Sep 11 07:57:44 AM UTC 24 |
2058591565 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.3993695376 |
|
|
Sep 11 07:55:58 AM UTC 24 |
Sep 11 07:57:47 AM UTC 24 |
780884235 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_alert_test.3429574784 |
|
|
Sep 11 07:57:45 AM UTC 24 |
Sep 11 07:57:47 AM UTC 24 |
18619049 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_bijection.1180650867 |
|
|
Sep 11 07:43:30 AM UTC 24 |
Sep 11 07:58:11 AM UTC 24 |
13794921487 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_regwen.583375823 |
|
|
Sep 11 07:52:22 AM UTC 24 |
Sep 11 07:58:13 AM UTC 24 |
24421411289 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.3720974163 |
|
|
Sep 11 07:31:58 AM UTC 24 |
Sep 11 07:58:21 AM UTC 24 |
56382359714 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_bijection.666327723 |
|
|
Sep 11 07:29:25 AM UTC 24 |
Sep 11 07:58:24 AM UTC 24 |
104058272673 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all.3031092836 |
|
|
Sep 11 07:38:13 AM UTC 24 |
Sep 11 07:58:27 AM UTC 24 |
33035407388 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.3714640440 |
|
|
Sep 11 07:55:13 AM UTC 24 |
Sep 11 07:58:30 AM UTC 24 |
20950286461 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.1308915986 |
|
|
Sep 11 07:56:16 AM UTC 24 |
Sep 11 07:58:30 AM UTC 24 |
23093755836 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.3959105524 |
|
|
Sep 11 07:58:28 AM UTC 24 |
Sep 11 07:58:38 AM UTC 24 |
1373898670 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.846928102 |
|
|
Sep 11 07:45:51 AM UTC 24 |
Sep 11 07:58:45 AM UTC 24 |
57403951583 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access.1578228485 |
|
|
Sep 11 07:58:21 AM UTC 24 |
Sep 11 07:58:48 AM UTC 24 |
1700848465 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.2196467443 |
|
|
Sep 11 07:58:31 AM UTC 24 |
Sep 11 07:58:54 AM UTC 24 |
2937450547 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.2752942025 |
|
|
Sep 11 07:58:49 AM UTC 24 |
Sep 11 07:58:57 AM UTC 24 |
2393291911 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_bijection.1848655845 |
|
|
Sep 11 07:41:32 AM UTC 24 |
Sep 11 07:59:00 AM UTC 24 |
66953298799 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_smoke.1520360802 |
|
|
Sep 11 07:57:47 AM UTC 24 |
Sep 11 07:59:01 AM UTC 24 |
3132706994 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_regwen.2067523059 |
|
|
Sep 11 07:35:53 AM UTC 24 |
Sep 11 07:59:05 AM UTC 24 |
18684342967 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.3756926311 |
|
|
Sep 11 07:53:13 AM UTC 24 |
Sep 11 07:59:07 AM UTC 24 |
20718118822 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_alert_test.829393716 |
|
|
Sep 11 07:59:06 AM UTC 24 |
Sep 11 07:59:08 AM UTC 24 |
13160780 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all.3901028679 |
|
|
Sep 11 07:11:11 AM UTC 24 |
Sep 11 07:59:16 AM UTC 24 |
26325318266 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1226547154 |
|
|
Sep 11 07:57:29 AM UTC 24 |
Sep 11 07:59:41 AM UTC 24 |
1268032154 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.3868089684 |
|
|
Sep 11 07:58:31 AM UTC 24 |
Sep 11 07:59:42 AM UTC 24 |
53843758201 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1462314486 |
|
|
Sep 11 07:59:01 AM UTC 24 |
Sep 11 07:59:48 AM UTC 24 |
1225630488 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all.1106447241 |
|
|
Sep 11 06:20:45 AM UTC 24 |
Sep 11 07:59:59 AM UTC 24 |
508005538128 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_executable.3351631331 |
|
|
Sep 11 07:54:39 AM UTC 24 |
Sep 11 08:00:00 AM UTC 24 |
5815012673 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.2777602515 |
|
|
Sep 11 07:57:24 AM UTC 24 |
Sep 11 08:00:12 AM UTC 24 |
10521891608 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.2906721206 |
|
|
Sep 11 07:55:44 AM UTC 24 |
Sep 11 08:00:12 AM UTC 24 |
4168941320 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all.381843239 |
|
|
Sep 11 07:03:53 AM UTC 24 |
Sep 11 08:00:32 AM UTC 24 |
134246363592 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.164102243 |
|
|
Sep 11 07:58:58 AM UTC 24 |
Sep 11 08:00:33 AM UTC 24 |
2945274623 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.3846399045 |
|
|
Sep 11 07:57:26 AM UTC 24 |
Sep 11 08:00:51 AM UTC 24 |
5419732194 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_executable.205039601 |
|
|
Sep 11 07:56:50 AM UTC 24 |
Sep 11 08:01:04 AM UTC 24 |
19368279377 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.2773977917 |
|
|
Sep 11 07:58:55 AM UTC 24 |
Sep 11 08:01:25 AM UTC 24 |
2661740742 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all.2362215795 |
|
|
Sep 11 06:48:02 AM UTC 24 |
Sep 11 08:01:43 AM UTC 24 |
87747116352 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.197755240 |
|
|
Sep 11 07:55:55 AM UTC 24 |
Sep 11 08:01:46 AM UTC 24 |
22280219231 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_executable.2149206696 |
|
|
Sep 11 07:48:57 AM UTC 24 |
Sep 11 08:01:54 AM UTC 24 |
58129126770 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_bijection.4009752116 |
|
|
Sep 11 07:45:59 AM UTC 24 |
Sep 11 08:02:16 AM UTC 24 |
48498430857 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_regwen.3852817730 |
|
|
Sep 11 07:44:59 AM UTC 24 |
Sep 11 08:02:42 AM UTC 24 |
12066615008 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.3852533475 |
|
|
Sep 11 07:53:48 AM UTC 24 |
Sep 11 08:03:11 AM UTC 24 |
45382277062 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.1964569492 |
|
|
Sep 11 07:51:57 AM UTC 24 |
Sep 11 08:03:35 AM UTC 24 |
62005890918 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_executable.3942360803 |
|
|
Sep 11 07:52:13 AM UTC 24 |
Sep 11 08:03:39 AM UTC 24 |
21832669372 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.1155222876 |
|
|
Sep 11 07:58:14 AM UTC 24 |
Sep 11 08:03:55 AM UTC 24 |
4159863279 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.231235614 |
|
|
Sep 11 07:58:26 AM UTC 24 |
Sep 11 08:04:23 AM UTC 24 |
13205239562 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.633900557 |
|
|
Sep 11 07:50:49 AM UTC 24 |
Sep 11 08:04:33 AM UTC 24 |
22851140597 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_regwen.1700678047 |
|
|
Sep 11 07:56:52 AM UTC 24 |
Sep 11 08:05:17 AM UTC 24 |
10573283427 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_executable.197858433 |
|
|
Sep 11 07:58:39 AM UTC 24 |
Sep 11 08:05:38 AM UTC 24 |
17531438967 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.353638919 |
|
|
Sep 11 07:55:39 AM UTC 24 |
Sep 11 08:06:58 AM UTC 24 |
39859304657 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.697746028 |
|
|
Sep 11 07:57:48 AM UTC 24 |
Sep 11 08:07:08 AM UTC 24 |
34121310027 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all.1119561223 |
|
|
Sep 11 06:57:42 AM UTC 24 |
Sep 11 08:08:23 AM UTC 24 |
437835180603 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.1347090068 |
|
|
Sep 11 07:53:03 AM UTC 24 |
Sep 11 08:08:31 AM UTC 24 |
17014036863 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_bijection.3392555851 |
|
|
Sep 11 07:32:15 AM UTC 24 |
Sep 11 08:08:40 AM UTC 24 |
469637917892 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_bijection.999140986 |
|
|
Sep 11 07:47:58 AM UTC 24 |
Sep 11 08:09:04 AM UTC 24 |
51368822029 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_bijection.3160345321 |
|
|
Sep 11 07:58:11 AM UTC 24 |
Sep 11 08:10:16 AM UTC 24 |
45231859022 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.2421912994 |
|
|
Sep 11 07:56:18 AM UTC 24 |
Sep 11 08:10:29 AM UTC 24 |
11291694598 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.2782009483 |
|
|
Sep 11 07:58:33 AM UTC 24 |
Sep 11 08:10:30 AM UTC 24 |
154317070165 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_regwen.2226977591 |
|
|
Sep 11 07:54:48 AM UTC 24 |
Sep 11 08:10:50 AM UTC 24 |
3610925071 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_bijection.3827972505 |
|
|
Sep 11 07:50:49 AM UTC 24 |
Sep 11 08:11:47 AM UTC 24 |
127742337031 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all.505999120 |
|
|
Sep 11 07:25:31 AM UTC 24 |
Sep 11 08:12:27 AM UTC 24 |
657774915609 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all.1765934282 |
|
|
Sep 11 07:05:30 AM UTC 24 |
Sep 11 08:12:45 AM UTC 24 |
698526631106 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all.3107571282 |
|
|
Sep 11 07:34:12 AM UTC 24 |
Sep 11 08:14:32 AM UTC 24 |
132340100299 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_regwen.746360862 |
|
|
Sep 11 07:49:58 AM UTC 24 |
Sep 11 08:15:19 AM UTC 24 |
20748223290 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_bijection.4071140214 |
|
|
Sep 11 07:38:33 AM UTC 24 |
Sep 11 08:16:05 AM UTC 24 |
32459937708 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_regwen.1579654271 |
|
|
Sep 11 07:58:45 AM UTC 24 |
Sep 11 08:16:52 AM UTC 24 |
26247003221 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all.2416105924 |
|
|
Sep 11 07:43:24 AM UTC 24 |
Sep 11 08:17:14 AM UTC 24 |
215213629516 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_bijection.2088186218 |
|
|
Sep 11 07:55:40 AM UTC 24 |
Sep 11 08:17:44 AM UTC 24 |
132988228192 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all.1504107739 |
|
|
Sep 11 07:28:43 AM UTC 24 |
Sep 11 08:21:22 AM UTC 24 |
68153276755 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all.4180980278 |
|
|
Sep 11 07:13:08 AM UTC 24 |
Sep 11 08:24:43 AM UTC 24 |
1197980878172 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all.938393377 |
|
|
Sep 11 07:17:57 AM UTC 24 |
Sep 11 08:27:42 AM UTC 24 |
159314197432 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all.3678375963 |
|
|
Sep 11 07:22:14 AM UTC 24 |
Sep 11 08:29:22 AM UTC 24 |
119390119328 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all.3064456853 |
|
|
Sep 11 07:36:23 AM UTC 24 |
Sep 11 08:30:12 AM UTC 24 |
46060211428 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all.2323356099 |
|
|
Sep 11 07:41:22 AM UTC 24 |
Sep 11 08:35:23 AM UTC 24 |
42336642848 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_bijection.3549253571 |
|
|
Sep 11 07:53:05 AM UTC 24 |
Sep 11 08:38:29 AM UTC 24 |
116274171189 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all.1176957879 |
|
|
Sep 11 07:02:00 AM UTC 24 |
Sep 11 08:39:28 AM UTC 24 |
147805814746 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all.1896223190 |
|
|
Sep 11 07:57:42 AM UTC 24 |
Sep 11 08:47:20 AM UTC 24 |
28513396299 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all.1530763207 |
|
|
Sep 11 07:45:31 AM UTC 24 |
Sep 11 08:50:09 AM UTC 24 |
53671125236 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all.888941928 |
|
|
Sep 11 07:15:42 AM UTC 24 |
Sep 11 08:52:23 AM UTC 24 |
317314814272 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all.2485574219 |
|
|
Sep 11 07:52:54 AM UTC 24 |
Sep 11 09:04:35 AM UTC 24 |
402077019934 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all.1890183742 |
|
|
Sep 11 07:50:13 AM UTC 24 |
Sep 11 09:05:25 AM UTC 24 |
678220618013 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all.1116633776 |
|
|
Sep 11 07:55:34 AM UTC 24 |
Sep 11 09:13:47 AM UTC 24 |
324095967526 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all.2498384123 |
|
|
Sep 11 07:59:02 AM UTC 24 |
Sep 11 09:39:40 AM UTC 24 |
471986740812 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all.283728466 |
|
|
Sep 11 07:47:51 AM UTC 24 |
Sep 11 09:54:02 AM UTC 24 |
334756372289 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1969639589 |
|
|
Sep 11 07:59:08 AM UTC 24 |
Sep 11 07:59:12 AM UTC 24 |
127696950 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.112371463 |
|
|
Sep 11 07:59:13 AM UTC 24 |
Sep 11 07:59:18 AM UTC 24 |
535885620 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1104220166 |
|
|
Sep 11 07:59:17 AM UTC 24 |
Sep 11 07:59:20 AM UTC 24 |
26439245 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3427067534 |
|
|
Sep 11 07:59:18 AM UTC 24 |
Sep 11 07:59:20 AM UTC 24 |
12780399 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3546245974 |
|
|
Sep 11 07:59:20 AM UTC 24 |
Sep 11 07:59:24 AM UTC 24 |
361516852 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1187072776 |
|
|
Sep 11 07:59:21 AM UTC 24 |
Sep 11 07:59:24 AM UTC 24 |
87898189 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.734568005 |
|
|
Sep 11 07:59:24 AM UTC 24 |
Sep 11 07:59:27 AM UTC 24 |
138588627 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3552621533 |
|
|
Sep 11 07:59:26 AM UTC 24 |
Sep 11 07:59:34 AM UTC 24 |
370858819 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1530785504 |
|
|
Sep 11 07:59:35 AM UTC 24 |
Sep 11 07:59:40 AM UTC 24 |
235426447 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3759217582 |
|
|
Sep 11 07:59:42 AM UTC 24 |
Sep 11 07:59:44 AM UTC 24 |
21668034 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3915749885 |
|
|
Sep 11 07:59:41 AM UTC 24 |
Sep 11 07:59:45 AM UTC 24 |
176812994 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3176968667 |
|
|
Sep 11 07:59:43 AM UTC 24 |
Sep 11 07:59:45 AM UTC 24 |
43199546 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3638669625 |
|
|
Sep 11 07:59:45 AM UTC 24 |
Sep 11 07:59:48 AM UTC 24 |
13199059 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2300509128 |
|
|
Sep 11 07:59:46 AM UTC 24 |
Sep 11 07:59:49 AM UTC 24 |
79845950 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1029088014 |
|
|
Sep 11 07:59:45 AM UTC 24 |
Sep 11 07:59:49 AM UTC 24 |
247000338 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.4199874182 |
|
|
Sep 11 07:59:50 AM UTC 24 |
Sep 11 07:59:54 AM UTC 24 |
251616353 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.875485950 |
|
|
Sep 11 07:59:50 AM UTC 24 |
Sep 11 07:59:55 AM UTC 24 |
309495209 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1040007516 |
|
|
Sep 11 07:59:55 AM UTC 24 |
Sep 11 07:59:57 AM UTC 24 |
12682151 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1393708469 |
|
|
Sep 11 07:59:49 AM UTC 24 |
Sep 11 07:59:57 AM UTC 24 |
355997496 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3251315692 |
|
|
Sep 11 07:59:56 AM UTC 24 |
Sep 11 07:59:58 AM UTC 24 |
13040918 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2602531375 |
|
|
Sep 11 07:59:58 AM UTC 24 |
Sep 11 08:00:00 AM UTC 24 |
13622502 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3121604860 |
|
|
Sep 11 07:59:59 AM UTC 24 |
Sep 11 08:00:01 AM UTC 24 |
15331208 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3023562546 |
|
|
Sep 11 07:59:58 AM UTC 24 |
Sep 11 08:00:03 AM UTC 24 |
185274009 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1766334609 |
|
|
Sep 11 08:00:03 AM UTC 24 |
Sep 11 08:00:08 AM UTC 24 |
154166794 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2118125357 |
|
|
Sep 11 08:00:07 AM UTC 24 |
Sep 11 08:00:09 AM UTC 24 |
41042075 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.284016730 |
|
|
Sep 11 08:00:00 AM UTC 24 |
Sep 11 08:00:10 AM UTC 24 |
724557346 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2413563238 |
|
|
Sep 11 08:00:01 AM UTC 24 |
Sep 11 08:00:10 AM UTC 24 |
146077486 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2973924265 |
|
|
Sep 11 08:00:10 AM UTC 24 |
Sep 11 08:00:12 AM UTC 24 |
95576922 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2147154900 |
|
|
Sep 11 08:00:10 AM UTC 24 |
Sep 11 08:00:13 AM UTC 24 |
182539909 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.64416983 |
|
|
Sep 11 08:00:11 AM UTC 24 |
Sep 11 08:00:13 AM UTC 24 |
20572282 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2203413361 |
|
|
Sep 11 08:00:11 AM UTC 24 |
Sep 11 08:00:13 AM UTC 24 |
52971202 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3777166275 |
|
|
Sep 11 08:00:15 AM UTC 24 |
Sep 11 08:00:16 AM UTC 24 |
32956945 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1420945121 |
|
|
Sep 11 08:00:15 AM UTC 24 |
Sep 11 08:00:17 AM UTC 24 |
50097057 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3525793643 |
|
|
Sep 11 08:00:12 AM UTC 24 |
Sep 11 08:00:18 AM UTC 24 |
1281114702 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1798769853 |
|
|
Sep 11 08:00:13 AM UTC 24 |
Sep 11 08:00:18 AM UTC 24 |
74726867 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1796192787 |
|
|
Sep 11 08:00:14 AM UTC 24 |
Sep 11 08:00:18 AM UTC 24 |
173943277 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1948018901 |
|
|
Sep 11 08:00:18 AM UTC 24 |
Sep 11 08:00:20 AM UTC 24 |
16354612 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.975482023 |
|
|
Sep 11 08:00:18 AM UTC 24 |
Sep 11 08:00:21 AM UTC 24 |
155829662 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1990490744 |
|
|
Sep 11 08:00:19 AM UTC 24 |
Sep 11 08:00:21 AM UTC 24 |
33196564 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1249199453 |
|
|
Sep 11 08:00:22 AM UTC 24 |
Sep 11 08:00:24 AM UTC 24 |
15533958 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.340217781 |
|
|
Sep 11 08:00:20 AM UTC 24 |
Sep 11 08:00:25 AM UTC 24 |
68842368 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4031269484 |
|
|
Sep 11 07:59:49 AM UTC 24 |
Sep 11 08:00:26 AM UTC 24 |
7412242593 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2739247711 |
|
|
Sep 11 08:00:19 AM UTC 24 |
Sep 11 08:00:26 AM UTC 24 |
1497654316 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1888115923 |
|
|
Sep 11 08:00:22 AM UTC 24 |
Sep 11 08:00:27 AM UTC 24 |
181031898 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2986462038 |
|
|
Sep 11 08:00:26 AM UTC 24 |
Sep 11 08:00:28 AM UTC 24 |
41076526 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2125640582 |
|
|
Sep 11 08:00:29 AM UTC 24 |
Sep 11 08:00:31 AM UTC 24 |
14894536 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3952451156 |
|
|
Sep 11 08:00:27 AM UTC 24 |
Sep 11 08:00:32 AM UTC 24 |
81854310 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1247361423 |
|
|
Sep 11 08:00:26 AM UTC 24 |
Sep 11 08:00:33 AM UTC 24 |
351905020 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.45318184 |
|
|
Sep 11 07:59:08 AM UTC 24 |
Sep 11 08:00:33 AM UTC 24 |
14879268816 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.422746642 |
|
|
Sep 11 08:00:28 AM UTC 24 |
Sep 11 08:00:34 AM UTC 24 |
4717671179 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.27007590 |
|
|
Sep 11 08:00:32 AM UTC 24 |
Sep 11 08:00:34 AM UTC 24 |
29431281 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1348272939 |
|
|
Sep 11 08:00:35 AM UTC 24 |
Sep 11 08:00:37 AM UTC 24 |
20025881 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1851058781 |
|
|
Sep 11 08:00:35 AM UTC 24 |
Sep 11 08:00:37 AM UTC 24 |
20382669 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1982797637 |
|
|
Sep 11 08:00:43 AM UTC 24 |
Sep 11 08:00:49 AM UTC 24 |
449766667 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3023878578 |
|
|
Sep 11 07:59:28 AM UTC 24 |
Sep 11 08:00:38 AM UTC 24 |
22087779675 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2429140605 |
|
|
Sep 11 08:00:33 AM UTC 24 |
Sep 11 08:00:38 AM UTC 24 |
136040817 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3469402034 |
|
|
Sep 11 08:00:33 AM UTC 24 |
Sep 11 08:00:39 AM UTC 24 |
350632433 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2801578866 |
|
|
Sep 11 08:00:39 AM UTC 24 |
Sep 11 08:00:41 AM UTC 24 |
16638603 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.554661884 |
|
|
Sep 11 08:00:39 AM UTC 24 |
Sep 11 08:00:41 AM UTC 24 |
38047272 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2143766405 |
|
|
Sep 11 08:00:38 AM UTC 24 |
Sep 11 08:00:44 AM UTC 24 |
282149539 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3941116315 |
|
|
Sep 11 08:00:39 AM UTC 24 |
Sep 11 08:00:44 AM UTC 24 |
1684993859 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3809988485 |
|
|
Sep 11 08:00:35 AM UTC 24 |
Sep 11 08:00:45 AM UTC 24 |
5715749141 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1768799496 |
|
|
Sep 11 08:00:45 AM UTC 24 |
Sep 11 08:00:47 AM UTC 24 |
13822284 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3345682586 |
|
|
Sep 11 08:00:40 AM UTC 24 |
Sep 11 08:00:48 AM UTC 24 |
387651850 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1382865945 |
|
|
Sep 11 08:00:45 AM UTC 24 |
Sep 11 08:00:48 AM UTC 24 |
159637552 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2163877338 |
|
|
Sep 11 08:00:46 AM UTC 24 |
Sep 11 08:00:48 AM UTC 24 |
44795418 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.285517116 |
|
|
Sep 11 08:00:50 AM UTC 24 |
Sep 11 08:00:52 AM UTC 24 |
20888085 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2311694634 |
|
|
Sep 11 08:00:50 AM UTC 24 |
Sep 11 08:00:54 AM UTC 24 |
23115496 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2641249500 |
|
|
Sep 11 08:00:52 AM UTC 24 |
Sep 11 08:00:54 AM UTC 24 |
21484620 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.659029954 |
|
|
Sep 11 08:00:50 AM UTC 24 |
Sep 11 08:00:54 AM UTC 24 |
327787536 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2865717601 |
|
|
Sep 11 08:00:48 AM UTC 24 |
Sep 11 08:00:56 AM UTC 24 |
803691457 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3203870861 |
|
|
Sep 11 08:00:57 AM UTC 24 |
Sep 11 08:00:59 AM UTC 24 |
45931810 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3916989338 |
|
|
Sep 11 08:00:56 AM UTC 24 |
Sep 11 08:01:00 AM UTC 24 |
164071815 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3444852125 |
|
|
Sep 11 08:00:54 AM UTC 24 |
Sep 11 08:01:01 AM UTC 24 |
249369580 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.549957685 |
|
|
Sep 11 08:01:00 AM UTC 24 |
Sep 11 08:01:02 AM UTC 24 |
45215938 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2050788436 |
|
|
Sep 11 08:00:53 AM UTC 24 |
Sep 11 08:01:03 AM UTC 24 |
2905911980 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2460054002 |
|
|
Sep 11 08:01:05 AM UTC 24 |
Sep 11 08:01:07 AM UTC 24 |
20167981 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2018577829 |
|
|
Sep 11 08:01:03 AM UTC 24 |
Sep 11 08:01:08 AM UTC 24 |
77838219 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.302206668 |
|
|
Sep 11 08:01:01 AM UTC 24 |
Sep 11 08:01:09 AM UTC 24 |
3901109514 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3614043336 |
|
|
Sep 11 08:01:05 AM UTC 24 |
Sep 11 08:01:10 AM UTC 24 |
554397185 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2479180615 |
|
|
Sep 11 08:01:08 AM UTC 24 |
Sep 11 08:01:10 AM UTC 24 |
49000891 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.229496533 |
|
|
Sep 11 08:00:38 AM UTC 24 |
Sep 11 08:01:13 AM UTC 24 |
3851329626 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2757149525 |
|
|
Sep 11 08:01:12 AM UTC 24 |
Sep 11 08:01:14 AM UTC 24 |
63549747 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.276204437 |
|
|
Sep 11 08:01:09 AM UTC 24 |
Sep 11 08:01:15 AM UTC 24 |
627890249 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1836371292 |
|
|
Sep 11 08:00:33 AM UTC 24 |
Sep 11 08:01:16 AM UTC 24 |
14820491448 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3435308755 |
|
|
Sep 11 08:01:10 AM UTC 24 |
Sep 11 08:01:16 AM UTC 24 |
245881477 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1142939361 |
|
|
Sep 11 08:01:11 AM UTC 24 |
Sep 11 08:01:16 AM UTC 24 |
162316862 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2461041962 |
|
|
Sep 11 08:01:14 AM UTC 24 |
Sep 11 08:01:16 AM UTC 24 |
25559822 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2121058441 |
|
|
Sep 11 08:01:17 AM UTC 24 |
Sep 11 08:01:19 AM UTC 24 |
13027909 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1401458852 |
|
|
Sep 11 08:01:17 AM UTC 24 |
Sep 11 08:01:20 AM UTC 24 |
29530787 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3643279753 |
|
|
Sep 11 08:01:17 AM UTC 24 |
Sep 11 08:01:22 AM UTC 24 |
584577033 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2940319127 |
|
|
Sep 11 08:01:16 AM UTC 24 |
Sep 11 08:01:22 AM UTC 24 |
164383049 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1732628350 |
|
|
Sep 11 08:01:15 AM UTC 24 |
Sep 11 08:01:23 AM UTC 24 |
1515930348 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1374997214 |
|
|
Sep 11 08:01:24 AM UTC 24 |
Sep 11 08:01:26 AM UTC 24 |
48564780 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.4135415593 |
|
|
Sep 11 08:01:23 AM UTC 24 |
Sep 11 08:01:26 AM UTC 24 |
230586881 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.500437563 |
|
|
Sep 11 08:01:23 AM UTC 24 |
Sep 11 08:01:27 AM UTC 24 |
207317876 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.363811042 |
|
|
Sep 11 08:01:21 AM UTC 24 |
Sep 11 08:01:28 AM UTC 24 |
1188897617 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2825970161 |
|
|
Sep 11 08:01:26 AM UTC 24 |
Sep 11 08:01:29 AM UTC 24 |
99324199 ps |