| T552 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_alert_test.4263498035 |
|
|
Sep 11 07:13:26 AM UTC 24 |
Sep 11 07:13:28 AM UTC 24 |
13343993 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_regwen.2889078878 |
|
|
Sep 11 07:01:17 AM UTC 24 |
Sep 11 07:13:28 AM UTC 24 |
11954911024 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1163949878 |
|
|
Sep 11 07:13:04 AM UTC 24 |
Sep 11 07:13:30 AM UTC 24 |
798498585 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.1246194896 |
|
|
Sep 11 06:23:25 AM UTC 24 |
Sep 11 07:13:38 AM UTC 24 |
158982537415 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.2641921184 |
|
|
Sep 11 07:12:37 AM UTC 24 |
Sep 11 07:13:45 AM UTC 24 |
6680501185 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_smoke.4244242176 |
|
|
Sep 11 07:13:28 AM UTC 24 |
Sep 11 07:14:03 AM UTC 24 |
6267113038 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.1291217985 |
|
|
Sep 11 07:09:47 AM UTC 24 |
Sep 11 07:14:11 AM UTC 24 |
11423273935 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.1286384901 |
|
|
Sep 11 07:13:45 AM UTC 24 |
Sep 11 07:14:15 AM UTC 24 |
2946875586 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access.2787749176 |
|
|
Sep 11 07:13:31 AM UTC 24 |
Sep 11 07:15:18 AM UTC 24 |
1243079292 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.1398780213 |
|
|
Sep 11 07:10:07 AM UTC 24 |
Sep 11 07:15:21 AM UTC 24 |
37486608444 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.3892280098 |
|
|
Sep 11 07:12:54 AM UTC 24 |
Sep 11 07:15:21 AM UTC 24 |
5263506374 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_executable.1848089519 |
|
|
Sep 11 06:58:49 AM UTC 24 |
Sep 11 07:15:23 AM UTC 24 |
21954793559 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.3366550895 |
|
|
Sep 11 07:15:22 AM UTC 24 |
Sep 11 07:15:26 AM UTC 24 |
360144816 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.2810017148 |
|
|
Sep 11 07:14:12 AM UTC 24 |
Sep 11 07:15:41 AM UTC 24 |
7441629979 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.729555025 |
|
|
Sep 11 07:14:04 AM UTC 24 |
Sep 11 07:15:41 AM UTC 24 |
5988780851 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.622445227 |
|
|
Sep 11 07:06:45 AM UTC 24 |
Sep 11 07:15:54 AM UTC 24 |
64727715274 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_alert_test.2939013399 |
|
|
Sep 11 07:15:56 AM UTC 24 |
Sep 11 07:15:58 AM UTC 24 |
24354885 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_executable.298522304 |
|
|
Sep 11 07:05:00 AM UTC 24 |
Sep 11 07:16:13 AM UTC 24 |
19762137356 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_smoke.674254751 |
|
|
Sep 11 07:15:59 AM UTC 24 |
Sep 11 07:16:21 AM UTC 24 |
1870678467 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.2041010820 |
|
|
Sep 11 07:12:07 AM UTC 24 |
Sep 11 07:16:37 AM UTC 24 |
17583841651 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.2430263519 |
|
|
Sep 11 07:13:00 AM UTC 24 |
Sep 11 07:16:39 AM UTC 24 |
5925211913 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access.834596446 |
|
|
Sep 11 07:16:40 AM UTC 24 |
Sep 11 07:16:49 AM UTC 24 |
405521465 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.538920700 |
|
|
Sep 11 06:58:05 AM UTC 24 |
Sep 11 07:16:49 AM UTC 24 |
55080614827 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_executable.254766655 |
|
|
Sep 11 07:01:08 AM UTC 24 |
Sep 11 07:16:50 AM UTC 24 |
11509622553 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.645516978 |
|
|
Sep 11 07:13:39 AM UTC 24 |
Sep 11 07:16:54 AM UTC 24 |
11974074859 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_executable.1532203691 |
|
|
Sep 11 07:03:21 AM UTC 24 |
Sep 11 07:17:05 AM UTC 24 |
7986245899 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.822657262 |
|
|
Sep 11 07:13:30 AM UTC 24 |
Sep 11 07:17:14 AM UTC 24 |
3687773465 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all.604085686 |
|
|
Sep 11 06:39:41 AM UTC 24 |
Sep 11 07:17:27 AM UTC 24 |
28938829575 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all.2715906924 |
|
|
Sep 11 06:20:31 AM UTC 24 |
Sep 11 07:17:44 AM UTC 24 |
43818090881 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.2160198286 |
|
|
Sep 11 07:16:49 AM UTC 24 |
Sep 11 07:17:44 AM UTC 24 |
10536809344 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.1627850088 |
|
|
Sep 11 07:17:45 AM UTC 24 |
Sep 11 07:17:52 AM UTC 24 |
667935493 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1505994438 |
|
|
Sep 11 07:15:42 AM UTC 24 |
Sep 11 07:17:56 AM UTC 24 |
1624424230 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_bijection.2868617652 |
|
|
Sep 11 06:55:53 AM UTC 24 |
Sep 11 07:18:08 AM UTC 24 |
19676909619 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_executable.3188077333 |
|
|
Sep 11 07:17:15 AM UTC 24 |
Sep 11 07:18:11 AM UTC 24 |
2498248363 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_alert_test.1669325505 |
|
|
Sep 11 07:18:10 AM UTC 24 |
Sep 11 07:18:12 AM UTC 24 |
14544600 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_bijection.279681207 |
|
|
Sep 11 06:30:58 AM UTC 24 |
Sep 11 07:18:13 AM UTC 24 |
225440873535 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_bijection.3731585150 |
|
|
Sep 11 06:29:24 AM UTC 24 |
Sep 11 07:18:13 AM UTC 24 |
547503711152 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_bijection.2472033546 |
|
|
Sep 11 06:50:22 AM UTC 24 |
Sep 11 07:18:18 AM UTC 24 |
897745837298 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_smoke.4145484439 |
|
|
Sep 11 07:18:12 AM UTC 24 |
Sep 11 07:18:19 AM UTC 24 |
376412310 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_bijection.2432752652 |
|
|
Sep 11 06:34:56 AM UTC 24 |
Sep 11 07:18:22 AM UTC 24 |
405150653587 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_executable.3793534475 |
|
|
Sep 11 06:53:04 AM UTC 24 |
Sep 11 07:18:25 AM UTC 24 |
243176168582 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.1113406654 |
|
|
Sep 11 07:16:55 AM UTC 24 |
Sep 11 07:18:27 AM UTC 24 |
49357938236 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.2086534468 |
|
|
Sep 11 07:17:52 AM UTC 24 |
Sep 11 07:18:30 AM UTC 24 |
830315343 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.1601020511 |
|
|
Sep 11 07:14:15 AM UTC 24 |
Sep 11 07:18:31 AM UTC 24 |
10792355363 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.2514920266 |
|
|
Sep 11 07:15:27 AM UTC 24 |
Sep 11 07:18:32 AM UTC 24 |
3169648733 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.4027137289 |
|
|
Sep 11 07:18:23 AM UTC 24 |
Sep 11 07:18:38 AM UTC 24 |
688351266 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.2139694426 |
|
|
Sep 11 07:18:39 AM UTC 24 |
Sep 11 07:18:47 AM UTC 24 |
1350402149 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.912347722 |
|
|
Sep 11 07:16:14 AM UTC 24 |
Sep 11 07:18:59 AM UTC 24 |
880234168 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access.3745962730 |
|
|
Sep 11 07:18:18 AM UTC 24 |
Sep 11 07:19:01 AM UTC 24 |
744358660 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.3658899988 |
|
|
Sep 11 07:17:50 AM UTC 24 |
Sep 11 07:19:04 AM UTC 24 |
1926468233 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.777522143 |
|
|
Sep 11 07:11:48 AM UTC 24 |
Sep 11 07:19:13 AM UTC 24 |
7041303556 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_alert_test.79656775 |
|
|
Sep 11 07:19:13 AM UTC 24 |
Sep 11 07:19:15 AM UTC 24 |
34824798 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1334487295 |
|
|
Sep 11 07:19:01 AM UTC 24 |
Sep 11 07:19:30 AM UTC 24 |
3166256933 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_smoke.4065870439 |
|
|
Sep 11 07:19:16 AM UTC 24 |
Sep 11 07:19:30 AM UTC 24 |
1349079222 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.2334394973 |
|
|
Sep 11 07:04:59 AM UTC 24 |
Sep 11 07:19:34 AM UTC 24 |
130208338769 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_executable.3254836845 |
|
|
Sep 11 07:07:37 AM UTC 24 |
Sep 11 07:19:46 AM UTC 24 |
29896620329 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.4276589935 |
|
|
Sep 11 07:18:28 AM UTC 24 |
Sep 11 07:20:09 AM UTC 24 |
28728931742 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.2811002458 |
|
|
Sep 11 07:17:45 AM UTC 24 |
Sep 11 07:20:13 AM UTC 24 |
8224187368 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.3103893554 |
|
|
Sep 11 07:18:26 AM UTC 24 |
Sep 11 07:20:14 AM UTC 24 |
947653112 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access.1053696275 |
|
|
Sep 11 07:19:47 AM UTC 24 |
Sep 11 07:20:15 AM UTC 24 |
14039965357 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.4181582652 |
|
|
Sep 11 07:20:14 AM UTC 24 |
Sep 11 07:20:30 AM UTC 24 |
1368068295 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_regwen.1965080467 |
|
|
Sep 11 07:10:10 AM UTC 24 |
Sep 11 07:20:45 AM UTC 24 |
24405098138 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.2283667935 |
|
|
Sep 11 07:15:24 AM UTC 24 |
Sep 11 07:20:46 AM UTC 24 |
6487014332 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.1940474951 |
|
|
Sep 11 07:16:49 AM UTC 24 |
Sep 11 07:20:57 AM UTC 24 |
9935111423 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.2311348338 |
|
|
Sep 11 07:20:59 AM UTC 24 |
Sep 11 07:21:05 AM UTC 24 |
5606430629 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.1102561461 |
|
|
Sep 11 07:19:00 AM UTC 24 |
Sep 11 07:21:43 AM UTC 24 |
1663741073 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.488934953 |
|
|
Sep 11 07:20:15 AM UTC 24 |
Sep 11 07:22:03 AM UTC 24 |
815789744 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.2955898533 |
|
|
Sep 11 07:16:38 AM UTC 24 |
Sep 11 07:22:13 AM UTC 24 |
5641516869 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.3620203683 |
|
|
Sep 11 07:08:55 AM UTC 24 |
Sep 11 07:22:33 AM UTC 24 |
133018187558 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.1517101386 |
|
|
Sep 11 07:20:15 AM UTC 24 |
Sep 11 07:22:35 AM UTC 24 |
13408032426 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_alert_test.2988921754 |
|
|
Sep 11 07:22:34 AM UTC 24 |
Sep 11 07:22:36 AM UTC 24 |
14276450 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_smoke.86528338 |
|
|
Sep 11 07:22:36 AM UTC 24 |
Sep 11 07:22:48 AM UTC 24 |
2012969473 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all.3245148226 |
|
|
Sep 11 06:30:48 AM UTC 24 |
Sep 11 07:22:57 AM UTC 24 |
50218490209 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.122784868 |
|
|
Sep 11 07:11:22 AM UTC 24 |
Sep 11 07:23:13 AM UTC 24 |
50961125539 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.3039790243 |
|
|
Sep 11 07:19:36 AM UTC 24 |
Sep 11 07:23:29 AM UTC 24 |
2825495095 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.1491173081 |
|
|
Sep 11 07:18:14 AM UTC 24 |
Sep 11 07:23:37 AM UTC 24 |
70719170083 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access.3188556887 |
|
|
Sep 11 07:23:14 AM UTC 24 |
Sep 11 07:23:46 AM UTC 24 |
3399216093 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all.3439088410 |
|
|
Sep 11 06:32:43 AM UTC 24 |
Sep 11 07:23:53 AM UTC 24 |
56366861707 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.3381315356 |
|
|
Sep 11 07:23:46 AM UTC 24 |
Sep 11 07:24:00 AM UTC 24 |
7692560126 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.1812770619 |
|
|
Sep 11 07:18:48 AM UTC 24 |
Sep 11 07:24:28 AM UTC 24 |
10507716650 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.137724260 |
|
|
Sep 11 07:12:38 AM UTC 24 |
Sep 11 07:24:47 AM UTC 24 |
10377141893 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.1574535063 |
|
|
Sep 11 07:21:44 AM UTC 24 |
Sep 11 07:25:00 AM UTC 24 |
20780376351 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.1791445472 |
|
|
Sep 11 07:20:30 AM UTC 24 |
Sep 11 07:25:02 AM UTC 24 |
21207181249 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.1320494188 |
|
|
Sep 11 07:23:54 AM UTC 24 |
Sep 11 07:25:04 AM UTC 24 |
39552103762 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.3957493489 |
|
|
Sep 11 07:25:01 AM UTC 24 |
Sep 11 07:25:07 AM UTC 24 |
1351963803 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.3457883091 |
|
|
Sep 11 07:24:01 AM UTC 24 |
Sep 11 07:25:29 AM UTC 24 |
4201602159 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.1306027354 |
|
|
Sep 11 07:25:08 AM UTC 24 |
Sep 11 07:25:29 AM UTC 24 |
970287915 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.1690920545 |
|
|
Sep 11 07:23:37 AM UTC 24 |
Sep 11 07:25:30 AM UTC 24 |
870553313 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_alert_test.1814254241 |
|
|
Sep 11 07:25:31 AM UTC 24 |
Sep 11 07:25:33 AM UTC 24 |
22741395 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.321024802 |
|
|
Sep 11 07:20:10 AM UTC 24 |
Sep 11 07:25:45 AM UTC 24 |
15886513142 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_smoke.762047987 |
|
|
Sep 11 07:25:31 AM UTC 24 |
Sep 11 07:25:53 AM UTC 24 |
3663542041 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_executable.1743229450 |
|
|
Sep 11 07:12:38 AM UTC 24 |
Sep 11 07:26:18 AM UTC 24 |
41089330719 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_regwen.2025780678 |
|
|
Sep 11 07:24:48 AM UTC 24 |
Sep 11 07:26:23 AM UTC 24 |
884345121 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.444876580 |
|
|
Sep 11 07:22:04 AM UTC 24 |
Sep 11 07:26:37 AM UTC 24 |
3141130561 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_executable.1480298112 |
|
|
Sep 11 07:18:33 AM UTC 24 |
Sep 11 07:26:41 AM UTC 24 |
9311519142 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.2806751546 |
|
|
Sep 11 07:25:05 AM UTC 24 |
Sep 11 07:26:42 AM UTC 24 |
4651298127 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.2774024494 |
|
|
Sep 11 07:26:42 AM UTC 24 |
Sep 11 07:26:56 AM UTC 24 |
2748431560 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.737944458 |
|
|
Sep 11 07:21:07 AM UTC 24 |
Sep 11 07:27:16 AM UTC 24 |
21551663730 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access.613564729 |
|
|
Sep 11 07:26:19 AM UTC 24 |
Sep 11 07:27:35 AM UTC 24 |
825485706 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.2948749477 |
|
|
Sep 11 07:18:13 AM UTC 24 |
Sep 11 07:27:38 AM UTC 24 |
5921391575 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.1884360345 |
|
|
Sep 11 07:27:39 AM UTC 24 |
Sep 11 07:27:45 AM UTC 24 |
723984033 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.576519276 |
|
|
Sep 11 07:26:38 AM UTC 24 |
Sep 11 07:27:48 AM UTC 24 |
1560283579 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.1432697787 |
|
|
Sep 11 07:18:20 AM UTC 24 |
Sep 11 07:28:06 AM UTC 24 |
20250472695 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_bijection.3569496857 |
|
|
Sep 11 06:52:32 AM UTC 24 |
Sep 11 07:28:41 AM UTC 24 |
98220256473 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.52841927 |
|
|
Sep 11 07:26:43 AM UTC 24 |
Sep 11 07:28:52 AM UTC 24 |
11487252881 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_alert_test.1677460324 |
|
|
Sep 11 07:28:54 AM UTC 24 |
Sep 11 07:28:55 AM UTC 24 |
13559067 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.3771430896 |
|
|
Sep 11 07:22:58 AM UTC 24 |
Sep 11 07:29:17 AM UTC 24 |
23888964358 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_smoke.3160407203 |
|
|
Sep 11 07:28:57 AM UTC 24 |
Sep 11 07:29:24 AM UTC 24 |
4545719447 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.2022395346 |
|
|
Sep 11 07:25:54 AM UTC 24 |
Sep 11 07:29:30 AM UTC 24 |
3118633214 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_executable.3305172593 |
|
|
Sep 11 07:20:46 AM UTC 24 |
Sep 11 07:29:50 AM UTC 24 |
17376601007 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_regwen.4009264707 |
|
|
Sep 11 07:15:21 AM UTC 24 |
Sep 11 07:30:03 AM UTC 24 |
2464102166 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access.2492552344 |
|
|
Sep 11 07:29:50 AM UTC 24 |
Sep 11 07:30:15 AM UTC 24 |
7369975451 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.183784754 |
|
|
Sep 11 07:26:24 AM UTC 24 |
Sep 11 07:30:22 AM UTC 24 |
24491863973 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1860922938 |
|
|
Sep 11 07:28:07 AM UTC 24 |
Sep 11 07:30:24 AM UTC 24 |
8271739222 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.2506184327 |
|
|
Sep 11 07:25:03 AM UTC 24 |
Sep 11 07:30:25 AM UTC 24 |
8208982214 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.2492005970 |
|
|
Sep 11 07:30:23 AM UTC 24 |
Sep 11 07:30:38 AM UTC 24 |
1128155776 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.3412654978 |
|
|
Sep 11 07:27:46 AM UTC 24 |
Sep 11 07:30:53 AM UTC 24 |
5264461241 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_executable.3021688234 |
|
|
Sep 11 07:10:07 AM UTC 24 |
Sep 11 07:31:11 AM UTC 24 |
46756932373 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.479058089 |
|
|
Sep 11 07:13:29 AM UTC 24 |
Sep 11 07:31:11 AM UTC 24 |
23073547605 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.1355914439 |
|
|
Sep 11 07:27:48 AM UTC 24 |
Sep 11 07:31:15 AM UTC 24 |
22264580186 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.3840614479 |
|
|
Sep 11 07:31:11 AM UTC 24 |
Sep 11 07:31:17 AM UTC 24 |
696077717 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.1234826065 |
|
|
Sep 11 07:30:16 AM UTC 24 |
Sep 11 07:31:30 AM UTC 24 |
1518953798 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.2263742511 |
|
|
Sep 11 07:23:30 AM UTC 24 |
Sep 11 07:31:42 AM UTC 24 |
69524533260 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_alert_test.2968039338 |
|
|
Sep 11 07:31:43 AM UTC 24 |
Sep 11 07:31:45 AM UTC 24 |
61602562 ps |
| T45 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3973108162 |
|
|
Sep 11 07:31:18 AM UTC 24 |
Sep 11 07:31:57 AM UTC 24 |
2447928151 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.817837357 |
|
|
Sep 11 06:22:57 AM UTC 24 |
Sep 11 07:32:15 AM UTC 24 |
494315081163 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_bijection.793222727 |
|
|
Sep 11 07:16:22 AM UTC 24 |
Sep 11 07:32:19 AM UTC 24 |
13449729788 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_executable.484036855 |
|
|
Sep 11 07:15:20 AM UTC 24 |
Sep 11 07:32:24 AM UTC 24 |
6477338387 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all.2150682813 |
|
|
Sep 11 06:59:12 AM UTC 24 |
Sep 11 07:32:30 AM UTC 24 |
19149788581 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_regwen.1412386262 |
|
|
Sep 11 07:12:39 AM UTC 24 |
Sep 11 07:32:44 AM UTC 24 |
14351101881 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.239124630 |
|
|
Sep 11 07:30:25 AM UTC 24 |
Sep 11 07:32:46 AM UTC 24 |
70362665986 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access.3440130486 |
|
|
Sep 11 07:32:26 AM UTC 24 |
Sep 11 07:32:52 AM UTC 24 |
1669456089 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_smoke.2811293207 |
|
|
Sep 11 07:31:46 AM UTC 24 |
Sep 11 07:32:54 AM UTC 24 |
1530617853 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.2603805769 |
|
|
Sep 11 07:32:45 AM UTC 24 |
Sep 11 07:33:23 AM UTC 24 |
4847707538 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.2395685632 |
|
|
Sep 11 07:17:06 AM UTC 24 |
Sep 11 07:33:29 AM UTC 24 |
27614593987 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.3818574587 |
|
|
Sep 11 07:32:53 AM UTC 24 |
Sep 11 07:33:37 AM UTC 24 |
3817192925 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all.3675760340 |
|
|
Sep 11 06:34:46 AM UTC 24 |
Sep 11 07:33:39 AM UTC 24 |
135317480640 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.3923869127 |
|
|
Sep 11 07:33:38 AM UTC 24 |
Sep 11 07:33:43 AM UTC 24 |
352621399 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all.1000692258 |
|
|
Sep 11 06:53:31 AM UTC 24 |
Sep 11 07:33:55 AM UTC 24 |
120182252959 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.2722710566 |
|
|
Sep 11 07:32:47 AM UTC 24 |
Sep 11 07:34:11 AM UTC 24 |
1589558821 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all.2839285984 |
|
|
Sep 11 07:19:05 AM UTC 24 |
Sep 11 07:34:16 AM UTC 24 |
133463988997 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_alert_test.2533526350 |
|
|
Sep 11 07:34:17 AM UTC 24 |
Sep 11 07:34:19 AM UTC 24 |
14374921 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_smoke.3924527633 |
|
|
Sep 11 07:34:20 AM UTC 24 |
Sep 11 07:34:38 AM UTC 24 |
2108681355 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.100408828 |
|
|
Sep 11 07:31:16 AM UTC 24 |
Sep 11 07:34:39 AM UTC 24 |
4561428993 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all.3829262410 |
|
|
Sep 11 06:45:54 AM UTC 24 |
Sep 11 07:34:44 AM UTC 24 |
83726087411 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.323330482 |
|
|
Sep 11 07:29:30 AM UTC 24 |
Sep 11 07:34:51 AM UTC 24 |
15139968225 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.3273645135 |
|
|
Sep 11 07:22:38 AM UTC 24 |
Sep 11 07:35:00 AM UTC 24 |
10820494678 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access.1507676003 |
|
|
Sep 11 07:34:52 AM UTC 24 |
Sep 11 07:35:02 AM UTC 24 |
1492819090 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.3539064004 |
|
|
Sep 11 07:33:44 AM UTC 24 |
Sep 11 07:35:18 AM UTC 24 |
5589175426 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_executable.393740487 |
|
|
Sep 11 07:33:23 AM UTC 24 |
Sep 11 07:35:26 AM UTC 24 |
4039200722 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_regwen.2171928178 |
|
|
Sep 11 07:17:28 AM UTC 24 |
Sep 11 07:35:39 AM UTC 24 |
147986905182 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.3302181102 |
|
|
Sep 11 07:35:03 AM UTC 24 |
Sep 11 07:35:51 AM UTC 24 |
1480086424 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.667617321 |
|
|
Sep 11 07:33:56 AM UTC 24 |
Sep 11 07:35:52 AM UTC 24 |
1520170226 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.3349342615 |
|
|
Sep 11 07:30:04 AM UTC 24 |
Sep 11 07:35:54 AM UTC 24 |
27857946075 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.1295880608 |
|
|
Sep 11 07:35:27 AM UTC 24 |
Sep 11 07:35:56 AM UTC 24 |
9547763225 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.1927277795 |
|
|
Sep 11 07:35:55 AM UTC 24 |
Sep 11 07:36:01 AM UTC 24 |
357854729 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_bijection.952419942 |
|
|
Sep 11 07:02:06 AM UTC 24 |
Sep 11 07:36:04 AM UTC 24 |
282722104701 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_bijection.1230707826 |
|
|
Sep 11 07:19:31 AM UTC 24 |
Sep 11 07:36:23 AM UTC 24 |
26898954989 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.1243939173 |
|
|
Sep 11 07:31:12 AM UTC 24 |
Sep 11 07:36:26 AM UTC 24 |
27679985671 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_bijection.1119745599 |
|
|
Sep 11 07:11:46 AM UTC 24 |
Sep 11 07:36:28 AM UTC 24 |
76110632059 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_alert_test.1701146311 |
|
|
Sep 11 07:36:27 AM UTC 24 |
Sep 11 07:36:29 AM UTC 24 |
14397753 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.2573514233 |
|
|
Sep 11 07:32:19 AM UTC 24 |
Sep 11 07:36:39 AM UTC 24 |
6817269643 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_smoke.3866607296 |
|
|
Sep 11 07:36:28 AM UTC 24 |
Sep 11 07:36:39 AM UTC 24 |
746145130 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.2245059502 |
|
|
Sep 11 07:35:19 AM UTC 24 |
Sep 11 07:36:46 AM UTC 24 |
801157497 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3458920186 |
|
|
Sep 11 07:36:05 AM UTC 24 |
Sep 11 07:37:03 AM UTC 24 |
6139486743 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access.1342579308 |
|
|
Sep 11 07:36:47 AM UTC 24 |
Sep 11 07:37:14 AM UTC 24 |
3653654800 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_regwen.1254299554 |
|
|
Sep 11 07:27:36 AM UTC 24 |
Sep 11 07:37:25 AM UTC 24 |
3069332699 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.3015595459 |
|
|
Sep 11 07:33:40 AM UTC 24 |
Sep 11 07:37:27 AM UTC 24 |
21177774062 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.2150244018 |
|
|
Sep 11 07:36:01 AM UTC 24 |
Sep 11 07:37:35 AM UTC 24 |
10936035091 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.3200175694 |
|
|
Sep 11 07:29:18 AM UTC 24 |
Sep 11 07:37:39 AM UTC 24 |
15123526883 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.4151393051 |
|
|
Sep 11 07:37:26 AM UTC 24 |
Sep 11 07:37:44 AM UTC 24 |
722988203 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_regwen.1328647935 |
|
|
Sep 11 07:20:47 AM UTC 24 |
Sep 11 07:37:45 AM UTC 24 |
12983707841 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.2981817631 |
|
|
Sep 11 07:37:46 AM UTC 24 |
Sep 11 07:37:52 AM UTC 24 |
1407875001 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.3352281180 |
|
|
Sep 11 07:37:15 AM UTC 24 |
Sep 11 07:38:01 AM UTC 24 |
2529057298 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_bijection.3993966302 |
|
|
Sep 11 07:09:00 AM UTC 24 |
Sep 11 07:38:07 AM UTC 24 |
180157024117 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.1672272723 |
|
|
Sep 11 07:32:31 AM UTC 24 |
Sep 11 07:38:12 AM UTC 24 |
25363954075 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.43493295 |
|
|
Sep 11 07:37:27 AM UTC 24 |
Sep 11 07:38:21 AM UTC 24 |
20759085766 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_alert_test.2507559622 |
|
|
Sep 11 07:38:22 AM UTC 24 |
Sep 11 07:38:24 AM UTC 24 |
42991550 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_bijection.818149938 |
|
|
Sep 11 06:53:43 AM UTC 24 |
Sep 11 07:38:26 AM UTC 24 |
782289215316 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.779139311 |
|
|
Sep 11 07:38:08 AM UTC 24 |
Sep 11 07:38:32 AM UTC 24 |
804237427 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_smoke.21234425 |
|
|
Sep 11 07:38:25 AM UTC 24 |
Sep 11 07:38:41 AM UTC 24 |
536938793 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.56794718 |
|
|
Sep 11 07:35:57 AM UTC 24 |
Sep 11 07:38:53 AM UTC 24 |
9743304220 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access.222791824 |
|
|
Sep 11 07:38:54 AM UTC 24 |
Sep 11 07:39:24 AM UTC 24 |
2623398072 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_bijection.3968846526 |
|
|
Sep 11 07:13:30 AM UTC 24 |
Sep 11 07:39:43 AM UTC 24 |
67272794970 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_regwen.1656061185 |
|
|
Sep 11 07:30:54 AM UTC 24 |
Sep 11 07:39:56 AM UTC 24 |
26985763973 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.3824768256 |
|
|
Sep 11 07:39:44 AM UTC 24 |
Sep 11 07:40:00 AM UTC 24 |
2794738502 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.4057265985 |
|
|
Sep 11 07:36:40 AM UTC 24 |
Sep 11 07:40:04 AM UTC 24 |
41983649931 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.387834722 |
|
|
Sep 11 07:34:45 AM UTC 24 |
Sep 11 07:40:14 AM UTC 24 |
4286438298 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_executable.4070556357 |
|
|
Sep 11 07:24:29 AM UTC 24 |
Sep 11 07:40:30 AM UTC 24 |
96206198369 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.407741214 |
|
|
Sep 11 07:39:57 AM UTC 24 |
Sep 11 07:40:37 AM UTC 24 |
1024289632 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.2258214399 |
|
|
Sep 11 07:40:38 AM UTC 24 |
Sep 11 07:40:44 AM UTC 24 |
1409922551 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.2164113474 |
|
|
Sep 11 07:37:35 AM UTC 24 |
Sep 11 07:40:59 AM UTC 24 |
10184550781 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.1387254720 |
|
|
Sep 11 07:38:02 AM UTC 24 |
Sep 11 07:41:14 AM UTC 24 |
10118186480 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all.2981032868 |
|
|
Sep 11 06:43:20 AM UTC 24 |
Sep 11 07:41:21 AM UTC 24 |
163018351123 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_regwen.1507219111 |
|
|
Sep 11 07:37:46 AM UTC 24 |
Sep 11 07:41:22 AM UTC 24 |
16341546663 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_alert_test.2150967826 |
|
|
Sep 11 07:41:23 AM UTC 24 |
Sep 11 07:41:24 AM UTC 24 |
16454895 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all.1266617500 |
|
|
Sep 11 06:36:02 AM UTC 24 |
Sep 11 07:41:27 AM UTC 24 |
446223919372 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_bijection.3129345748 |
|
|
Sep 11 07:18:14 AM UTC 24 |
Sep 11 07:41:31 AM UTC 24 |
89754962432 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_smoke.2125876822 |
|
|
Sep 11 07:41:25 AM UTC 24 |
Sep 11 07:41:43 AM UTC 24 |
813987670 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_regwen.487630112 |
|
|
Sep 11 07:18:33 AM UTC 24 |
Sep 11 07:42:00 AM UTC 24 |
22415563048 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.1216449977 |
|
|
Sep 11 07:26:58 AM UTC 24 |
Sep 11 07:42:04 AM UTC 24 |
13327014166 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3977815181 |
|
|
Sep 11 07:41:14 AM UTC 24 |
Sep 11 07:42:08 AM UTC 24 |
1324563104 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access.2733066177 |
|
|
Sep 11 07:42:01 AM UTC 24 |
Sep 11 07:42:12 AM UTC 24 |
474481192 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.332206200 |
|
|
Sep 11 07:42:09 AM UTC 24 |
Sep 11 07:42:24 AM UTC 24 |
1361999415 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.3329014876 |
|
|
Sep 11 07:40:01 AM UTC 24 |
Sep 11 07:42:29 AM UTC 24 |
127094736216 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.3668460612 |
|
|
Sep 11 07:41:00 AM UTC 24 |
Sep 11 07:42:31 AM UTC 24 |
6960586007 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.928814779 |
|
|
Sep 11 07:42:13 AM UTC 24 |
Sep 11 07:42:32 AM UTC 24 |
3139457617 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.2090280088 |
|
|
Sep 11 07:30:26 AM UTC 24 |
Sep 11 07:42:48 AM UTC 24 |
47114516874 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.509656466 |
|
|
Sep 11 07:42:25 AM UTC 24 |
Sep 11 07:42:54 AM UTC 24 |
4377848221 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.241149969 |
|
|
Sep 11 07:42:49 AM UTC 24 |
Sep 11 07:42:56 AM UTC 24 |
545151869 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.2543513063 |
|
|
Sep 11 07:37:53 AM UTC 24 |
Sep 11 07:43:05 AM UTC 24 |
56296058529 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.385071498 |
|
|
Sep 11 07:34:40 AM UTC 24 |
Sep 11 07:43:23 AM UTC 24 |
19194879483 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all.2166827571 |
|
|
Sep 11 06:49:58 AM UTC 24 |
Sep 11 07:43:25 AM UTC 24 |
216010237544 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.2302297534 |
|
|
Sep 11 07:35:01 AM UTC 24 |
Sep 11 07:43:26 AM UTC 24 |
10531531129 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_alert_test.3218410580 |
|
|
Sep 11 07:43:26 AM UTC 24 |
Sep 11 07:43:28 AM UTC 24 |
42016019 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.1187231468 |
|
|
Sep 11 07:18:31 AM UTC 24 |
Sep 11 07:43:29 AM UTC 24 |
18992138872 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all.1492648566 |
|
|
Sep 11 07:08:37 AM UTC 24 |
Sep 11 07:43:36 AM UTC 24 |
41702543706 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.2889909822 |
|
|
Sep 11 07:40:05 AM UTC 24 |
Sep 11 07:43:39 AM UTC 24 |
30017588677 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_smoke.2337438445 |
|
|
Sep 11 07:43:27 AM UTC 24 |
Sep 11 07:43:42 AM UTC 24 |
4271701746 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access.2344708264 |
|
|
Sep 11 07:43:40 AM UTC 24 |
Sep 11 07:43:58 AM UTC 24 |
1550373072 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.2062943782 |
|
|
Sep 11 07:19:31 AM UTC 24 |
Sep 11 07:44:00 AM UTC 24 |
104627647627 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1945576399 |
|
|
Sep 11 07:43:06 AM UTC 24 |
Sep 11 07:44:27 AM UTC 24 |
3097265012 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.683110934 |
|
|
Sep 11 07:39:25 AM UTC 24 |
Sep 11 07:44:33 AM UTC 24 |
11986945490 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.1342717003 |
|
|
Sep 11 07:38:43 AM UTC 24 |
Sep 11 07:44:49 AM UTC 24 |
26802158278 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.1986383926 |
|
|
Sep 11 07:44:00 AM UTC 24 |
Sep 11 07:44:58 AM UTC 24 |
1498724542 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_executable.4165160228 |
|
|
Sep 11 07:30:39 AM UTC 24 |
Sep 11 07:44:59 AM UTC 24 |
9791122497 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.4030332444 |
|
|
Sep 11 07:45:00 AM UTC 24 |
Sep 11 07:45:05 AM UTC 24 |
693358930 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.1774074334 |
|
|
Sep 11 07:44:28 AM UTC 24 |
Sep 11 07:45:11 AM UTC 24 |
5804484825 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_executable.363518215 |
|
|
Sep 11 07:35:52 AM UTC 24 |
Sep 11 07:45:18 AM UTC 24 |
10087129566 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all.2340784441 |
|
|
Sep 11 06:19:59 AM UTC 24 |
Sep 11 07:45:30 AM UTC 24 |
125594399713 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.1938124622 |
|
|
Sep 11 07:43:29 AM UTC 24 |
Sep 11 07:45:33 AM UTC 24 |
14952891611 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_alert_test.2799245689 |
|
|
Sep 11 07:45:34 AM UTC 24 |
Sep 11 07:45:36 AM UTC 24 |
20263819 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.905301819 |
|
|
Sep 11 07:42:56 AM UTC 24 |
Sep 11 07:45:50 AM UTC 24 |
10191306001 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_smoke.1958856707 |
|
|
Sep 11 07:45:37 AM UTC 24 |
Sep 11 07:45:58 AM UTC 24 |
1052059109 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.1823745488 |
|
|
Sep 11 07:44:01 AM UTC 24 |
Sep 11 07:46:04 AM UTC 24 |
1599363411 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.2975283506 |
|
|
Sep 11 07:40:45 AM UTC 24 |
Sep 11 07:46:23 AM UTC 24 |
8756809182 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.1228558459 |
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|
Sep 11 07:43:36 AM UTC 24 |
Sep 11 07:46:30 AM UTC 24 |
18124556263 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_executable.1200165127 |
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|
Sep 11 07:37:40 AM UTC 24 |
Sep 11 07:46:36 AM UTC 24 |
12641004718 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.199168793 |
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|
Sep 11 07:37:04 AM UTC 24 |
Sep 11 07:46:40 AM UTC 24 |
363095168193 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_regwen.590865429 |
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|
Sep 11 07:40:31 AM UTC 24 |
Sep 11 07:46:46 AM UTC 24 |
6568189129 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.4050105791 |
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|
Sep 11 07:45:12 AM UTC 24 |
Sep 11 07:46:55 AM UTC 24 |
2727333926 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all.3128991473 |
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|
Sep 11 06:55:02 AM UTC 24 |
Sep 11 07:47:10 AM UTC 24 |
975820224705 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.2829075670 |
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|
Sep 11 07:32:55 AM UTC 24 |
Sep 11 07:47:12 AM UTC 24 |
14479869514 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.3372728619 |
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|
Sep 11 07:46:37 AM UTC 24 |
Sep 11 07:47:18 AM UTC 24 |
6636079788 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.3379391508 |
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|
Sep 11 07:41:44 AM UTC 24 |
Sep 11 07:47:23 AM UTC 24 |
47890366806 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.278173132 |
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|
Sep 11 07:47:18 AM UTC 24 |
Sep 11 07:47:25 AM UTC 24 |
1347615938 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2050974929 |
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Sep 11 07:45:19 AM UTC 24 |
Sep 11 07:47:34 AM UTC 24 |
5593153675 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.245943430 |
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Sep 11 07:38:27 AM UTC 24 |
Sep 11 07:47:50 AM UTC 24 |
29478701891 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.1244186209 |
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|
Sep 11 07:46:41 AM UTC 24 |
Sep 11 07:47:52 AM UTC 24 |
826284009 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.3028927807 |
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Sep 11 07:46:47 AM UTC 24 |
Sep 11 07:47:53 AM UTC 24 |
18829794118 ps |