Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16468801

1

T3

87

T4

700

T5

2390

full_word

174001112

1

T3

926

T4

6882

T5

531

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	190469603	1			T3	1013		T4	7582		T5	2921
auto[TlIntgErrCmd]	101	1			T61	6		T62	6		T63	4
auto[TlIntgErrData]	122	1			T61	9		T62	9		T63	1
auto[TlIntgErrBoth]	87	1			T61	5		T62	5		T63	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

92283664

1

T3

511

T4

3831

T5

1459

auto[1]

98186249

1

T3

502

T4

3751

T5

1462

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8055633	1			T3	46		T4	342		T5	1208
auto[TlIntgErrNone]	partial	auto[1]	8412883	1			T3	41		T4	358		T5	1182
auto[TlIntgErrNone]	full_word	auto[0]	84227885	1			T3	465		T4	3489		T5	251
auto[TlIntgErrNone]	full_word	auto[1]	89773202	1			T3	461		T4	3393		T5	280
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T61	3		T63	2		T126	1
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T61	2		T62	4		T63	2
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T61	1		T62	2		T126	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T127	1		T128	1		T129	1
auto[TlIntgErrData]	partial	auto[0]	56	1			T61	5		T62	3		T126	2
auto[TlIntgErrData]	partial	auto[1]	53	1			T61	4		T62	5		T126	6
auto[TlIntgErrData]	full_word	auto[0]	8	1			T63	1		T126	1		T127	2
auto[TlIntgErrData]	full_word	auto[1]	5	1			T62	1		T126	1		T130	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1			T61	2		T62	3		T63	2
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T61	3		T62	2		T63	3
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T131	1		T132	1		-	-