Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	981261	1			T32	516		T10	30		T11	1
auto[1]	10665290	1			T4	11		T8	1337		T12	1467
auto[2]	758762	1			T32	318		T10	20		T11	1
auto[3]	10349217	1			T4	10		T8	1337		T12	1530

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14622548	1			T4	20		T8	2674		T12	85
auto[1]	2105498	1			T12	475		T29	390		T31	566
auto[2]	2144703	1			T4	1		T12	476		T29	399
auto[3]	3881781	1			T12	1961		T29	87		T31	49

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9396677

1

T4

21

T8

2674

T12

2997

auto[1]

13357853

1

T29

1

T59

1

T60

2

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	384719	1			T32	432		T10	29		T150	10
auto[0]	auto[0]	auto[1]	39444	1			T32	36		T10	1		T11	1
auto[0]	auto[0]	auto[2]	39081	1			T32	43		T81	7		T150	37
auto[0]	auto[0]	auto[3]	46827	1			T32	5		T81	852		T150	139
auto[0]	auto[1]	auto[0]	3347054	1			T4	10		T8	1337		T12	35
auto[0]	auto[1]	auto[1]	353996	1			T12	227		T29	186		T31	275
auto[0]	auto[1]	auto[2]	360517	1			T4	1		T12	228		T29	195
auto[0]	auto[1]	auto[3]	308417	1			T12	977		T29	48		T31	21
auto[0]	auto[2]	auto[0]	278233	1			T32	256		T10	18		T150	6
auto[0]	auto[2]	auto[1]	30360	1			T32	20		T150	23		T20	2
auto[0]	auto[2]	auto[2]	30945	1			T32	38		T10	2		T11	1
auto[0]	auto[2]	auto[3]	33966	1			T32	4		T81	570		T150	126
auto[0]	auto[3]	auto[0]	3167053	1			T4	10		T8	1337		T12	50
auto[0]	auto[3]	auto[1]	338782	1			T12	248		T29	204		T31	291
auto[0]	auto[3]	auto[2]	356128	1			T12	248		T29	204		T31	291
auto[0]	auto[3]	auto[3]	281155	1			T12	984		T29	38		T31	28
auto[1]	auto[0]	auto[0]	15567	1			T113	124		T116	754		T149	414
auto[1]	auto[0]	auto[1]	69989	1			T113	505		T116	3487		T149	1904
auto[1]	auto[0]	auto[2]	70467	1			T113	496		T116	3324		T149	1931
auto[1]	auto[0]	auto[3]	315167	1			T113	2228		T116	15356		T149	8684
auto[1]	auto[1]	auto[0]	3713751	1			T59	1		T106	68282		T113	217
auto[1]	auto[1]	auto[1]	636550	1			T106	6660		T113	1485		T114	4461
auto[1]	auto[1]	auto[2]	603412	1			T106	6873		T113	860		T114	4882
auto[1]	auto[1]	auto[3]	1341593	1			T60	1		T106	700		T113	6536
auto[1]	auto[2]	auto[0]	11479	1			T116	667		T149	256		T151	903
auto[1]	auto[2]	auto[1]	51590	1			T116	3175		T149	1127		T151	4044
auto[1]	auto[2]	auto[2]	58798	1			T113	406		T116	2942		T149	1804
auto[1]	auto[2]	auto[3]	263391	1			T113	2031		T116	12994		T149	8232
auto[1]	auto[3]	auto[0]	3704692	1			T106	67743		T113	90		T114	1065
auto[1]	auto[3]	auto[1]	584787	1			T106	6711		T113	390		T114	5033
auto[1]	auto[3]	auto[2]	625355	1			T106	6731		T113	1416		T114	4540
auto[1]	auto[3]	auto[3]	1291265	1			T29	1		T60	1		T106	690