SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_reg_regs.u_chk.u_chk | 100.00 | 100.00 | |||||
tb.dut.u_tlul_adapter_sram.gen_cmd_intg_check.u_cmd_intg_chk.u_chk | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_chk |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_cmd_intg_check.u_cmd_intg_chk |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Covered | Percent | |
---|---|---|---|
Totals | 4 | 4 | 100.00 |
Total Bits | 232 | 232 | 100.00 |
Total Bits 0->1 | 116 | 116 | 100.00 |
Total Bits 1->0 | 116 | 116 | 100.00 |
Ports | 4 | 4 | 100.00 |
Port Bits | 232 | 232 | 100.00 |
Port Bits 0->1 | 116 | 116 | 100.00 |
Port Bits 1->0 | 116 | 116 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[42:0] | Yes | Yes | *T1,*T3,*T4 | Yes | T1,T3,T4 | INPUT |
data_i[56:43] | Unreachable | Unreachable | Unreachable | INPUT | ||
data_i[63:57] | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | INPUT |
data_o[56:0] | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | OUTPUT |
syndrome_o[6:0] | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | OUTPUT |
err_o[1:0] | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 4 | 4 | 100.00 |
Total Bits | 232 | 232 | 100.00 |
Total Bits 0->1 | 116 | 116 | 100.00 |
Total Bits 1->0 | 116 | 116 | 100.00 |
Ports | 4 | 4 | 100.00 |
Port Bits | 232 | 232 | 100.00 |
Port Bits 0->1 | 116 | 116 | 100.00 |
Port Bits 1->0 | 116 | 116 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[42:0] | Yes | Yes | *T1,T21,*T17 | Yes | T1,T21,T17 | INPUT |
data_i[56:43] | Unreachable | Unreachable | Unreachable | INPUT | ||
data_i[63:57] | Yes | Yes | T1,T21,T22 | Yes | T1,T14,T12 | INPUT |
data_o[56:0] | Yes | Yes | T1,T21,T17 | Yes | T1,T21,T17 | OUTPUT |
syndrome_o[6:0] | Yes | Yes | T1,T24,T43 | Yes | T1,T24,T43 | OUTPUT |
err_o[1:0] | Yes | Yes | T1,T24,T43 | Yes | T1,T43,T83 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 4 | 4 | 100.00 |
Total Bits | 232 | 232 | 100.00 |
Total Bits 0->1 | 116 | 116 | 100.00 |
Total Bits 1->0 | 116 | 116 | 100.00 |
Ports | 4 | 4 | 100.00 |
Port Bits | 232 | 232 | 100.00 |
Port Bits 0->1 | 116 | 116 | 100.00 |
Port Bits 1->0 | 116 | 116 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[42:0] | Yes | Yes | *T3,*T4,*T5 | Yes | T3,T4,T5 | INPUT |
data_i[56:43] | Unreachable | Unreachable | Unreachable | INPUT | ||
data_i[63:57] | Yes | Yes | T3,T4,T5 | Yes | T3,T4,T5 | INPUT |
data_o[56:0] | Yes | Yes | T3,T4,T5 | Yes | T3,T4,T5 | OUTPUT |
syndrome_o[6:0] | Yes | Yes | T3,T4,T6 | Yes | T1,T3,T4 | OUTPUT |
err_o[1:0] | Yes | Yes | T3,T4,T5 | Yes | T3,T4,T6 | OUTPUT |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |