Unified Coverage Report :: Module :: prim_prince

Module : prim_prince

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_prince.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_ram_1p_scr.gen_par_scr[0].u_prim_prince	100.00			100.00

---

Module Instance : tb.dut.u_prim_ram_1p_scr.gen_par_scr[0].u_prim_prince

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.53	98.11	100.00			100.00	100.00	u_prim_ram_1p_scr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : prim_prince

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	520	520	100.00
Total Bits 0->1	260	260	100.00
Total Bits 1->0	260	260	100.00

Ports	7	7	100.00
Port Bits	520	520	100.00
Port Bits 0->1	260	260	100.00
Port Bits 1->0	260	260	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T6,T21	Yes	T1,T2,T3	INPUT
valid_i	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
data_i[63:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
key_i[127:0]	Yes	Yes	T4,T8,T29	Yes	T29,T21,T23	INPUT
dec_i	Unreachable	Unreachable		Unreachable		INPUT
valid_o	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
data_o[63:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT