Unified Coverage Report :: Module :: prim_generic_ram_1p

Module : prim_generic_ram_1p

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_ram_1p_scr.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_prim_ram_1p_scr.u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_generic_ram_1p

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
ALWAYS	63	6	6	100.00

41                        logic unused_cfg;
42         1/1            assign unused_cfg = ^cfg_i;
           Tests:       T2 T13 T34 
43                      
44                        // Width of internal write mask. Note wmask_i input into the module is always assumed
45                        // to be the full bit mask
46                        localparam int MaskWidth = Width / DataBitsPerMask;
47                      
48                        logic [Width-1:0]     mem [Depth];
49                        logic [MaskWidth-1:0] wmask;
50                      
51                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
52         1/1              assign wmask[k] = &wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
           Tests:       T1 T2 T3 
53                      
54                          // Ensure that all mask bits within a group have the same value for a write
55                          `ASSERT(MaskCheck_A, req_i && write_i |->
56                              wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
57                              clk_i, '0)
58                        end
59                      
60                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
61                        // thrown when using $readmemh system task to backdoor load an image
62                        always @(posedge clk_i) begin
63         1/1              if (req_i) begin
           Tests:       T1 T2 T3 
64         1/1                if (write_i) begin
           Tests:       T2 T4 T5 
65         1/1                  for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T2 T4 T5 
66         1/1                    if (wmask[i]) begin
           Tests:       T2 T4 T5 
67         1/1                      mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T2 T4 T5 
68                                    wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                                end
                   ==>  MISSING_ELSE
70                              end
71                            end else begin
72         1/1                  rdata_o <= mem[addr_i];
           Tests:       T4 T5 T8 
73                            end
74                          end
                        MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1p

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

63             if (req_i) begin
               -1-  
64               if (write_i) begin
                 -2-  
65                 for (int i=0; i < MaskWidth; i = i + 1) begin
                   ==>
66                   if (wmask[i]) begin
67                     mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
68                       wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                   end
70                 end
71               end else begin
72                 rdata_o <= mem[addr_i];
                   ==>
73               end
74             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T4,T5
1	0	Covered	T4,T5,T8
0	-	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1p

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	905	905	0	0
gen_wmask[0].MaskCheck_A	1304269677	296449543	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304269677	296449543	0	0
T2	34149	32768	0	0
T3	16579	0	0	0
T4	49584	36519	0	0
T5	94743	66998	0	0
T6	8857	0	0	0
T8	69249	66874	0	0
T12	72512	67090	0	0
T13	34567	32768	0	0
T14	990	0	0	0
T29	69912	66909	0	0
T30	0	66288	0	0
T31	0	69204	0	0
T37	0	36109	0	0