Line Coverage for Module :
sram_ctrl_regs_reg_top
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 76 | 76 | 100.00 |
| ALWAYS | 68 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 90 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 119 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 174 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 426 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 496 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 523 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 551 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 613 | 1 | 1 | 100.00 |
| ALWAYS | 644 | 10 | 10 | 100.00 |
| CONT_ASSIGN | 656 | 1 | 1 | 100.00 |
| ALWAYS | 660 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 673 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 675 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 676 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 678 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 679 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 681 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 682 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 684 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 685 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 687 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 689 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 690 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 692 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 693 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 695 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 696 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 698 | 1 | 1 | 100.00 |
| ALWAYS | 702 | 10 | 10 | 100.00 |
| ALWAYS | 716 | 19 | 19 | 100.00 |
| CONT_ASSIGN | 773 | 0 | 0 | |
| CONT_ASSIGN | 781 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 782 | 1 | 1 | 100.00 |
67 always_ff @(posedge clk_i or negedge rst_ni) begin
68 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
69 1/1 err_q <= '0;
Tests: T1 T2 T3
70 1/1 end else if (intg_err || reg_we_err) begin
Tests: T1 T2 T3
71 1/1 err_q <= 1'b1;
Tests: T3 T6 T7
72 end
MISSING_ELSE
73 end
74
75 // integrity error output is permanent and should be used for alert generation
76 // register errors are transactional
77 1/1 assign intg_err_o = err_q | intg_err | reg_we_err;
Tests: T1 T2 T3
78
79 // outgoing integrity generation
80 tlul_pkg::tl_d2h_t tl_o_pre;
81 tlul_rsp_intg_gen #(
82 .EnableRspIntgGen(1),
83 .EnableDataIntgGen(1)
84 ) u_rsp_intg_gen (
85 .tl_i(tl_o_pre),
86 .tl_o(tl_o)
87 );
88
89 1/1 assign tl_reg_h2d = tl_i;
Tests: T1 T2 T3
90 1/1 assign tl_o_pre = tl_reg_d2h;
Tests: T1 T2 T3
91
92 tlul_adapter_reg #(
93 .RegAw(AW),
94 .RegDw(DW),
95 .EnableDataIntgGen(0)
96 ) u_reg_if (
97 .clk_i (clk_i),
98 .rst_ni (rst_ni),
99
100 .tl_i (tl_reg_h2d),
101 .tl_o (tl_reg_d2h),
102
103 .en_ifetch_i(prim_mubi_pkg::MuBi4False),
104 .intg_error_o(),
105
106 .we_o (reg_we),
107 .re_o (reg_re),
108 .addr_o (reg_addr),
109 .wdata_o (reg_wdata),
110 .be_o (reg_be),
111 .busy_i (reg_busy),
112 .rdata_i (reg_rdata),
113 .error_i (reg_error)
114 );
115
116 // cdc oversampling signals
117
118 1/1 assign reg_rdata = reg_rdata_next ;
Tests: T1 T2 T3
119 1/1 assign reg_error = addrmiss | wr_err | intg_err;
Tests: T21 T23 T25
120
121 // Define SW related signals
122 // Format: <reg>_<field>_{wd|we|qs}
123 // or <reg>_{wd|we|qs} if field == 1 or 0
124 logic alert_test_we;
125 logic alert_test_wd;
126 logic status_bus_integ_error_qs;
127 logic status_init_error_qs;
128 logic status_escalated_qs;
129 logic status_scr_key_valid_qs;
130 logic status_scr_key_seed_valid_qs;
131 logic status_init_done_qs;
132 logic status_readback_error_qs;
133 logic status_sram_alert_qs;
134 logic exec_regwen_we;
135 logic exec_regwen_qs;
136 logic exec_regwen_wd;
137 logic exec_we;
138 logic [3:0] exec_qs;
139 logic [3:0] exec_wd;
140 logic ctrl_regwen_we;
141 logic ctrl_regwen_qs;
142 logic ctrl_regwen_wd;
143 logic ctrl_we;
144 logic ctrl_renew_scr_key_wd;
145 logic ctrl_init_wd;
146 logic scr_key_rotated_we;
147 logic [3:0] scr_key_rotated_qs;
148 logic [3:0] scr_key_rotated_wd;
149 logic readback_regwen_we;
150 logic readback_regwen_qs;
151 logic readback_regwen_wd;
152 logic readback_we;
153 logic [3:0] readback_qs;
154 logic [3:0] readback_wd;
155
156 // Register instances
157 // R[alert_test]: V(True)
158 logic alert_test_qe;
159 logic [0:0] alert_test_flds_we;
160 1/1 assign alert_test_qe = &alert_test_flds_we;
Tests: T1 T14 T21
161 prim_subreg_ext #(
162 .DW (1)
163 ) u_alert_test (
164 .re (1'b0),
165 .we (alert_test_we),
166 .wd (alert_test_wd),
167 .d ('0),
168 .qre (),
169 .qe (alert_test_flds_we[0]),
170 .q (reg2hw.alert_test.q),
171 .ds (),
172 .qs ()
173 );
174 1/1 assign reg2hw.alert_test.qe = alert_test_qe;
Tests: T1 T14 T21
175
176
177 // R[status]: V(False)
178 // F[bus_integ_error]: 0:0
179 prim_subreg #(
180 .DW (1),
181 .SwAccess(prim_subreg_pkg::SwAccessRO),
182 .RESVAL (1'h0),
183 .Mubi (1'b0)
184 ) u_status_bus_integ_error (
185 .clk_i (clk_i),
186 .rst_ni (rst_ni),
187
188 // from register interface
189 .we (1'b0),
190 .wd ('0),
191
192 // from internal hardware
193 .de (hw2reg.status.bus_integ_error.de),
194 .d (hw2reg.status.bus_integ_error.d),
195
196 // to internal hardware
197 .qe (),
198 .q (reg2hw.status.bus_integ_error.q),
199 .ds (),
200
201 // to register interface (read)
202 .qs (status_bus_integ_error_qs)
203 );
204
205 // F[init_error]: 1:1
206 prim_subreg #(
207 .DW (1),
208 .SwAccess(prim_subreg_pkg::SwAccessRO),
209 .RESVAL (1'h0),
210 .Mubi (1'b0)
211 ) u_status_init_error (
212 .clk_i (clk_i),
213 .rst_ni (rst_ni),
214
215 // from register interface
216 .we (1'b0),
217 .wd ('0),
218
219 // from internal hardware
220 .de (hw2reg.status.init_error.de),
221 .d (hw2reg.status.init_error.d),
222
223 // to internal hardware
224 .qe (),
225 .q (reg2hw.status.init_error.q),
226 .ds (),
227
228 // to register interface (read)
229 .qs (status_init_error_qs)
230 );
231
232 // F[escalated]: 2:2
233 prim_subreg #(
234 .DW (1),
235 .SwAccess(prim_subreg_pkg::SwAccessRO),
236 .RESVAL (1'h0),
237 .Mubi (1'b0)
238 ) u_status_escalated (
239 .clk_i (clk_i),
240 .rst_ni (rst_ni),
241
242 // from register interface
243 .we (1'b0),
244 .wd ('0),
245
246 // from internal hardware
247 .de (hw2reg.status.escalated.de),
248 .d (hw2reg.status.escalated.d),
249
250 // to internal hardware
251 .qe (),
252 .q (reg2hw.status.escalated.q),
253 .ds (),
254
255 // to register interface (read)
256 .qs (status_escalated_qs)
257 );
258
259 // F[scr_key_valid]: 3:3
260 prim_subreg #(
261 .DW (1),
262 .SwAccess(prim_subreg_pkg::SwAccessRO),
263 .RESVAL (1'h0),
264 .Mubi (1'b0)
265 ) u_status_scr_key_valid (
266 .clk_i (clk_i),
267 .rst_ni (rst_ni),
268
269 // from register interface
270 .we (1'b0),
271 .wd ('0),
272
273 // from internal hardware
274 .de (hw2reg.status.scr_key_valid.de),
275 .d (hw2reg.status.scr_key_valid.d),
276
277 // to internal hardware
278 .qe (),
279 .q (),
280 .ds (),
281
282 // to register interface (read)
283 .qs (status_scr_key_valid_qs)
284 );
285
286 // F[scr_key_seed_valid]: 4:4
287 prim_subreg #(
288 .DW (1),
289 .SwAccess(prim_subreg_pkg::SwAccessRO),
290 .RESVAL (1'h0),
291 .Mubi (1'b0)
292 ) u_status_scr_key_seed_valid (
293 .clk_i (clk_i),
294 .rst_ni (rst_ni),
295
296 // from register interface
297 .we (1'b0),
298 .wd ('0),
299
300 // from internal hardware
301 .de (hw2reg.status.scr_key_seed_valid.de),
302 .d (hw2reg.status.scr_key_seed_valid.d),
303
304 // to internal hardware
305 .qe (),
306 .q (reg2hw.status.scr_key_seed_valid.q),
307 .ds (),
308
309 // to register interface (read)
310 .qs (status_scr_key_seed_valid_qs)
311 );
312
313 // F[init_done]: 5:5
314 prim_subreg #(
315 .DW (1),
316 .SwAccess(prim_subreg_pkg::SwAccessRO),
317 .RESVAL (1'h0),
318 .Mubi (1'b0)
319 ) u_status_init_done (
320 .clk_i (clk_i),
321 .rst_ni (rst_ni),
322
323 // from register interface
324 .we (1'b0),
325 .wd ('0),
326
327 // from internal hardware
328 .de (hw2reg.status.init_done.de),
329 .d (hw2reg.status.init_done.d),
330
331 // to internal hardware
332 .qe (),
333 .q (reg2hw.status.init_done.q),
334 .ds (),
335
336 // to register interface (read)
337 .qs (status_init_done_qs)
338 );
339
340 // F[readback_error]: 6:6
341 prim_subreg #(
342 .DW (1),
343 .SwAccess(prim_subreg_pkg::SwAccessRO),
344 .RESVAL (1'h0),
345 .Mubi (1'b0)
346 ) u_status_readback_error (
347 .clk_i (clk_i),
348 .rst_ni (rst_ni),
349
350 // from register interface
351 .we (1'b0),
352 .wd ('0),
353
354 // from internal hardware
355 .de (hw2reg.status.readback_error.de),
356 .d (hw2reg.status.readback_error.d),
357
358 // to internal hardware
359 .qe (),
360 .q (reg2hw.status.readback_error.q),
361 .ds (),
362
363 // to register interface (read)
364 .qs (status_readback_error_qs)
365 );
366
367 // F[sram_alert]: 7:7
368 prim_subreg #(
369 .DW (1),
370 .SwAccess(prim_subreg_pkg::SwAccessRO),
371 .RESVAL (1'h0),
372 .Mubi (1'b0)
373 ) u_status_sram_alert (
374 .clk_i (clk_i),
375 .rst_ni (rst_ni),
376
377 // from register interface
378 .we (1'b0),
379 .wd ('0),
380
381 // from internal hardware
382 .de (hw2reg.status.sram_alert.de),
383 .d (hw2reg.status.sram_alert.d),
384
385 // to internal hardware
386 .qe (),
387 .q (reg2hw.status.sram_alert.q),
388 .ds (),
389
390 // to register interface (read)
391 .qs (status_sram_alert_qs)
392 );
393
394
395 // R[exec_regwen]: V(False)
396 prim_subreg #(
397 .DW (1),
398 .SwAccess(prim_subreg_pkg::SwAccessW0C),
399 .RESVAL (1'h1),
400 .Mubi (1'b0)
401 ) u_exec_regwen (
402 .clk_i (clk_i),
403 .rst_ni (rst_ni),
404
405 // from register interface
406 .we (exec_regwen_we),
407 .wd (exec_regwen_wd),
408
409 // from internal hardware
410 .de (1'b0),
411 .d ('0),
412
413 // to internal hardware
414 .qe (),
415 .q (),
416 .ds (),
417
418 // to register interface (read)
419 .qs (exec_regwen_qs)
420 );
421
422
423 // R[exec]: V(False)
424 // Create REGWEN-gated WE signal
425 logic exec_gated_we;
426 1/1 assign exec_gated_we = exec_we & exec_regwen_qs;
Tests: T1 T2 T3
427 prim_subreg #(
428 .DW (4),
429 .SwAccess(prim_subreg_pkg::SwAccessRW),
430 .RESVAL (4'h9),
431 .Mubi (1'b1)
432 ) u_exec (
433 .clk_i (clk_i),
434 .rst_ni (rst_ni),
435
436 // from register interface
437 .we (exec_gated_we),
438 .wd (exec_wd),
439
440 // from internal hardware
441 .de (1'b0),
442 .d ('0),
443
444 // to internal hardware
445 .qe (),
446 .q (reg2hw.exec.q),
447 .ds (),
448
449 // to register interface (read)
450 .qs (exec_qs)
451 );
452
453
454 // R[ctrl_regwen]: V(False)
455 prim_subreg #(
456 .DW (1),
457 .SwAccess(prim_subreg_pkg::SwAccessW0C),
458 .RESVAL (1'h1),
459 .Mubi (1'b0)
460 ) u_ctrl_regwen (
461 .clk_i (clk_i),
462 .rst_ni (rst_ni),
463
464 // from register interface
465 .we (ctrl_regwen_we),
466 .wd (ctrl_regwen_wd),
467
468 // from internal hardware
469 .de (1'b0),
470 .d ('0),
471
472 // to internal hardware
473 .qe (),
474 .q (),
475 .ds (),
476
477 // to register interface (read)
478 .qs (ctrl_regwen_qs)
479 );
480
481
482 // R[ctrl]: V(False)
483 logic ctrl_qe;
484 logic [1:0] ctrl_flds_we;
485 prim_flop #(
486 .Width(1),
487 .ResetValue(0)
488 ) u_ctrl0_qe (
489 .clk_i(clk_i),
490 .rst_ni(rst_ni),
491 .d_i(&ctrl_flds_we),
492 .q_o(ctrl_qe)
493 );
494 // Create REGWEN-gated WE signal
495 logic ctrl_gated_we;
496 1/1 assign ctrl_gated_we = ctrl_we & ctrl_regwen_qs;
Tests: T1 T2 T3
497 // F[renew_scr_key]: 0:0
498 prim_subreg #(
499 .DW (1),
500 .SwAccess(prim_subreg_pkg::SwAccessWO),
501 .RESVAL (1'h0),
502 .Mubi (1'b0)
503 ) u_ctrl_renew_scr_key (
504 .clk_i (clk_i),
505 .rst_ni (rst_ni),
506
507 // from register interface
508 .we (ctrl_gated_we),
509 .wd (ctrl_renew_scr_key_wd),
510
511 // from internal hardware
512 .de (1'b0),
513 .d ('0),
514
515 // to internal hardware
516 .qe (ctrl_flds_we[0]),
517 .q (reg2hw.ctrl.renew_scr_key.q),
518 .ds (),
519
520 // to register interface (read)
521 .qs ()
522 );
523 1/1 assign reg2hw.ctrl.renew_scr_key.qe = ctrl_qe;
Tests: T1 T2 T3
524
525 // F[init]: 1:1
526 prim_subreg #(
527 .DW (1),
528 .SwAccess(prim_subreg_pkg::SwAccessWO),
529 .RESVAL (1'h0),
530 .Mubi (1'b0)
531 ) u_ctrl_init (
532 .clk_i (clk_i),
533 .rst_ni (rst_ni),
534
535 // from register interface
536 .we (ctrl_gated_we),
537 .wd (ctrl_init_wd),
538
539 // from internal hardware
540 .de (1'b0),
541 .d ('0),
542
543 // to internal hardware
544 .qe (ctrl_flds_we[1]),
545 .q (reg2hw.ctrl.init.q),
546 .ds (),
547
548 // to register interface (read)
549 .qs ()
550 );
551 1/1 assign reg2hw.ctrl.init.qe = ctrl_qe;
Tests: T1 T2 T3
552
553
554 // R[scr_key_rotated]: V(False)
555 prim_subreg #(
556 .DW (4),
557 .SwAccess(prim_subreg_pkg::SwAccessW1C),
558 .RESVAL (4'h9),
559 .Mubi (1'b1)
560 ) u_scr_key_rotated (
561 .clk_i (clk_i),
562 .rst_ni (rst_ni),
563
564 // from register interface
565 .we (scr_key_rotated_we),
566 .wd (scr_key_rotated_wd),
567
568 // from internal hardware
569 .de (hw2reg.scr_key_rotated.de),
570 .d (hw2reg.scr_key_rotated.d),
571
572 // to internal hardware
573 .qe (),
574 .q (),
575 .ds (),
576
577 // to register interface (read)
578 .qs (scr_key_rotated_qs)
579 );
580
581
582 // R[readback_regwen]: V(False)
583 prim_subreg #(
584 .DW (1),
585 .SwAccess(prim_subreg_pkg::SwAccessW0C),
586 .RESVAL (1'h1),
587 .Mubi (1'b0)
588 ) u_readback_regwen (
589 .clk_i (clk_i),
590 .rst_ni (rst_ni),
591
592 // from register interface
593 .we (readback_regwen_we),
594 .wd (readback_regwen_wd),
595
596 // from internal hardware
597 .de (1'b0),
598 .d ('0),
599
600 // to internal hardware
601 .qe (),
602 .q (),
603 .ds (),
604
605 // to register interface (read)
606 .qs (readback_regwen_qs)
607 );
608
609
610 // R[readback]: V(False)
611 // Create REGWEN-gated WE signal
612 logic readback_gated_we;
613 1/1 assign readback_gated_we = readback_we & readback_regwen_qs;
Tests: T1 T2 T3
614 prim_subreg #(
615 .DW (4),
616 .SwAccess(prim_subreg_pkg::SwAccessRW),
617 .RESVAL (4'h9),
618 .Mubi (1'b1)
619 ) u_readback (
620 .clk_i (clk_i),
621 .rst_ni (rst_ni),
622
623 // from register interface
624 .we (readback_gated_we),
625 .wd (readback_wd),
626
627 // from internal hardware
628 .de (1'b0),
629 .d ('0),
630
631 // to internal hardware
632 .qe (),
633 .q (reg2hw.readback.q),
634 .ds (),
635
636 // to register interface (read)
637 .qs (readback_qs)
638 );
639
640
641
642 logic [8:0] addr_hit;
643 always_comb begin
644 1/1 addr_hit = '0;
Tests: T1 T2 T3
645 1/1 addr_hit[0] = (reg_addr == SRAM_CTRL_ALERT_TEST_OFFSET);
Tests: T1 T2 T3
646 1/1 addr_hit[1] = (reg_addr == SRAM_CTRL_STATUS_OFFSET);
Tests: T1 T2 T3
647 1/1 addr_hit[2] = (reg_addr == SRAM_CTRL_EXEC_REGWEN_OFFSET);
Tests: T1 T2 T3
648 1/1 addr_hit[3] = (reg_addr == SRAM_CTRL_EXEC_OFFSET);
Tests: T1 T2 T3
649 1/1 addr_hit[4] = (reg_addr == SRAM_CTRL_CTRL_REGWEN_OFFSET);
Tests: T1 T2 T3
650 1/1 addr_hit[5] = (reg_addr == SRAM_CTRL_CTRL_OFFSET);
Tests: T1 T2 T3
651 1/1 addr_hit[6] = (reg_addr == SRAM_CTRL_SCR_KEY_ROTATED_OFFSET);
Tests: T1 T2 T3
652 1/1 addr_hit[7] = (reg_addr == SRAM_CTRL_READBACK_REGWEN_OFFSET);
Tests: T1 T2 T3
653 1/1 addr_hit[8] = (reg_addr == SRAM_CTRL_READBACK_OFFSET);
Tests: T1 T2 T3
654 end
655
656 1/1 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
Tests: T1 T2 T3
657
658 // Check sub-word write is permitted
659 always_comb begin
660 1/1 wr_err = (reg_we &
Tests: T1 T2 T3
661 ((addr_hit[0] & (|(SRAM_CTRL_REGS_PERMIT[0] & ~reg_be))) |
662 (addr_hit[1] & (|(SRAM_CTRL_REGS_PERMIT[1] & ~reg_be))) |
663 (addr_hit[2] & (|(SRAM_CTRL_REGS_PERMIT[2] & ~reg_be))) |
664 (addr_hit[3] & (|(SRAM_CTRL_REGS_PERMIT[3] & ~reg_be))) |
665 (addr_hit[4] & (|(SRAM_CTRL_REGS_PERMIT[4] & ~reg_be))) |
666 (addr_hit[5] & (|(SRAM_CTRL_REGS_PERMIT[5] & ~reg_be))) |
667 (addr_hit[6] & (|(SRAM_CTRL_REGS_PERMIT[6] & ~reg_be))) |
668 (addr_hit[7] & (|(SRAM_CTRL_REGS_PERMIT[7] & ~reg_be))) |
669 (addr_hit[8] & (|(SRAM_CTRL_REGS_PERMIT[8] & ~reg_be)))));
670 end
671
672 // Generate write-enables
673 1/1 assign alert_test_we = addr_hit[0] & reg_we & !reg_error;
Tests: T1 T2 T3
674
675 1/1 assign alert_test_wd = reg_wdata[0];
Tests: T1 T2 T3
676 1/1 assign exec_regwen_we = addr_hit[2] & reg_we & !reg_error;
Tests: T1 T2 T3
677
678 1/1 assign exec_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
679 1/1 assign exec_we = addr_hit[3] & reg_we & !reg_error;
Tests: T1 T2 T3
680
681 1/1 assign exec_wd = reg_wdata[3:0];
Tests: T1 T2 T3
682 1/1 assign ctrl_regwen_we = addr_hit[4] & reg_we & !reg_error;
Tests: T1 T2 T3
683
684 1/1 assign ctrl_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
685 1/1 assign ctrl_we = addr_hit[5] & reg_we & !reg_error;
Tests: T1 T2 T3
686
687 1/1 assign ctrl_renew_scr_key_wd = reg_wdata[0];
Tests: T1 T2 T3
688
689 1/1 assign ctrl_init_wd = reg_wdata[1];
Tests: T1 T2 T3
690 1/1 assign scr_key_rotated_we = addr_hit[6] & reg_we & !reg_error;
Tests: T1 T2 T3
691
692 1/1 assign scr_key_rotated_wd = reg_wdata[3:0];
Tests: T1 T2 T3
693 1/1 assign readback_regwen_we = addr_hit[7] & reg_we & !reg_error;
Tests: T1 T2 T3
694
695 1/1 assign readback_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
696 1/1 assign readback_we = addr_hit[8] & reg_we & !reg_error;
Tests: T1 T2 T3
697
698 1/1 assign readback_wd = reg_wdata[3:0];
Tests: T1 T2 T3
699
700 // Assign write-enables to checker logic vector.
701 always_comb begin
702 1/1 reg_we_check = '0;
Tests: T1 T2 T4
703 1/1 reg_we_check[0] = alert_test_we;
Tests: T1 T2 T4
704 1/1 reg_we_check[1] = 1'b0;
Tests: T1 T2 T4
705 1/1 reg_we_check[2] = exec_regwen_we;
Tests: T1 T2 T4
706 1/1 reg_we_check[3] = exec_gated_we;
Tests: T1 T2 T4
707 1/1 reg_we_check[4] = ctrl_regwen_we;
Tests: T1 T2 T4
708 1/1 reg_we_check[5] = ctrl_gated_we;
Tests: T1 T2 T4
709 1/1 reg_we_check[6] = scr_key_rotated_we;
Tests: T1 T2 T4
710 1/1 reg_we_check[7] = readback_regwen_we;
Tests: T1 T2 T4
711 1/1 reg_we_check[8] = readback_gated_we;
Tests: T1 T2 T4
712 end
713
714 // Read data return
715 always_comb begin
716 1/1 reg_rdata_next = '0;
Tests: T1 T2 T3
717 1/1 unique case (1'b1)
Tests: T1 T2 T3
718 addr_hit[0]: begin
719 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T3
720 end
721
722 addr_hit[1]: begin
723 1/1 reg_rdata_next[0] = status_bus_integ_error_qs;
Tests: T2 T3 T4
724 1/1 reg_rdata_next[1] = status_init_error_qs;
Tests: T2 T3 T4
725 1/1 reg_rdata_next[2] = status_escalated_qs;
Tests: T2 T3 T4
726 1/1 reg_rdata_next[3] = status_scr_key_valid_qs;
Tests: T2 T3 T4
727 1/1 reg_rdata_next[4] = status_scr_key_seed_valid_qs;
Tests: T2 T3 T4
728 1/1 reg_rdata_next[5] = status_init_done_qs;
Tests: T2 T3 T4
729 1/1 reg_rdata_next[6] = status_readback_error_qs;
Tests: T2 T3 T4
730 1/1 reg_rdata_next[7] = status_sram_alert_qs;
Tests: T2 T3 T4
731 end
732
733 addr_hit[2]: begin
734 1/1 reg_rdata_next[0] = exec_regwen_qs;
Tests: T2 T3 T4
735 end
736
737 addr_hit[3]: begin
738 1/1 reg_rdata_next[3:0] = exec_qs;
Tests: T2 T3 T4
739 end
740
741 addr_hit[4]: begin
742 1/1 reg_rdata_next[0] = ctrl_regwen_qs;
Tests: T2 T3 T4
743 end
744
745 addr_hit[5]: begin
746 1/1 reg_rdata_next[0] = '0;
Tests: T2 T3 T4
747 1/1 reg_rdata_next[1] = '0;
Tests: T2 T3 T4
748 end
749
750 addr_hit[6]: begin
751 1/1 reg_rdata_next[3:0] = scr_key_rotated_qs;
Tests: T2 T3 T4
752 end
753
754 addr_hit[7]: begin
755 1/1 reg_rdata_next[0] = readback_regwen_qs;
Tests: T2 T3 T4
756 end
757
758 addr_hit[8]: begin
759 1/1 reg_rdata_next[3:0] = readback_qs;
Tests: T1 T2 T3
760 end
761
762 default: begin
763 reg_rdata_next = '1;
764 end
765 endcase
766 end
767
768 // shadow busy
769 logic shadow_busy;
770 assign shadow_busy = 1'b0;
771
772 // register busy
773 unreachable assign reg_busy = shadow_busy;
774
775 // Unused signal tieoff
776
777 // wdata / byte enable are not always fully used
778 // add a blanket unused statement to handle lint waivers
779 logic unused_wdata;
780 logic unused_be;
781 1/1 assign unused_wdata = ^reg_wdata;
Tests: T1 T2 T3
782 1/1 assign unused_be = ^reg_be;
Tests: T1 T2 T3
Cond Coverage for Module :
sram_ctrl_regs_reg_top
| Total | Covered | Percent |
|---|
| Conditions | 118 | 116 | 98.31 |
| Logical | 118 | 116 | 98.31 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 58
EXPRESSION (reg_we && ((!addrmiss)))
---1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T21,T23,T25 |
| 1 | 1 | Covered | T1,T2,T4 |
LINE 70
EXPRESSION (intg_err || reg_we_err)
----1--- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T3,T6,T7 |
| 1 | 0 | Covered | T61,T62,T63 |
LINE 77
EXPRESSION (err_q | intg_err | reg_we_err)
--1-- ----2--- -----3----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T3,T6,T7 |
| 0 | 1 | 0 | Covered | T61,T62,T63 |
| 1 | 0 | 0 | Covered | T3,T6,T7 |
LINE 119
EXPRESSION (addrmiss | wr_err | intg_err)
----1--- ---2-- ----3---
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T61,T62,T63 |
| 0 | 1 | 0 | Covered | T21,T23,T25 |
| 1 | 0 | 0 | Covered | T21,T23,T25 |
LINE 426
EXPRESSION (exec_we & exec_regwen_qs)
---1--- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T18,T64 |
| 1 | 1 | Covered | T21,T17,T27 |
LINE 496
EXPRESSION (ctrl_we & ctrl_regwen_qs)
---1--- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T27,T18,T64 |
| 1 | 1 | Covered | T2,T4,T5 |
LINE 613
EXPRESSION (readback_we & readback_regwen_qs)
-----1----- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T14,T21 |
LINE 645
EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_ALERT_TEST_OFFSET)
------------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T14,T21 |
LINE 646
EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_STATUS_OFFSET)
----------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T6,T21 |
LINE 647
EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_EXEC_REGWEN_OFFSET)
------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T21,T23,T25 |
LINE 648
EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_EXEC_OFFSET)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T21,T17,T23 |
LINE 649
EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_CTRL_REGWEN_OFFSET)
------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T21,T23,T25 |
LINE 650
EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_CTRL_OFFSET)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 651
EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_SCR_KEY_ROTATED_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T21,T23,T25 |
LINE 652
EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_READBACK_REGWEN_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T21,T23,T25 |
LINE 653
EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_READBACK_OFFSET)
-----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T14,T21 |
LINE 656
EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 656
SUB-EXPRESSION (reg_re || reg_we)
---1-- ---2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T4 |
| 1 | 0 | Covered | T3,T6,T21 |
LINE 660
EXPRESSION
Number Term
1 reg_we &
2 ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be)))))))
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T21,T17 |
| 1 | 0 | Covered | T1,T2,T4 |
| 1 | 1 | Covered | T21,T23,T25 |
LINE 660
SUB-EXPRESSION
Number Term
1 (addr_hit[0] & ((|(4'b1 & (~reg_be))))) |
2 (addr_hit[1] & ((|(4'b1 & (~reg_be))))) |
3 (addr_hit[2] & ((|(4'b1 & (~reg_be))))) |
4 (addr_hit[3] & ((|(4'b1 & (~reg_be))))) |
5 (addr_hit[4] & ((|(4'b1 & (~reg_be))))) |
6 (addr_hit[5] & ((|(4'b1 & (~reg_be))))) |
7 (addr_hit[6] & ((|(4'b1 & (~reg_be))))) |
8 (addr_hit[7] & ((|(4'b1 & (~reg_be))))) |
9 (addr_hit[8] & ((|(4'b1 & (~reg_be))))))
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | Covered | T1,T21,T23 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | Covered | T21,T23,T25 |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | Covered | T21,T23,T25 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | Covered | T21,T17,T23 |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | Covered | T21,T23,T25 |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | Covered | T21,T23,T25 |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T21,T23,T25 |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T21,T23,T25 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T21,T23,T25 |
LINE 660
SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T21,T17 |
| 1 | 0 | Covered | T1,T14,T21 |
| 1 | 1 | Covered | T21,T23,T25 |
LINE 660
SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T21,T17 |
| 1 | 0 | Covered | T3,T6,T21 |
| 1 | 1 | Covered | T21,T23,T25 |
LINE 660
SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T21,T17 |
| 1 | 0 | Covered | T21,T23,T25 |
| 1 | 1 | Covered | T21,T23,T25 |
LINE 660
SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T21,T17 |
| 1 | 0 | Covered | T21,T17,T23 |
| 1 | 1 | Covered | T21,T23,T25 |
LINE 660
SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T21,T17 |
| 1 | 0 | Covered | T21,T23,T25 |
| 1 | 1 | Covered | T21,T23,T25 |
LINE 660
SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T21,T23 |
| 1 | 0 | Covered | T2,T4,T5 |
| 1 | 1 | Covered | T21,T17,T23 |
LINE 660
SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T21,T17 |
| 1 | 0 | Covered | T21,T23,T25 |
| 1 | 1 | Covered | T21,T23,T25 |
LINE 660
SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T21,T17 |
| 1 | 0 | Covered | T21,T23,T25 |
| 1 | 1 | Covered | T21,T23,T25 |
LINE 660
SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T21,T17 |
| 1 | 0 | Covered | T1,T14,T21 |
| 1 | 1 | Covered | T1,T21,T23 |
LINE 673
EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T4 |
| 1 | 0 | 1 | Covered | T1,T14,T21 |
| 1 | 1 | 0 | Covered | T21,T23,T25 |
| 1 | 1 | 1 | Covered | T1,T14,T15 |
LINE 676
EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T4 |
| 1 | 0 | 1 | Covered | T21,T23,T24 |
| 1 | 1 | 0 | Covered | T21,T23,T25 |
| 1 | 1 | 1 | Covered | T27,T18,T64 |
LINE 679
EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T4 |
| 1 | 0 | 1 | Covered | T21,T17,T23 |
| 1 | 1 | 0 | Covered | T21,T23,T25 |
| 1 | 1 | 1 | Covered | T21,T17,T27 |
LINE 682
EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T4 |
| 1 | 0 | 1 | Covered | T21,T23,T25 |
| 1 | 1 | 0 | Covered | T21,T23,T25 |
| 1 | 1 | 1 | Covered | T27,T18,T64 |
LINE 685
EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T14,T21 |
| 1 | 0 | 1 | Covered | T2,T4,T5 |
| 1 | 1 | 0 | Covered | T21,T23,T25 |
| 1 | 1 | 1 | Covered | T2,T4,T5 |
LINE 690
EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T4 |
| 1 | 0 | 1 | Covered | T1,T21,T23 |
| 1 | 1 | 0 | Covered | T21,T23,T25 |
| 1 | 1 | 1 | Covered | T65,T66,T61 |
LINE 693
EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T4 |
| 1 | 0 | 1 | Covered | T21,T23,T25 |
| 1 | 1 | 0 | Covered | T21,T23,T25 |
| 1 | 1 | 1 | Not Covered | |
LINE 696
EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T4 |
| 1 | 0 | 1 | Covered | T1,T14,T21 |
| 1 | 1 | 0 | Covered | T21,T23,T25 |
| 1 | 1 | 1 | Covered | T1,T14,T21 |
Branch Coverage for Module :
sram_ctrl_regs_reg_top
| Line No. | Total | Covered | Percent |
| Branches |
|
15 |
15 |
100.00 |
| TERNARY |
656 |
2 |
2 |
100.00 |
| IF |
68 |
3 |
3 |
100.00 |
| CASE |
717 |
10 |
10 |
100.00 |
656 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
68 if (!rst_ni) begin
-1-
69 err_q <= '0;
==>
70 end else if (intg_err || reg_we_err) begin
-2-
71 err_q <= 1'b1;
==>
72 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T3,T6,T7 |
| 0 |
0 |
Covered |
T1,T2,T3 |
717 unique case (1'b1)
-1-
718 addr_hit[0]: begin
719 reg_rdata_next[0] = '0;
==>
720 end
721
722 addr_hit[1]: begin
723 reg_rdata_next[0] = status_bus_integ_error_qs;
==>
724 reg_rdata_next[1] = status_init_error_qs;
725 reg_rdata_next[2] = status_escalated_qs;
726 reg_rdata_next[3] = status_scr_key_valid_qs;
727 reg_rdata_next[4] = status_scr_key_seed_valid_qs;
728 reg_rdata_next[5] = status_init_done_qs;
729 reg_rdata_next[6] = status_readback_error_qs;
730 reg_rdata_next[7] = status_sram_alert_qs;
731 end
732
733 addr_hit[2]: begin
734 reg_rdata_next[0] = exec_regwen_qs;
==>
735 end
736
737 addr_hit[3]: begin
738 reg_rdata_next[3:0] = exec_qs;
==>
739 end
740
741 addr_hit[4]: begin
742 reg_rdata_next[0] = ctrl_regwen_qs;
==>
743 end
744
745 addr_hit[5]: begin
746 reg_rdata_next[0] = '0;
==>
747 reg_rdata_next[1] = '0;
748 end
749
750 addr_hit[6]: begin
751 reg_rdata_next[3:0] = scr_key_rotated_qs;
==>
752 end
753
754 addr_hit[7]: begin
755 reg_rdata_next[0] = readback_regwen_qs;
==>
756 end
757
758 addr_hit[8]: begin
759 reg_rdata_next[3:0] = readback_qs;
==>
760 end
761
762 default: begin
763 reg_rdata_next = '1;
==>
Branches:
| -1- | Status | Tests |
| addr_hit[0] |
Covered |
T1,T2,T3 |
| addr_hit[1] |
Covered |
T2,T3,T4 |
| addr_hit[2] |
Covered |
T2,T3,T4 |
| addr_hit[3] |
Covered |
T2,T3,T4 |
| addr_hit[4] |
Covered |
T2,T3,T4 |
| addr_hit[5] |
Covered |
T2,T3,T4 |
| addr_hit[6] |
Covered |
T2,T3,T4 |
| addr_hit[7] |
Covered |
T2,T3,T4 |
| addr_hit[8] |
Covered |
T1,T2,T3 |
| default |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
sram_ctrl_regs_reg_top
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
en2addrHit |
1315337505 |
62001 |
0 |
0 |
|
reAfterRv |
1315337505 |
62001 |
0 |
0 |
|
rePulse |
1315337505 |
20560 |
0 |
0 |
|
wePulse |
1315337505 |
41441 |
0 |
0 |
en2addrHit
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1315337505 |
62001 |
0 |
0 |
| T1 |
683 |
3 |
0 |
0 |
| T2 |
34149 |
1 |
0 |
0 |
| T3 |
16579 |
80 |
0 |
0 |
| T4 |
49584 |
1 |
0 |
0 |
| T5 |
94743 |
2 |
0 |
0 |
| T6 |
8857 |
40 |
0 |
0 |
| T8 |
69249 |
2 |
0 |
0 |
| T12 |
72512 |
2 |
0 |
0 |
| T13 |
34567 |
1 |
0 |
0 |
| T14 |
990 |
3 |
0 |
0 |
reAfterRv
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1315337505 |
62001 |
0 |
0 |
| T1 |
683 |
3 |
0 |
0 |
| T2 |
34149 |
1 |
0 |
0 |
| T3 |
16579 |
80 |
0 |
0 |
| T4 |
49584 |
1 |
0 |
0 |
| T5 |
94743 |
2 |
0 |
0 |
| T6 |
8857 |
40 |
0 |
0 |
| T8 |
69249 |
2 |
0 |
0 |
| T12 |
72512 |
2 |
0 |
0 |
| T13 |
34567 |
1 |
0 |
0 |
| T14 |
990 |
3 |
0 |
0 |
rePulse
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1315337505 |
20560 |
0 |
0 |
| T3 |
16579 |
80 |
0 |
0 |
| T4 |
49584 |
0 |
0 |
0 |
| T5 |
94743 |
0 |
0 |
0 |
| T6 |
8857 |
40 |
0 |
0 |
| T7 |
0 |
80 |
0 |
0 |
| T8 |
69249 |
0 |
0 |
0 |
| T9 |
0 |
37 |
0 |
0 |
| T10 |
0 |
43 |
0 |
0 |
| T11 |
0 |
44 |
0 |
0 |
| T12 |
72512 |
0 |
0 |
0 |
| T13 |
34567 |
0 |
0 |
0 |
| T14 |
990 |
0 |
0 |
0 |
| T17 |
0 |
2 |
0 |
0 |
| T21 |
0 |
118 |
0 |
0 |
| T23 |
0 |
50 |
0 |
0 |
| T25 |
0 |
123 |
0 |
0 |
| T29 |
69912 |
0 |
0 |
0 |
| T30 |
68864 |
0 |
0 |
0 |
wePulse
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1315337505 |
41441 |
0 |
0 |
| T1 |
683 |
3 |
0 |
0 |
| T2 |
34149 |
1 |
0 |
0 |
| T3 |
16579 |
0 |
0 |
0 |
| T4 |
49584 |
1 |
0 |
0 |
| T5 |
94743 |
2 |
0 |
0 |
| T6 |
8857 |
0 |
0 |
0 |
| T8 |
69249 |
2 |
0 |
0 |
| T12 |
72512 |
2 |
0 |
0 |
| T13 |
34567 |
1 |
0 |
0 |
| T14 |
990 |
3 |
0 |
0 |
| T29 |
0 |
2 |
0 |
0 |
| T30 |
0 |
2 |
0 |
0 |
