Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1315337505	270719	0	0
ctrl_regwen_rd_A	1315337505	6139	0	0
exec_rd_A	1315337505	5841	0	0
exec_regwen_rd_A	1315337505	6204	0	0
readback_rd_A	1315337505	4750	0	0
readback_regwen_rd_A	1315337505	4263	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1315337505	270719	0	0
T7	25890	0	0	0
T15	1580	0	0	0
T17	120023	0	0	0
T21	223049	6641	0	0
T22	74514	0	0	0
T23	23630	1930	0	0
T24	36969	0	0	0
T25	0	6599	0	0
T26	0	5838	0	0
T32	115615	0	0	0
T33	78423	0	0	0
T44	0	4355	0	0
T54	76136	0	0	0
T55	0	6363	0	0
T67	0	3174	0	0
T68	0	1179	0	0
T69	0	2151	0	0
T70	0	4056	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1315337505	6139	0	0
T7	25890	0	0	0
T15	1580	0	0	0
T17	120023	0	0	0
T21	223049	381	0	0
T22	74514	0	0	0
T23	23630	0	0	0
T24	36969	0	0	0
T26	0	226	0	0
T32	115615	0	0	0
T33	78423	0	0	0
T44	0	282	0	0
T46	0	210	0	0
T54	76136	0	0	0
T55	0	482	0	0
T68	0	101	0	0
T69	0	168	0	0
T123	0	405	0	0
T124	0	100	0	0
T125	0	387	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1315337505	5841	0	0
T7	25890	0	0	0
T15	1580	0	0	0
T17	120023	0	0	0
T21	223049	437	0	0
T22	74514	0	0	0
T23	23630	0	0	0
T24	36969	0	0	0
T26	0	198	0	0
T32	115615	0	0	0
T33	78423	0	0	0
T44	0	276	0	0
T46	0	178	0	0
T54	76136	0	0	0
T55	0	378	0	0
T68	0	53	0	0
T69	0	172	0	0
T123	0	334	0	0
T124	0	187	0	0
T125	0	271	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1315337505	6204	0	0
T7	25890	0	0	0
T15	1580	0	0	0
T17	120023	0	0	0
T21	223049	413	0	0
T22	74514	0	0	0
T23	23630	0	0	0
T24	36969	0	0	0
T26	0	219	0	0
T32	115615	0	0	0
T33	78423	0	0	0
T44	0	347	0	0
T46	0	190	0	0
T54	76136	0	0	0
T55	0	459	0	0
T68	0	147	0	0
T69	0	154	0	0
T123	0	360	0	0
T124	0	156	0	0
T125	0	253	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1315337505	4750	0	0
T7	25890	0	0	0
T15	1580	0	0	0
T17	120023	0	0	0
T21	223049	418	0	0
T22	74514	0	0	0
T23	23630	0	0	0
T24	36969	0	0	0
T26	0	185	0	0
T32	115615	0	0	0
T33	78423	0	0	0
T44	0	366	0	0
T46	0	233	0	0
T54	76136	0	0	0
T55	0	431	0	0
T68	0	80	0	0
T69	0	173	0	0
T123	0	414	0	0
T124	0	121	0	0
T125	0	227	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1315337505	4263	0	0
T7	25890	0	0	0
T15	1580	0	0	0
T17	120023	0	0	0
T21	223049	374	0	0
T22	74514	0	0	0
T23	23630	0	0	0
T24	36969	0	0	0
T26	0	148	0	0
T32	115615	0	0	0
T33	78423	0	0	0
T44	0	289	0	0
T46	0	197	0	0
T54	76136	0	0	0
T55	0	361	0	0
T68	0	149	0	0
T69	0	137	0	0
T123	0	420	0	0
T124	0	106	0	0
T125	0	221	0	0