Unified Coverage Report :: Module :: prim_secded_inv_39_32

Module : prim_secded_inv_39_32_enc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_regs.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen	100.00	100.00
tb.dut.u_tlul_data_integ_enc.u_data_gen	100.00	100.00
tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen	100.00	100.00
tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_tlul_data_integ_enc.u_data_gen	100.00	100.00
tb.dut.u_tlul_adapter_sram.u_tlul_data_integ_enc_instr.u_data_gen
tb.dut.u_tlul_adapter_sram.u_tlul_data_integ_enc_data.u_data_gen

Module Instance : tb.dut.u_reg_regs.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_data_intg.u_tlul_data_integ_enc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_tlul_data_integ_enc.u_data_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_tlul_data_integ_enc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_data_intg.u_tlul_data_integ_enc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_tlul_data_integ_enc.u_data_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_integ_handling.u_tlul_data_integ_enc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_secded_inv_39_32_enc

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00



12                        always_comb begin : p_encode
13         1/1              data_o = 39'(data_i);
           Tests:       T1 T2 T3 
14         1/1              data_o[32] = ^(data_o & 39'h002606BD25);
           Tests:       T1 T2 T3 
15         1/1              data_o[33] = ^(data_o & 39'h00DEBA8050);
           Tests:       T1 T2 T3 
16         1/1              data_o[34] = ^(data_o & 39'h00413D89AA);
           Tests:       T1 T2 T3 
17         1/1              data_o[35] = ^(data_o & 39'h0031234ED1);
           Tests:       T1 T2 T3 
18         1/1              data_o[36] = ^(data_o & 39'h00C2C1323B);
           Tests:       T1 T2 T3 
19         1/1              data_o[37] = ^(data_o & 39'h002DCC624C);
           Tests:       T1 T2 T3 
20         1/1              data_o[38] = ^(data_o & 39'h0098505586);
           Tests:       T1 T2 T3 
21         1/1              data_o ^= 39'h2A00000000;
           Tests:       T1 T2 T3

Line Coverage for Instance : tb.dut.u_reg_regs.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00



12                        always_comb begin : p_encode
13         1/1              data_o = 39'(data_i);
           Tests:       T1 T2 T3 
14         1/1              data_o[32] = ^(data_o & 39'h002606BD25);
           Tests:       T1 T2 T3 
15         1/1              data_o[33] = ^(data_o & 39'h00DEBA8050);
           Tests:       T1 T2 T3 
16         1/1              data_o[34] = ^(data_o & 39'h00413D89AA);
           Tests:       T1 T2 T3 
17         1/1              data_o[35] = ^(data_o & 39'h0031234ED1);
           Tests:       T1 T2 T3 
18         1/1              data_o[36] = ^(data_o & 39'h00C2C1323B);
           Tests:       T1 T2 T3 
19         1/1              data_o[37] = ^(data_o & 39'h002DCC624C);
           Tests:       T1 T2 T3 
20         1/1              data_o[38] = ^(data_o & 39'h0098505586);
           Tests:       T1 T2 T3 
21         1/1              data_o ^= 39'h2A00000000;
           Tests:       T1 T2 T3

Line Coverage for Instance : tb.dut.u_tlul_data_integ_enc.u_data_gen

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00



12                        always_comb begin : p_encode
13         1/1              data_o = 39'(data_i);
           Tests:       T1 T2 T3 
14         1/1              data_o[32] = ^(data_o & 39'h002606BD25);
           Tests:       T1 T2 T3 
15         1/1              data_o[33] = ^(data_o & 39'h00DEBA8050);
           Tests:       T1 T2 T3 
16         1/1              data_o[34] = ^(data_o & 39'h00413D89AA);
           Tests:       T1 T2 T3 
17         1/1              data_o[35] = ^(data_o & 39'h0031234ED1);
           Tests:       T1 T2 T3 
18         1/1              data_o[36] = ^(data_o & 39'h00C2C1323B);
           Tests:       T1 T2 T3 
19         1/1              data_o[37] = ^(data_o & 39'h002DCC624C);
           Tests:       T1 T2 T3 
20         1/1              data_o[38] = ^(data_o & 39'h0098505586);
           Tests:       T1 T2 T3 
21         1/1              data_o ^= 39'h2A00000000;
           Tests:       T1 T2 T3

Line Coverage for Instance : tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00



12                        always_comb begin : p_encode
13         1/1              data_o = 39'(data_i);
           Tests:       T1 T2 T3 
14         1/1              data_o[32] = ^(data_o & 39'h002606BD25);
           Tests:       T1 T2 T3 
15         1/1              data_o[33] = ^(data_o & 39'h00DEBA8050);
           Tests:       T1 T2 T3 
16         1/1              data_o[34] = ^(data_o & 39'h00413D89AA);
           Tests:       T1 T2 T3 
17         1/1              data_o[35] = ^(data_o & 39'h0031234ED1);
           Tests:       T1 T2 T3 
18         1/1              data_o[36] = ^(data_o & 39'h00C2C1323B);
           Tests:       T1 T2 T3 
19         1/1              data_o[37] = ^(data_o & 39'h002DCC624C);
           Tests:       T1 T2 T3 
20         1/1              data_o[38] = ^(data_o & 39'h0098505586);
           Tests:       T1 T2 T3 
21         1/1              data_o ^= 39'h2A00000000;
           Tests:       T1 T2 T3

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte.gen_integ_handling.u_tlul_data_integ_enc.u_data_gen

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00



12                        always_comb begin : p_encode
13         1/1              data_o = 39'(data_i);
           Tests:       T4 T5 T12 
14         1/1              data_o[32] = ^(data_o & 39'h002606BD25);
           Tests:       T4 T5 T12 
15         1/1              data_o[33] = ^(data_o & 39'h00DEBA8050);
           Tests:       T4 T5 T12 
16         1/1              data_o[34] = ^(data_o & 39'h00413D89AA);
           Tests:       T4 T5 T12 
17         1/1              data_o[35] = ^(data_o & 39'h0031234ED1);
           Tests:       T4 T5 T12 
18         1/1              data_o[36] = ^(data_o & 39'h00C2C1323B);
           Tests:       T4 T5 T12 
19         1/1              data_o[37] = ^(data_o & 39'h002DCC624C);
           Tests:       T4 T5 T12 
20         1/1              data_o[38] = ^(data_o & 39'h0098505586);
           Tests:       T4 T5 T12 
21         1/1              data_o ^= 39'h2A00000000;
           Tests:       T4 T5 T12