Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16342066

1

T2

958

T3

3471

T4

55

full_word

154809333

1

T2

9090

T3

34731

T4

505

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	171151099	1			T2	10048		T3	38202		T4	560
auto[TlIntgErrCmd]	122	1			T114	10		T115	12		T116	2
auto[TlIntgErrData]	87	1			T114	5		T115	5		T116	2
auto[TlIntgErrBoth]	91	1			T114	5		T115	3		T116	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

82565800

1

T2

5067

T3

15598

T4

286

auto[1]

88585599

1

T2

4981

T3

22604

T4

274

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8005082	1			T2	488		T3	1416		T4	24
auto[TlIntgErrNone]	partial	auto[1]	8336711	1			T2	470		T3	2055		T4	31
auto[TlIntgErrNone]	full_word	auto[0]	74560589	1			T2	4579		T3	14182		T4	262
auto[TlIntgErrNone]	full_word	auto[1]	80248717	1			T2	4511		T3	20549		T4	243
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T114	3		T115	4		T116	2
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T114	5		T115	5		T137	2
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T115	2		T139	1		T143	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T114	2		T115	1		T141	2
auto[TlIntgErrData]	partial	auto[0]	32	1			T114	1		T115	3		T116	1
auto[TlIntgErrData]	partial	auto[1]	50	1			T114	3		T115	2		T116	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T138	1		T140	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1			T114	1		T137	1		T138	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T114	3		T116	5		T137	2
auto[TlIntgErrBoth]	partial	auto[1]	44	1			T114	2		T115	2		T137	1
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T115	1		T116	1		T144	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T134	1		T145	1		T140	1