Unified Coverage Report :: Group :: dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg

Group : dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_lockable_field_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
lockable_field_cov_of_sram_ctrl_regs_reg_block.ctrl.init	100.00	1	100	1	64	64
lockable_field_cov_of_sram_ctrl_regs_reg_block.ctrl.renew_scr_key	100.00	1	100	1	64	64
lockable_field_cov_of_sram_ctrl_regs_reg_block.exec.en	100.00	1	100	1	64	64
lockable_field_cov_of_sram_ctrl_regs_reg_block.readback.en	100.00	1	100	1	64	64

---

Group Instance : lockable_field_cov_of_sram_ctrl_regs_reg_block.ctrl.init

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sram_ctrl_regs_reg_block.ctrl.init

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sram_ctrl_regs_reg_block.ctrl.init

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sram_ctrl_regs_reg_block.ctrl.renew_scr_key

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sram_ctrl_regs_reg_block.ctrl.renew_scr_key

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sram_ctrl_regs_reg_block.ctrl.renew_scr_key

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sram_ctrl_regs_reg_block.exec.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sram_ctrl_regs_reg_block.exec.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sram_ctrl_regs_reg_block.exec.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sram_ctrl_regs_reg_block.readback.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sram_ctrl_regs_reg_block.readback.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sram_ctrl_regs_reg_block.readback.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1024

1

T3

3

T112

3

T18

1

auto[1]

156

1

T3

5

T113

1

T18

3

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1022

1

T3

3

T112

3

T18

2

auto[1]

158

1

T3

5

T113

1

T18

2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

717

1

T114

8

T69

128

T70

2

auto[1]

535

1

T114

12

T68

2

T70

9

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2103	1			T3	15		T112	3		T18	7
auto[1]	1	1			T122	1		-	-		-	-