Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	965716	1			T3	6		T31	2		T33	11
auto[1]	10627813	1			T3	85		T7	1564		T29	425
auto[2]	739689	1			T3	4		T31	6		T33	7
auto[3]	10312658	1			T3	70		T7	1542		T29	381

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13831033	1			T3	103		T7	3106		T29	38
auto[1]	2150271	1			T3	29		T29	133		T8	17
auto[2]	2175588	1			T3	26		T29	129		T8	13
auto[3]	4488984	1			T3	7		T29	506		T8	1

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9383768

1

T3

165

T7

3106

T29

806

auto[1]

13262108

1

T63

1

T78

1

T52

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	302609	1			T3	5		T33	9		T9	9
auto[0]	auto[0]	auto[1]	32055	1			T31	1		T33	1		T9	2
auto[0]	auto[0]	auto[2]	32185	1			T3	1		T33	1		T9	3
auto[0]	auto[0]	auto[3]	102115	1			T31	1		T77	28		T56	1
auto[0]	auto[1]	auto[0]	3363340	1			T3	52		T7	1564		T29	20
auto[0]	auto[1]	auto[1]	348938	1			T3	25		T29	64		T8	8
auto[0]	auto[1]	auto[2]	360087	1			T3	6		T29	67		T8	6
auto[0]	auto[1]	auto[3]	324306	1			T3	2		T29	274		T8	1
auto[0]	auto[2]	auto[0]	215343	1			T9	12		T16	15		T17	6
auto[0]	auto[2]	auto[1]	28709	1			T31	2		T9	2		T16	4
auto[0]	auto[2]	auto[2]	26017	1			T3	4		T31	2		T33	5
auto[0]	auto[2]	auto[3]	72125	1			T31	2		T33	2		T77	26
auto[0]	auto[3]	auto[0]	3196798	1			T3	46		T7	1542		T29	18
auto[0]	auto[3]	auto[1]	339270	1			T3	4		T29	69		T8	9
auto[0]	auto[3]	auto[2]	355885	1			T3	15		T29	62		T8	7
auto[0]	auto[3]	auto[3]	283986	1			T3	5		T29	232		T31	1
auto[1]	auto[0]	auto[0]	16377	1			T124	1		T105	649		T155	174
auto[1]	auto[0]	auto[1]	73936	1			T105	3086		T155	719		T156	636
auto[1]	auto[0]	auto[2]	74311	1			T105	3112		T155	685		T156	652
auto[1]	auto[0]	auto[3]	332128	1			T84	2		T85	2		T86	2
auto[1]	auto[1]	auto[0]	3360738	1			T63	1		T55	29617		T102	66474
auto[1]	auto[1]	auto[1]	661254	1			T55	3038		T102	6748		T103	6883
auto[1]	auto[1]	auto[2]	621227	1			T55	3046		T102	6779		T103	6857
auto[1]	auto[1]	auto[3]	1587923	1			T52	1		T55	278		T85	1
auto[1]	auto[2]	auto[0]	13417	1			T105	627		T157	735		T158	717
auto[1]	auto[2]	auto[1]	60138	1			T105	2787		T157	3313		T158	3323
auto[1]	auto[2]	auto[2]	58728	1			T105	2067		T155	658		T156	554
auto[1]	auto[2]	auto[3]	265212	1			T105	9124		T155	2765		T156	2457
auto[1]	auto[3]	auto[0]	3362411	1			T78	1		T55	29726		T35	1
auto[1]	auto[3]	auto[1]	605971	1			T55	2958		T85	1		T102	6676
auto[1]	auto[3]	auto[2]	647148	1			T55	3004		T102	6575		T103	6903
auto[1]	auto[3]	auto[3]	1521189	1			T55	296		T102	667		T103	657