Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1138007828	232400	0	0
ctrl_regwen_rd_A	1138007828	3945	0	0
exec_rd_A	1138007828	3669	0	0
exec_regwen_rd_A	1138007828	4142	0	0
readback_rd_A	1138007828	4006	0	0
readback_regwen_rd_A	1138007828	1832	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1138007828	232400	0	0
T8	238311	0	0	0
T11	29905	1945	0	0
T21	46074	2904	0	0
T22	31610	1745	0	0
T25	67931	0	0	0
T29	68767	0	0	0
T30	57878	0	0	0
T31	146426	0	0	0
T32	69895	0	0	0
T33	54164	0	0	0
T39	0	6176	0	0
T42	0	2475	0	0
T53	0	1989	0	0
T58	0	5867	0	0
T64	0	1692	0	0
T65	0	1385	0	0
T66	0	2216	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1138007828	3945	0	0
T35	563737	0	0	0
T42	68933	108	0	0
T43	578987	0	0	0
T48	691171	0	0	0
T49	262722	0	0	0
T64	0	137	0	0
T67	0	4	0	0
T69	0	416	0	0
T102	389730	0	0	0
T117	0	232	0	0
T118	0	127	0	0
T119	0	361	0	0
T120	0	303	0	0
T121	0	467	0	0
T122	0	406	0	0
T123	97945	0	0	0
T124	467439	0	0	0
T125	57269	0	0	0
T126	71635	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1138007828	3669	0	0
T35	563737	0	0	0
T42	68933	77	0	0
T43	578987	0	0	0
T48	691171	0	0	0
T49	262722	0	0	0
T64	0	127	0	0
T69	0	457	0	0
T102	389730	0	0	0
T117	0	189	0	0
T118	0	87	0	0
T119	0	328	0	0
T120	0	306	0	0
T121	0	433	0	0
T122	0	360	0	0
T123	97945	0	0	0
T124	467439	0	0	0
T125	57269	0	0	0
T126	71635	0	0	0
T127	0	34	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1138007828	4142	0	0
T35	563737	0	0	0
T42	68933	77	0	0
T43	578987	0	0	0
T48	691171	0	0	0
T49	262722	0	0	0
T64	0	155	0	0
T67	0	2	0	0
T69	0	533	0	0
T102	389730	0	0	0
T117	0	300	0	0
T118	0	167	0	0
T119	0	307	0	0
T120	0	325	0	0
T121	0	566	0	0
T122	0	303	0	0
T123	97945	0	0	0
T124	467439	0	0	0
T125	57269	0	0	0
T126	71635	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1138007828	4006	0	0
T35	563737	0	0	0
T42	68933	60	0	0
T43	578987	0	0	0
T48	691171	0	0	0
T49	262722	0	0	0
T64	0	181	0	0
T102	389730	0	0	0
T117	0	180	0	0
T118	0	90	0	0
T119	0	356	0	0
T123	97945	0	0	0
T124	467439	0	0	0
T125	57269	0	0	0
T126	71635	0	0	0
T128	0	56	0	0
T129	0	210	0	0
T130	0	199	0	0
T131	0	101	0	0
T132	0	10	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1138007828	1832	0	0
T35	563737	0	0	0
T42	68933	85	0	0
T43	578987	0	0	0
T48	691171	0	0	0
T49	262722	0	0	0
T64	0	110	0	0
T102	389730	0	0	0
T117	0	191	0	0
T118	0	97	0	0
T119	0	261	0	0
T120	0	203	0	0
T121	0	435	0	0
T122	0	324	0	0
T123	97945	0	0	0
T124	467439	0	0	0
T125	57269	0	0	0
T126	71635	0	0	0
T127	0	7	0	0
T133	0	20	0	0