| T301 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_bijection.3942654210 |
|
|
Oct 12 02:37:13 AM UTC 24 |
Oct 12 03:01:20 AM UTC 24 |
97771348132 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.3992722111 |
|
|
Oct 12 02:57:46 AM UTC 24 |
Oct 12 03:01:24 AM UTC 24 |
19203606819 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access.4038017334 |
|
|
Oct 12 03:01:21 AM UTC 24 |
Oct 12 03:01:45 AM UTC 24 |
1810371540 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.1374066304 |
|
|
Oct 12 03:01:46 AM UTC 24 |
Oct 12 03:01:57 AM UTC 24 |
1342521791 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.1544085477 |
|
|
Oct 12 03:01:25 AM UTC 24 |
Oct 12 03:02:17 AM UTC 24 |
5171246181 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.799198631 |
|
|
Oct 12 02:48:45 AM UTC 24 |
Oct 12 03:02:28 AM UTC 24 |
30158730914 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_bijection.1976270394 |
|
|
Oct 12 02:37:35 AM UTC 24 |
Oct 12 03:02:51 AM UTC 24 |
122532696944 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_regwen.4088682886 |
|
|
Oct 12 02:59:49 AM UTC 24 |
Oct 12 03:02:53 AM UTC 24 |
960102048 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.4101209863 |
|
|
Oct 12 02:59:34 AM UTC 24 |
Oct 12 03:02:56 AM UTC 24 |
58729083658 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.2907511707 |
|
|
Oct 12 02:56:41 AM UTC 24 |
Oct 12 03:03:01 AM UTC 24 |
5467299006 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.2825234183 |
|
|
Oct 12 03:02:54 AM UTC 24 |
Oct 12 03:03:02 AM UTC 24 |
5564680608 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.2628665667 |
|
|
Oct 12 02:37:13 AM UTC 24 |
Oct 12 03:03:07 AM UTC 24 |
27470520532 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_readback_err.3360971734 |
|
|
Oct 12 03:03:03 AM UTC 24 |
Oct 12 03:03:15 AM UTC 24 |
2756414064 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.1699535648 |
|
|
Oct 12 03:00:30 AM UTC 24 |
Oct 12 03:03:24 AM UTC 24 |
9528458334 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.3716453246 |
|
|
Oct 12 02:57:46 AM UTC 24 |
Oct 12 03:03:26 AM UTC 24 |
18880047967 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_alert_test.2019111663 |
|
|
Oct 12 03:03:24 AM UTC 24 |
Oct 12 03:03:27 AM UTC 24 |
17056060 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.1465260777 |
|
|
Oct 12 03:01:57 AM UTC 24 |
Oct 12 03:03:39 AM UTC 24 |
21559586068 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.2878772684 |
|
|
Oct 12 02:58:59 AM UTC 24 |
Oct 12 03:03:39 AM UTC 24 |
4477384131 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2281851211 |
|
|
Oct 12 03:03:08 AM UTC 24 |
Oct 12 03:03:57 AM UTC 24 |
3282269853 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.2372566796 |
|
|
Oct 12 02:48:02 AM UTC 24 |
Oct 12 03:04:07 AM UTC 24 |
61407111648 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.3176118 |
|
|
Oct 12 02:57:25 AM UTC 24 |
Oct 12 03:04:36 AM UTC 24 |
131063095658 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_regwen.743991445 |
|
|
Oct 12 02:56:06 AM UTC 24 |
Oct 12 03:04:56 AM UTC 24 |
11468742068 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_smoke.546433855 |
|
|
Oct 12 03:03:26 AM UTC 24 |
Oct 12 03:05:05 AM UTC 24 |
9725019408 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3771101536 |
|
|
Oct 12 02:42:32 AM UTC 24 |
Oct 12 03:05:06 AM UTC 24 |
16363047326 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.1373398414 |
|
|
Oct 12 02:57:02 AM UTC 24 |
Oct 12 03:05:08 AM UTC 24 |
7470176859 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.2647216631 |
|
|
Oct 12 02:47:00 AM UTC 24 |
Oct 12 03:05:09 AM UTC 24 |
4723946369 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.589320784 |
|
|
Oct 12 02:40:09 AM UTC 24 |
Oct 12 03:05:20 AM UTC 24 |
60884955258 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.2905119110 |
|
|
Oct 12 02:40:57 AM UTC 24 |
Oct 12 03:05:23 AM UTC 24 |
51567638078 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.572106830 |
|
|
Oct 12 03:05:21 AM UTC 24 |
Oct 12 03:05:28 AM UTC 24 |
1344310614 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_executable.238202005 |
|
|
Oct 12 03:02:29 AM UTC 24 |
Oct 12 03:05:34 AM UTC 24 |
18637457067 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.1374106415 |
|
|
Oct 12 02:58:51 AM UTC 24 |
Oct 12 03:05:34 AM UTC 24 |
9294418764 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_readback_err.55446763 |
|
|
Oct 12 03:05:35 AM UTC 24 |
Oct 12 03:05:45 AM UTC 24 |
675759366 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access.2570823356 |
|
|
Oct 12 03:03:58 AM UTC 24 |
Oct 12 03:05:50 AM UTC 24 |
17955251664 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_alert_test.2983679266 |
|
|
Oct 12 03:05:51 AM UTC 24 |
Oct 12 03:05:53 AM UTC 24 |
29273907 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.3646504445 |
|
|
Oct 12 03:05:35 AM UTC 24 |
Oct 12 03:05:55 AM UTC 24 |
1642643174 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.2957947173 |
|
|
Oct 12 03:02:57 AM UTC 24 |
Oct 12 03:05:58 AM UTC 24 |
43121696345 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_regwen.2602548870 |
|
|
Oct 12 03:02:52 AM UTC 24 |
Oct 12 03:06:04 AM UTC 24 |
9765116994 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.4037371553 |
|
|
Oct 12 03:03:02 AM UTC 24 |
Oct 12 03:06:16 AM UTC 24 |
10187038466 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.2808489708 |
|
|
Oct 12 03:04:37 AM UTC 24 |
Oct 12 03:06:23 AM UTC 24 |
1601954243 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_smoke.996877586 |
|
|
Oct 12 03:05:54 AM UTC 24 |
Oct 12 03:06:25 AM UTC 24 |
1686295538 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.1041984961 |
|
|
Oct 12 03:00:19 AM UTC 24 |
Oct 12 03:06:36 AM UTC 24 |
20891768336 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.3358499514 |
|
|
Oct 12 03:06:25 AM UTC 24 |
Oct 12 03:06:38 AM UTC 24 |
718469605 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.2486408938 |
|
|
Oct 12 03:01:21 AM UTC 24 |
Oct 12 03:06:38 AM UTC 24 |
25469632931 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.1728916153 |
|
|
Oct 12 03:04:56 AM UTC 24 |
Oct 12 03:06:45 AM UTC 24 |
3133666431 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access.2076030817 |
|
|
Oct 12 03:06:17 AM UTC 24 |
Oct 12 03:06:57 AM UTC 24 |
1827532418 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all.979879404 |
|
|
Oct 12 02:37:15 AM UTC 24 |
Oct 12 03:07:00 AM UTC 24 |
144649092337 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.3147748278 |
|
|
Oct 12 03:07:01 AM UTC 24 |
Oct 12 03:07:08 AM UTC 24 |
346316239 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.3732639389 |
|
|
Oct 12 02:59:41 AM UTC 24 |
Oct 12 03:07:16 AM UTC 24 |
23202534277 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.2971429309 |
|
|
Oct 12 02:42:40 AM UTC 24 |
Oct 12 03:07:17 AM UTC 24 |
13524669317 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.3615314606 |
|
|
Oct 12 03:05:29 AM UTC 24 |
Oct 12 03:07:21 AM UTC 24 |
10928211364 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_readback_err.4168071061 |
|
|
Oct 12 03:07:17 AM UTC 24 |
Oct 12 03:07:28 AM UTC 24 |
1377122931 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2230960249 |
|
|
Oct 12 03:07:22 AM UTC 24 |
Oct 12 03:07:37 AM UTC 24 |
1078151218 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_alert_test.2577058374 |
|
|
Oct 12 03:07:38 AM UTC 24 |
Oct 12 03:07:40 AM UTC 24 |
37372987 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.1879026727 |
|
|
Oct 12 03:02:18 AM UTC 24 |
Oct 12 03:07:40 AM UTC 24 |
14191775785 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.3223444841 |
|
|
Oct 12 03:06:38 AM UTC 24 |
Oct 12 03:07:45 AM UTC 24 |
8098524146 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_smoke.2272109502 |
|
|
Oct 12 03:07:41 AM UTC 24 |
Oct 12 03:07:54 AM UTC 24 |
6514222724 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.4107608422 |
|
|
Oct 12 03:06:36 AM UTC 24 |
Oct 12 03:08:00 AM UTC 24 |
3206658915 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_regwen.2893068682 |
|
|
Oct 12 02:51:22 AM UTC 24 |
Oct 12 03:08:07 AM UTC 24 |
39351983089 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access.3636307115 |
|
|
Oct 12 03:08:00 AM UTC 24 |
Oct 12 03:08:15 AM UTC 24 |
793795223 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.362752210 |
|
|
Oct 12 03:05:06 AM UTC 24 |
Oct 12 03:08:20 AM UTC 24 |
105224956968 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.2434140434 |
|
|
Oct 12 03:03:40 AM UTC 24 |
Oct 12 03:08:24 AM UTC 24 |
7252430828 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.2805640298 |
|
|
Oct 12 03:08:16 AM UTC 24 |
Oct 12 03:08:29 AM UTC 24 |
1412904422 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.2915986130 |
|
|
Oct 12 03:07:17 AM UTC 24 |
Oct 12 03:08:42 AM UTC 24 |
2527488721 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.1716747601 |
|
|
Oct 12 02:58:38 AM UTC 24 |
Oct 12 03:09:00 AM UTC 24 |
46038281625 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.1656150993 |
|
|
Oct 12 03:05:24 AM UTC 24 |
Oct 12 03:09:04 AM UTC 24 |
36917227044 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.3048645283 |
|
|
Oct 12 03:09:05 AM UTC 24 |
Oct 12 03:09:11 AM UTC 24 |
1404253836 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.2764217705 |
|
|
Oct 12 02:55:58 AM UTC 24 |
Oct 12 03:09:14 AM UTC 24 |
32646869835 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.1833394761 |
|
|
Oct 12 03:08:21 AM UTC 24 |
Oct 12 03:09:15 AM UTC 24 |
765510142 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.3745273950 |
|
|
Oct 12 03:07:09 AM UTC 24 |
Oct 12 03:09:19 AM UTC 24 |
2440482634 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.97562367 |
|
|
Oct 12 02:51:14 AM UTC 24 |
Oct 12 03:09:25 AM UTC 24 |
15563651153 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_readback_err.3825891132 |
|
|
Oct 12 03:09:17 AM UTC 24 |
Oct 12 03:09:27 AM UTC 24 |
2649051689 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_alert_test.3925809680 |
|
|
Oct 12 03:09:27 AM UTC 24 |
Oct 12 03:09:29 AM UTC 24 |
16149922 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_executable.1395387054 |
|
|
Oct 12 02:54:02 AM UTC 24 |
Oct 12 03:09:46 AM UTC 24 |
15272750989 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.197250013 |
|
|
Oct 12 03:08:25 AM UTC 24 |
Oct 12 03:09:46 AM UTC 24 |
30721947692 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3612195859 |
|
|
Oct 12 03:09:20 AM UTC 24 |
Oct 12 03:09:52 AM UTC 24 |
13653184841 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_smoke.2228654557 |
|
|
Oct 12 03:09:30 AM UTC 24 |
Oct 12 03:10:06 AM UTC 24 |
6566309549 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.1384014583 |
|
|
Oct 12 03:01:21 AM UTC 24 |
Oct 12 03:10:12 AM UTC 24 |
12377131844 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_regwen.1879384233 |
|
|
Oct 12 03:09:01 AM UTC 24 |
Oct 12 03:10:24 AM UTC 24 |
16415198554 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access.2849219184 |
|
|
Oct 12 03:10:07 AM UTC 24 |
Oct 12 03:10:28 AM UTC 24 |
970981079 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_regwen.3744394923 |
|
|
Oct 12 02:54:03 AM UTC 24 |
Oct 12 03:10:31 AM UTC 24 |
12006241132 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.3659333025 |
|
|
Oct 12 03:05:07 AM UTC 24 |
Oct 12 03:10:39 AM UTC 24 |
24873523056 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.2794368907 |
|
|
Oct 12 02:56:40 AM UTC 24 |
Oct 12 03:10:40 AM UTC 24 |
8359876529 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.162949478 |
|
|
Oct 12 03:03:28 AM UTC 24 |
Oct 12 03:10:52 AM UTC 24 |
11910634745 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.2541097178 |
|
|
Oct 12 03:09:15 AM UTC 24 |
Oct 12 03:10:56 AM UTC 24 |
4018903774 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all.2620527986 |
|
|
Oct 12 03:05:45 AM UTC 24 |
Oct 12 03:10:56 AM UTC 24 |
143566045964 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.2700228137 |
|
|
Oct 12 03:10:57 AM UTC 24 |
Oct 12 03:11:03 AM UTC 24 |
705317544 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.1130660057 |
|
|
Oct 12 03:04:08 AM UTC 24 |
Oct 12 03:11:05 AM UTC 24 |
15304056136 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.280823883 |
|
|
Oct 12 03:07:55 AM UTC 24 |
Oct 12 03:11:11 AM UTC 24 |
12980260484 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_executable.1756904944 |
|
|
Oct 12 02:59:44 AM UTC 24 |
Oct 12 03:11:12 AM UTC 24 |
21758927825 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_readback_err.4072904199 |
|
|
Oct 12 03:11:06 AM UTC 24 |
Oct 12 03:11:18 AM UTC 24 |
680214670 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_alert_test.1228796520 |
|
|
Oct 12 03:11:18 AM UTC 24 |
Oct 12 03:11:20 AM UTC 24 |
14378257 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.3436793762 |
|
|
Oct 12 03:10:32 AM UTC 24 |
Oct 12 03:11:24 AM UTC 24 |
9216606262 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.3160625918 |
|
|
Oct 12 03:10:25 AM UTC 24 |
Oct 12 03:11:27 AM UTC 24 |
12535546016 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_regwen.1435365220 |
|
|
Oct 12 02:57:39 AM UTC 24 |
Oct 12 03:11:31 AM UTC 24 |
15486884162 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.3459671256 |
|
|
Oct 12 03:10:29 AM UTC 24 |
Oct 12 03:11:36 AM UTC 24 |
778818114 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.13970294 |
|
|
Oct 12 03:06:05 AM UTC 24 |
Oct 12 03:11:49 AM UTC 24 |
3591172983 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.3482287370 |
|
|
Oct 12 03:09:12 AM UTC 24 |
Oct 12 03:11:50 AM UTC 24 |
4113551326 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all.256432024 |
|
|
Oct 12 02:37:23 AM UTC 24 |
Oct 12 03:12:04 AM UTC 24 |
75011533532 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.3666488964 |
|
|
Oct 12 03:11:51 AM UTC 24 |
Oct 12 03:12:11 AM UTC 24 |
698070767 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_bijection.2294761660 |
|
|
Oct 12 02:37:53 AM UTC 24 |
Oct 12 03:12:12 AM UTC 24 |
431299573325 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.854472833 |
|
|
Oct 12 03:11:12 AM UTC 24 |
Oct 12 03:12:33 AM UTC 24 |
3670682959 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.2249515176 |
|
|
Oct 12 03:09:53 AM UTC 24 |
Oct 12 03:12:39 AM UTC 24 |
2699360091 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.1025838029 |
|
|
Oct 12 03:12:12 AM UTC 24 |
Oct 12 03:12:58 AM UTC 24 |
8794282184 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_smoke.550218261 |
|
|
Oct 12 03:11:21 AM UTC 24 |
Oct 12 03:13:08 AM UTC 24 |
1778458059 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.65846545 |
|
|
Oct 12 03:12:59 AM UTC 24 |
Oct 12 03:13:10 AM UTC 24 |
6722512045 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_bijection.297022596 |
|
|
Oct 12 02:48:21 AM UTC 24 |
Oct 12 03:13:11 AM UTC 24 |
74071775530 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_readback_err.3234909653 |
|
|
Oct 12 03:13:11 AM UTC 24 |
Oct 12 03:13:23 AM UTC 24 |
1387476544 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access.2021416490 |
|
|
Oct 12 03:11:37 AM UTC 24 |
Oct 12 03:13:27 AM UTC 24 |
993072992 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.3713641691 |
|
|
Oct 12 03:11:04 AM UTC 24 |
Oct 12 03:13:28 AM UTC 24 |
18361343063 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.1825253404 |
|
|
Oct 12 03:12:05 AM UTC 24 |
Oct 12 03:13:31 AM UTC 24 |
771930788 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_alert_test.843111088 |
|
|
Oct 12 03:13:29 AM UTC 24 |
Oct 12 03:13:31 AM UTC 24 |
23719869 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_bijection.2696343428 |
|
|
Oct 12 02:52:55 AM UTC 24 |
Oct 12 03:13:38 AM UTC 24 |
168745585787 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_smoke.3317664432 |
|
|
Oct 12 03:13:33 AM UTC 24 |
Oct 12 03:13:45 AM UTC 24 |
6093229574 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.601882737 |
|
|
Oct 12 03:08:08 AM UTC 24 |
Oct 12 03:13:47 AM UTC 24 |
12061359325 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.465078891 |
|
|
Oct 12 03:13:24 AM UTC 24 |
Oct 12 03:13:48 AM UTC 24 |
724915698 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_bijection.537643836 |
|
|
Oct 12 02:37:16 AM UTC 24 |
Oct 12 03:13:58 AM UTC 24 |
368662930362 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_bijection.3262003571 |
|
|
Oct 12 02:37:24 AM UTC 24 |
Oct 12 03:14:04 AM UTC 24 |
99708667940 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access.1976798811 |
|
|
Oct 12 03:13:48 AM UTC 24 |
Oct 12 03:14:23 AM UTC 24 |
4224518544 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.45560075 |
|
|
Oct 12 02:43:55 AM UTC 24 |
Oct 12 03:14:29 AM UTC 24 |
85467608416 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.658786819 |
|
|
Oct 12 03:10:57 AM UTC 24 |
Oct 12 03:14:33 AM UTC 24 |
31401413114 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.1746779543 |
|
|
Oct 12 03:14:05 AM UTC 24 |
Oct 12 03:14:34 AM UTC 24 |
1467467554 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.214927918 |
|
|
Oct 12 03:14:25 AM UTC 24 |
Oct 12 03:14:56 AM UTC 24 |
15032479919 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.3911563308 |
|
|
Oct 12 03:13:59 AM UTC 24 |
Oct 12 03:15:00 AM UTC 24 |
3054554325 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.3831323510 |
|
|
Oct 12 03:14:57 AM UTC 24 |
Oct 12 03:15:03 AM UTC 24 |
1408868712 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_executable.2588426750 |
|
|
Oct 12 03:12:33 AM UTC 24 |
Oct 12 03:15:34 AM UTC 24 |
1267625869 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.3582089130 |
|
|
Oct 12 03:13:11 AM UTC 24 |
Oct 12 03:15:43 AM UTC 24 |
6043862970 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_readback_err.572440823 |
|
|
Oct 12 03:15:34 AM UTC 24 |
Oct 12 03:15:46 AM UTC 24 |
684883216 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.1569970036 |
|
|
Oct 12 03:14:30 AM UTC 24 |
Oct 12 03:15:59 AM UTC 24 |
10908449767 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_alert_test.2901559924 |
|
|
Oct 12 03:16:00 AM UTC 24 |
Oct 12 03:16:02 AM UTC 24 |
134343374 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.3973110607 |
|
|
Oct 12 03:13:09 AM UTC 24 |
Oct 12 03:16:08 AM UTC 24 |
10684070375 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.1896216678 |
|
|
Oct 12 03:06:39 AM UTC 24 |
Oct 12 03:16:17 AM UTC 24 |
38237309723 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.684103968 |
|
|
Oct 12 02:38:43 AM UTC 24 |
Oct 12 03:16:22 AM UTC 24 |
496723309466 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2747144311 |
|
|
Oct 12 03:15:44 AM UTC 24 |
Oct 12 03:16:37 AM UTC 24 |
8964998712 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.379656316 |
|
|
Oct 12 03:13:46 AM UTC 24 |
Oct 12 03:16:45 AM UTC 24 |
2580584540 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_smoke.3751936376 |
|
|
Oct 12 03:16:03 AM UTC 24 |
Oct 12 03:16:50 AM UTC 24 |
3296790402 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.4063956070 |
|
|
Oct 12 03:15:04 AM UTC 24 |
Oct 12 03:16:52 AM UTC 24 |
2416163003 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access.2004290417 |
|
|
Oct 12 03:16:38 AM UTC 24 |
Oct 12 03:16:59 AM UTC 24 |
2779256533 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.596397774 |
|
|
Oct 12 03:01:16 AM UTC 24 |
Oct 12 03:17:00 AM UTC 24 |
164652058837 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_executable.2457445785 |
|
|
Oct 12 02:57:32 AM UTC 24 |
Oct 12 03:17:04 AM UTC 24 |
30815997676 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.2384979412 |
|
|
Oct 12 03:11:32 AM UTC 24 |
Oct 12 03:17:19 AM UTC 24 |
17583509762 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.3768183456 |
|
|
Oct 12 03:10:13 AM UTC 24 |
Oct 12 03:17:20 AM UTC 24 |
11705245645 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.2702688189 |
|
|
Oct 12 03:17:20 AM UTC 24 |
Oct 12 03:17:26 AM UTC 24 |
1256156613 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_regwen.3418030797 |
|
|
Oct 12 03:10:52 AM UTC 24 |
Oct 12 03:17:34 AM UTC 24 |
20542918962 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_bijection.254198986 |
|
|
Oct 12 02:49:50 AM UTC 24 |
Oct 12 03:17:40 AM UTC 24 |
131674558088 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.1419748961 |
|
|
Oct 12 03:06:24 AM UTC 24 |
Oct 12 03:17:42 AM UTC 24 |
90317172615 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.5076461 |
|
|
Oct 12 03:11:50 AM UTC 24 |
Oct 12 03:17:43 AM UTC 24 |
5016302624 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.4192944126 |
|
|
Oct 12 03:16:53 AM UTC 24 |
Oct 12 03:17:43 AM UTC 24 |
775628357 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_alert_test.737625260 |
|
|
Oct 12 03:17:44 AM UTC 24 |
Oct 12 03:17:46 AM UTC 24 |
45721156 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.29795333 |
|
|
Oct 12 03:16:51 AM UTC 24 |
Oct 12 03:17:49 AM UTC 24 |
1284898261 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_readback_err.332206235 |
|
|
Oct 12 03:17:41 AM UTC 24 |
Oct 12 03:17:52 AM UTC 24 |
1363646292 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.3802560159 |
|
|
Oct 12 03:17:00 AM UTC 24 |
Oct 12 03:18:01 AM UTC 24 |
36909080618 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_smoke.4141026275 |
|
|
Oct 12 03:17:47 AM UTC 24 |
Oct 12 03:18:04 AM UTC 24 |
692944882 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3084277888 |
|
|
Oct 12 03:17:44 AM UTC 24 |
Oct 12 03:18:16 AM UTC 24 |
1460673712 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.1319143286 |
|
|
Oct 12 03:13:49 AM UTC 24 |
Oct 12 03:18:22 AM UTC 24 |
5534201119 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_executable.1070877205 |
|
|
Oct 12 03:05:09 AM UTC 24 |
Oct 12 03:18:32 AM UTC 24 |
35032432381 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access.2240637138 |
|
|
Oct 12 03:18:06 AM UTC 24 |
Oct 12 03:18:48 AM UTC 24 |
463502069 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.500023009 |
|
|
Oct 12 03:10:40 AM UTC 24 |
Oct 12 03:18:51 AM UTC 24 |
8789671623 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.329044631 |
|
|
Oct 12 03:17:35 AM UTC 24 |
Oct 12 03:18:53 AM UTC 24 |
2002756800 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_executable.4069359393 |
|
|
Oct 12 03:14:34 AM UTC 24 |
Oct 12 03:19:05 AM UTC 24 |
4626426633 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.1504089326 |
|
|
Oct 12 02:47:49 AM UTC 24 |
Oct 12 03:19:16 AM UTC 24 |
219876680035 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.1836372436 |
|
|
Oct 12 03:19:17 AM UTC 24 |
Oct 12 03:19:23 AM UTC 24 |
352749615 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.2217994422 |
|
|
Oct 12 03:07:41 AM UTC 24 |
Oct 12 03:19:54 AM UTC 24 |
107552366902 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.2236404705 |
|
|
Oct 12 03:18:23 AM UTC 24 |
Oct 12 03:19:57 AM UTC 24 |
1596575029 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.70606128 |
|
|
Oct 12 03:18:33 AM UTC 24 |
Oct 12 03:19:58 AM UTC 24 |
805873636 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_readback_err.802618509 |
|
|
Oct 12 03:19:57 AM UTC 24 |
Oct 12 03:20:07 AM UTC 24 |
2768710168 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.383607397 |
|
|
Oct 12 03:18:49 AM UTC 24 |
Oct 12 03:20:10 AM UTC 24 |
9948273137 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_alert_test.828191268 |
|
|
Oct 12 03:20:11 AM UTC 24 |
Oct 12 03:20:13 AM UTC 24 |
24167719 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.2388661711 |
|
|
Oct 12 03:17:27 AM UTC 24 |
Oct 12 03:20:26 AM UTC 24 |
43132757094 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.199346031 |
|
|
Oct 12 03:19:58 AM UTC 24 |
Oct 12 03:20:30 AM UTC 24 |
2641966785 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_smoke.562310854 |
|
|
Oct 12 03:20:14 AM UTC 24 |
Oct 12 03:20:33 AM UTC 24 |
1737070040 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.4160413706 |
|
|
Oct 12 03:15:00 AM UTC 24 |
Oct 12 03:20:38 AM UTC 24 |
28200679151 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_executable.3158899267 |
|
|
Oct 12 03:06:46 AM UTC 24 |
Oct 12 03:20:40 AM UTC 24 |
22509350981 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access.4138234240 |
|
|
Oct 12 03:20:39 AM UTC 24 |
Oct 12 03:20:47 AM UTC 24 |
2001682434 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.2374103082 |
|
|
Oct 12 03:08:30 AM UTC 24 |
Oct 12 03:20:56 AM UTC 24 |
46079993613 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.2413707555 |
|
|
Oct 12 03:20:57 AM UTC 24 |
Oct 12 03:21:19 AM UTC 24 |
2988199549 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.484157370 |
|
|
Oct 12 03:20:48 AM UTC 24 |
Oct 12 03:21:33 AM UTC 24 |
759116073 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.1202668043 |
|
|
Oct 12 03:11:24 AM UTC 24 |
Oct 12 03:21:37 AM UTC 24 |
21708685069 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.683903451 |
|
|
Oct 12 03:18:03 AM UTC 24 |
Oct 12 03:21:59 AM UTC 24 |
37305438971 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.2227547744 |
|
|
Oct 12 03:19:24 AM UTC 24 |
Oct 12 03:22:20 AM UTC 24 |
8440725456 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_bijection.4244484273 |
|
|
Oct 12 02:55:02 AM UTC 24 |
Oct 12 03:22:24 AM UTC 24 |
586496468338 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.2153435724 |
|
|
Oct 12 03:22:21 AM UTC 24 |
Oct 12 03:22:27 AM UTC 24 |
346677806 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.1881231156 |
|
|
Oct 12 03:16:22 AM UTC 24 |
Oct 12 03:22:47 AM UTC 24 |
4745278387 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_readback_err.1594456137 |
|
|
Oct 12 03:22:48 AM UTC 24 |
Oct 12 03:22:57 AM UTC 24 |
1379582707 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.561335283 |
|
|
Oct 12 03:19:55 AM UTC 24 |
Oct 12 03:23:03 AM UTC 24 |
70389900818 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3467125077 |
|
|
Oct 12 03:22:58 AM UTC 24 |
Oct 12 03:23:18 AM UTC 24 |
360568877 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_regwen.3420033306 |
|
|
Oct 12 03:14:35 AM UTC 24 |
Oct 12 03:23:21 AM UTC 24 |
14849917654 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_alert_test.1501236439 |
|
|
Oct 12 03:23:19 AM UTC 24 |
Oct 12 03:23:21 AM UTC 24 |
15436221 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_bijection.52490914 |
|
|
Oct 12 03:11:28 AM UTC 24 |
Oct 12 03:23:38 AM UTC 24 |
28163730238 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.863577961 |
|
|
Oct 12 03:23:22 AM UTC 24 |
Oct 12 03:23:47 AM UTC 24 |
896868184 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.2527023754 |
|
|
Oct 12 03:12:12 AM UTC 24 |
Oct 12 03:23:56 AM UTC 24 |
19029693439 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_regwen.1293119982 |
|
|
Oct 12 03:06:58 AM UTC 24 |
Oct 12 03:24:03 AM UTC 24 |
13527837111 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.549707202 |
|
|
Oct 12 03:21:21 AM UTC 24 |
Oct 12 03:24:10 AM UTC 24 |
18388803959 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access.2979484502 |
|
|
Oct 12 03:23:57 AM UTC 24 |
Oct 12 03:24:15 AM UTC 24 |
823531225 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.4188607967 |
|
|
Oct 12 03:22:28 AM UTC 24 |
Oct 12 03:24:17 AM UTC 24 |
10708280941 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.3048013424 |
|
|
Oct 12 03:20:27 AM UTC 24 |
Oct 12 03:24:21 AM UTC 24 |
20939436118 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.1728841203 |
|
|
Oct 12 03:24:10 AM UTC 24 |
Oct 12 03:24:37 AM UTC 24 |
2965885230 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_regwen.1875500226 |
|
|
Oct 12 03:19:06 AM UTC 24 |
Oct 12 03:24:58 AM UTC 24 |
2063184177 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_smoke.3779024068 |
|
|
Oct 12 03:23:22 AM UTC 24 |
Oct 12 03:25:07 AM UTC 24 |
6983080645 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.3380443313 |
|
|
Oct 12 03:25:08 AM UTC 24 |
Oct 12 03:25:13 AM UTC 24 |
1605130212 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.507503444 |
|
|
Oct 12 03:24:16 AM UTC 24 |
Oct 12 03:25:30 AM UTC 24 |
10705329019 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all.1951456215 |
|
|
Oct 12 03:15:48 AM UTC 24 |
Oct 12 03:25:39 AM UTC 24 |
84336353849 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.2410201 |
|
|
Oct 12 03:22:25 AM UTC 24 |
Oct 12 03:25:42 AM UTC 24 |
43148746211 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_readback_err.1415035589 |
|
|
Oct 12 03:25:40 AM UTC 24 |
Oct 12 03:25:52 AM UTC 24 |
2131448675 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.2030890193 |
|
|
Oct 12 03:05:56 AM UTC 24 |
Oct 12 03:25:53 AM UTC 24 |
23499748278 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3361530797 |
|
|
Oct 12 03:25:42 AM UTC 24 |
Oct 12 03:25:55 AM UTC 24 |
412986953 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_alert_test.208527340 |
|
|
Oct 12 03:25:54 AM UTC 24 |
Oct 12 03:25:56 AM UTC 24 |
12908003 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.1410138126 |
|
|
Oct 12 03:20:41 AM UTC 24 |
Oct 12 03:25:56 AM UTC 24 |
12742145543 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_bijection.581447248 |
|
|
Oct 12 03:16:18 AM UTC 24 |
Oct 12 03:25:57 AM UTC 24 |
20294830141 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.1911845704 |
|
|
Oct 12 03:24:17 AM UTC 24 |
Oct 12 03:25:59 AM UTC 24 |
39661516566 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_regwen.3583888466 |
|
|
Oct 12 03:12:40 AM UTC 24 |
Oct 12 03:26:02 AM UTC 24 |
4303212496 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.4195152915 |
|
|
Oct 12 03:24:22 AM UTC 24 |
Oct 12 03:26:05 AM UTC 24 |
4050423397 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.3271864382 |
|
|
Oct 12 03:20:34 AM UTC 24 |
Oct 12 03:26:07 AM UTC 24 |
5015352945 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_smoke.3459487890 |
|
|
Oct 12 03:25:56 AM UTC 24 |
Oct 12 03:26:11 AM UTC 24 |
1054977387 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access.3909253242 |
|
|
Oct 12 03:26:00 AM UTC 24 |
Oct 12 03:26:18 AM UTC 24 |
4898482858 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.557978624 |
|
|
Oct 12 03:26:06 AM UTC 24 |
Oct 12 03:26:19 AM UTC 24 |
705338322 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.1135442154 |
|
|
Oct 12 03:25:57 AM UTC 24 |
Oct 12 03:26:21 AM UTC 24 |
1172714495 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_regwen.2923869392 |
|
|
Oct 12 03:05:10 AM UTC 24 |
Oct 12 03:26:37 AM UTC 24 |
4130664702 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_bijection.1707890763 |
|
|
Oct 12 03:09:46 AM UTC 24 |
Oct 12 03:26:39 AM UTC 24 |
67099192765 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.2553029282 |
|
|
Oct 12 03:17:50 AM UTC 24 |
Oct 12 03:26:40 AM UTC 24 |
22032179333 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.4173945336 |
|
|
Oct 12 03:26:38 AM UTC 24 |
Oct 12 03:26:43 AM UTC 24 |
539444437 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.588017327 |
|
|
Oct 12 03:26:12 AM UTC 24 |
Oct 12 03:26:47 AM UTC 24 |
4864198284 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_readback_err.1358171495 |
|
|
Oct 12 03:26:43 AM UTC 24 |
Oct 12 03:26:55 AM UTC 24 |
711947865 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_bijection.803393823 |
|
|
Oct 12 03:01:19 AM UTC 24 |
Oct 12 03:27:06 AM UTC 24 |
518240926695 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_alert_test.2132898510 |
|
|
Oct 12 03:27:07 AM UTC 24 |
Oct 12 03:27:09 AM UTC 24 |
19742206 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.1490376387 |
|
|
Oct 12 03:26:07 AM UTC 24 |
Oct 12 03:27:11 AM UTC 24 |
832438769 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.757949598 |
|
|
Oct 12 03:09:46 AM UTC 24 |
Oct 12 03:27:12 AM UTC 24 |
20847847511 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_bijection.2501087778 |
|
|
Oct 12 02:58:38 AM UTC 24 |
Oct 12 03:27:13 AM UTC 24 |
47144468586 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_smoke.4095938993 |
|
|
Oct 12 03:27:10 AM UTC 24 |
Oct 12 03:27:29 AM UTC 24 |
777462430 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.1113799707 |
|
|
Oct 12 03:16:46 AM UTC 24 |
Oct 12 03:27:33 AM UTC 24 |
24117463575 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.1989969845 |
|
|
Oct 12 02:46:20 AM UTC 24 |
Oct 12 03:27:46 AM UTC 24 |
132425391368 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.1067959911 |
|
|
Oct 12 03:18:17 AM UTC 24 |
Oct 12 03:27:57 AM UTC 24 |
22888379738 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.449528689 |
|
|
Oct 12 02:41:42 AM UTC 24 |
Oct 12 03:28:01 AM UTC 24 |
110042080651 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.3480097840 |
|
|
Oct 12 03:27:48 AM UTC 24 |
Oct 12 03:28:01 AM UTC 24 |
681857191 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.4070401688 |
|
|
Oct 12 03:26:48 AM UTC 24 |
Oct 12 03:28:04 AM UTC 24 |
6379631782 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access.3114024104 |
|
|
Oct 12 03:27:29 AM UTC 24 |
Oct 12 03:28:08 AM UTC 24 |
2353148140 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_executable.4242030943 |
|
|
Oct 12 03:17:04 AM UTC 24 |
Oct 12 03:28:23 AM UTC 24 |
5422388785 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.2772107042 |
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Oct 12 03:25:14 AM UTC 24 |
Oct 12 03:28:29 AM UTC 24 |
3521121777 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.2217860151 |
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Oct 12 03:28:24 AM UTC 24 |
Oct 12 03:28:31 AM UTC 24 |
2101168033 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.2650811977 |
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Oct 12 03:26:41 AM UTC 24 |
Oct 12 03:28:43 AM UTC 24 |
3275717274 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.2379883532 |
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Oct 12 03:25:31 AM UTC 24 |
Oct 12 03:28:51 AM UTC 24 |
20020613374 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_readback_err.2294398051 |
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Oct 12 03:28:44 AM UTC 24 |
Oct 12 03:28:56 AM UTC 24 |
1378661081 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.2751013394 |
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Oct 12 03:13:33 AM UTC 24 |
Oct 12 03:29:00 AM UTC 24 |
66898063054 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.841401108 |
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Oct 12 03:16:08 AM UTC 24 |
Oct 12 03:29:01 AM UTC 24 |
67759905680 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.1412733265 |
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Oct 12 03:18:51 AM UTC 24 |
Oct 12 03:29:02 AM UTC 24 |
6375138666 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_alert_test.224652442 |
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Oct 12 03:29:01 AM UTC 24 |
Oct 12 03:29:03 AM UTC 24 |
14906944 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.2047742462 |
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Oct 12 03:24:04 AM UTC 24 |
Oct 12 03:29:07 AM UTC 24 |
103776035575 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_smoke.3910251474 |
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Oct 12 03:29:02 AM UTC 24 |
Oct 12 03:29:10 AM UTC 24 |
2416511528 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.3577500803 |
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Oct 12 03:27:58 AM UTC 24 |
Oct 12 03:29:10 AM UTC 24 |
3071589349 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.336016524 |
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Oct 12 03:23:48 AM UTC 24 |
Oct 12 03:29:13 AM UTC 24 |
3636994378 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access.1331809939 |
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Oct 12 03:29:10 AM UTC 24 |
Oct 12 03:29:19 AM UTC 24 |
1461954554 ps |