| T793 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all.915814370 |
|
|
Oct 12 02:57:57 AM UTC 24 |
Oct 12 04:03:25 AM UTC 24 |
66381732821 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.3102240399 |
|
|
Oct 12 04:02:57 AM UTC 24 |
Oct 12 04:03:34 AM UTC 24 |
9034300989 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.2354003446 |
|
|
Oct 12 03:51:34 AM UTC 24 |
Oct 12 04:03:40 AM UTC 24 |
33850676608 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.21617027 |
|
|
Oct 12 03:58:37 AM UTC 24 |
Oct 12 04:03:47 AM UTC 24 |
13961371720 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.1062086936 |
|
|
Oct 12 04:03:41 AM UTC 24 |
Oct 12 04:03:51 AM UTC 24 |
5610930776 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access.2434772779 |
|
|
Oct 12 04:02:36 AM UTC 24 |
Oct 12 04:03:59 AM UTC 24 |
4639835728 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_executable.3482705117 |
|
|
Oct 12 03:55:26 AM UTC 24 |
Oct 12 04:04:04 AM UTC 24 |
11563523962 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_readback_err.1700269403 |
|
|
Oct 12 04:04:00 AM UTC 24 |
Oct 12 04:04:12 AM UTC 24 |
5067081495 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.2259687451 |
|
|
Oct 12 04:01:14 AM UTC 24 |
Oct 12 04:04:23 AM UTC 24 |
7137271395 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all.13055595 |
|
|
Oct 12 03:13:27 AM UTC 24 |
Oct 12 04:04:24 AM UTC 24 |
289289601149 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_alert_test.294067677 |
|
|
Oct 12 04:04:24 AM UTC 24 |
Oct 12 04:04:26 AM UTC 24 |
12807230 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1705316163 |
|
|
Oct 12 04:04:05 AM UTC 24 |
Oct 12 04:04:30 AM UTC 24 |
438016672 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_regwen.3213353807 |
|
|
Oct 12 03:44:02 AM UTC 24 |
Oct 12 04:04:34 AM UTC 24 |
7449009170 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_smoke.70741530 |
|
|
Oct 12 04:04:25 AM UTC 24 |
Oct 12 04:04:46 AM UTC 24 |
958513864 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all.3216969745 |
|
|
Oct 12 03:26:56 AM UTC 24 |
Oct 12 04:04:48 AM UTC 24 |
105977149950 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.1248907036 |
|
|
Oct 12 04:03:10 AM UTC 24 |
Oct 12 04:04:52 AM UTC 24 |
8171819059 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.1226006041 |
|
|
Oct 12 04:04:53 AM UTC 24 |
Oct 12 04:05:04 AM UTC 24 |
704539298 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.3523289349 |
|
|
Oct 12 04:03:52 AM UTC 24 |
Oct 12 04:05:28 AM UTC 24 |
2337872967 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access.1269786793 |
|
|
Oct 12 04:04:47 AM UTC 24 |
Oct 12 04:05:30 AM UTC 24 |
794773198 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_bijection.2378861721 |
|
|
Oct 12 03:51:37 AM UTC 24 |
Oct 12 04:05:48 AM UTC 24 |
24767223121 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_regwen.2384568817 |
|
|
Oct 12 04:03:35 AM UTC 24 |
Oct 12 04:05:48 AM UTC 24 |
1738619715 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.2026766912 |
|
|
Oct 12 04:04:27 AM UTC 24 |
Oct 12 04:05:58 AM UTC 24 |
12367455675 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.448811827 |
|
|
Oct 12 03:57:10 AM UTC 24 |
Oct 12 04:05:59 AM UTC 24 |
20254472168 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.2157414543 |
|
|
Oct 12 04:05:59 AM UTC 24 |
Oct 12 04:06:07 AM UTC 24 |
1600793722 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.3146631777 |
|
|
Oct 12 04:05:05 AM UTC 24 |
Oct 12 04:06:08 AM UTC 24 |
3111457634 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.613661465 |
|
|
Oct 12 04:03:16 AM UTC 24 |
Oct 12 04:06:19 AM UTC 24 |
17182103143 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_readback_err.3826759093 |
|
|
Oct 12 04:06:09 AM UTC 24 |
Oct 12 04:06:20 AM UTC 24 |
2750863679 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.1457473710 |
|
|
Oct 12 03:59:52 AM UTC 24 |
Oct 12 04:06:28 AM UTC 24 |
11109767133 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_alert_test.1421529785 |
|
|
Oct 12 04:06:29 AM UTC 24 |
Oct 12 04:06:31 AM UTC 24 |
19080647 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.521669408 |
|
|
Oct 12 04:05:28 AM UTC 24 |
Oct 12 04:06:50 AM UTC 24 |
10266492644 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3394335638 |
|
|
Oct 12 04:06:20 AM UTC 24 |
Oct 12 04:06:54 AM UTC 24 |
1724663096 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_regwen.1275278396 |
|
|
Oct 12 03:52:41 AM UTC 24 |
Oct 12 04:07:02 AM UTC 24 |
3938515539 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_smoke.2843031481 |
|
|
Oct 12 04:06:32 AM UTC 24 |
Oct 12 04:07:20 AM UTC 24 |
1179042345 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.1277859721 |
|
|
Oct 12 03:58:08 AM UTC 24 |
Oct 12 04:07:20 AM UTC 24 |
16253449061 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.2848936342 |
|
|
Oct 12 04:06:08 AM UTC 24 |
Oct 12 04:07:34 AM UTC 24 |
9797473890 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.2293256863 |
|
|
Oct 12 03:52:20 AM UTC 24 |
Oct 12 04:07:34 AM UTC 24 |
18740729809 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_regwen.3970203915 |
|
|
Oct 12 04:00:58 AM UTC 24 |
Oct 12 04:07:43 AM UTC 24 |
10944644538 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.2070850991 |
|
|
Oct 12 04:07:35 AM UTC 24 |
Oct 12 04:07:50 AM UTC 24 |
2975795486 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access.4077174921 |
|
|
Oct 12 04:07:20 AM UTC 24 |
Oct 12 04:07:51 AM UTC 24 |
939261842 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_regwen.592132120 |
|
|
Oct 12 03:58:23 AM UTC 24 |
Oct 12 04:07:59 AM UTC 24 |
80690725683 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.3069094930 |
|
|
Oct 12 04:07:44 AM UTC 24 |
Oct 12 04:08:07 AM UTC 24 |
1975342975 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.739431604 |
|
|
Oct 12 04:02:34 AM UTC 24 |
Oct 12 04:08:10 AM UTC 24 |
4703940686 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.2681778306 |
|
|
Oct 12 04:03:47 AM UTC 24 |
Oct 12 04:08:14 AM UTC 24 |
15755939594 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.4280611293 |
|
|
Oct 12 04:08:08 AM UTC 24 |
Oct 12 04:08:15 AM UTC 24 |
1544942395 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.714920690 |
|
|
Oct 12 04:07:35 AM UTC 24 |
Oct 12 04:08:24 AM UTC 24 |
3086441485 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_readback_err.951097859 |
|
|
Oct 12 04:08:17 AM UTC 24 |
Oct 12 04:08:28 AM UTC 24 |
696887072 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_bijection.1825896408 |
|
|
Oct 12 03:27:13 AM UTC 24 |
Oct 12 04:08:41 AM UTC 24 |
223056827501 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3247720015 |
|
|
Oct 12 04:08:25 AM UTC 24 |
Oct 12 04:08:41 AM UTC 24 |
394375338 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_alert_test.2008288848 |
|
|
Oct 12 04:08:42 AM UTC 24 |
Oct 12 04:08:44 AM UTC 24 |
20930076 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_executable.1881883067 |
|
|
Oct 12 04:00:52 AM UTC 24 |
Oct 12 04:09:06 AM UTC 24 |
35861631499 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.2347518518 |
|
|
Oct 12 04:00:27 AM UTC 24 |
Oct 12 04:09:07 AM UTC 24 |
12163422182 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_smoke.1728983135 |
|
|
Oct 12 04:08:42 AM UTC 24 |
Oct 12 04:09:07 AM UTC 24 |
3486787154 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access.3600888005 |
|
|
Oct 12 04:09:09 AM UTC 24 |
Oct 12 04:09:16 AM UTC 24 |
1555373607 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.2714008941 |
|
|
Oct 12 03:42:37 AM UTC 24 |
Oct 12 04:09:16 AM UTC 24 |
10780846690 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_bijection.1541339453 |
|
|
Oct 12 03:25:57 AM UTC 24 |
Oct 12 04:09:17 AM UTC 24 |
402964104280 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.3792108988 |
|
|
Oct 12 04:09:18 AM UTC 24 |
Oct 12 04:09:34 AM UTC 24 |
6260906303 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.3931315083 |
|
|
Oct 12 04:02:43 AM UTC 24 |
Oct 12 04:09:48 AM UTC 24 |
7390980076 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.3900624888 |
|
|
Oct 12 04:09:17 AM UTC 24 |
Oct 12 04:09:56 AM UTC 24 |
1241353354 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.2708510987 |
|
|
Oct 12 04:08:14 AM UTC 24 |
Oct 12 04:10:17 AM UTC 24 |
10722616927 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.2966070988 |
|
|
Oct 12 03:59:37 AM UTC 24 |
Oct 12 04:10:29 AM UTC 24 |
23468008958 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.829293053 |
|
|
Oct 12 04:10:30 AM UTC 24 |
Oct 12 04:10:36 AM UTC 24 |
350286780 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.4278457062 |
|
|
Oct 12 04:06:00 AM UTC 24 |
Oct 12 04:10:38 AM UTC 24 |
6683432708 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.818430649 |
|
|
Oct 12 03:55:10 AM UTC 24 |
Oct 12 04:10:39 AM UTC 24 |
18216717716 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_readback_err.2147099011 |
|
|
Oct 12 04:10:41 AM UTC 24 |
Oct 12 04:10:52 AM UTC 24 |
13169251098 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.454161426 |
|
|
Oct 12 04:07:03 AM UTC 24 |
Oct 12 04:11:03 AM UTC 24 |
39505665295 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.2540691015 |
|
|
Oct 12 04:09:49 AM UTC 24 |
Oct 12 04:11:07 AM UTC 24 |
1679137195 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_alert_test.1616773309 |
|
|
Oct 12 04:14:08 AM UTC 24 |
Oct 12 04:14:10 AM UTC 24 |
35015490 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_bijection.468603317 |
|
|
Oct 12 03:37:45 AM UTC 24 |
Oct 12 04:11:10 AM UTC 24 |
46220775238 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_alert_test.2588221653 |
|
|
Oct 12 04:11:08 AM UTC 24 |
Oct 12 04:11:10 AM UTC 24 |
12610343 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.1361379989 |
|
|
Oct 12 04:04:49 AM UTC 24 |
Oct 12 04:11:13 AM UTC 24 |
6525492377 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2376563366 |
|
|
Oct 12 04:10:53 AM UTC 24 |
Oct 12 04:11:38 AM UTC 24 |
9495864371 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.3442654680 |
|
|
Oct 12 04:09:35 AM UTC 24 |
Oct 12 04:11:38 AM UTC 24 |
20532400546 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_smoke.1361727950 |
|
|
Oct 12 04:11:10 AM UTC 24 |
Oct 12 04:11:40 AM UTC 24 |
1514553810 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_bijection.514290358 |
|
|
Oct 12 03:42:37 AM UTC 24 |
Oct 12 04:11:42 AM UTC 24 |
75225817449 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_regwen.1425338451 |
|
|
Oct 12 04:10:17 AM UTC 24 |
Oct 12 04:11:50 AM UTC 24 |
6658947599 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access.3472171581 |
|
|
Oct 12 04:11:39 AM UTC 24 |
Oct 12 04:12:10 AM UTC 24 |
5293139617 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all.3844363426 |
|
|
Oct 12 02:54:47 AM UTC 24 |
Oct 12 04:12:23 AM UTC 24 |
119983349855 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.375362282 |
|
|
Oct 12 04:11:50 AM UTC 24 |
Oct 12 04:12:40 AM UTC 24 |
765633431 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.2536537786 |
|
|
Oct 12 04:04:35 AM UTC 24 |
Oct 12 04:12:51 AM UTC 24 |
5435333082 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.4116482920 |
|
|
Oct 12 04:11:42 AM UTC 24 |
Oct 12 04:12:52 AM UTC 24 |
3088793308 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.1583810917 |
|
|
Oct 12 04:12:53 AM UTC 24 |
Oct 12 04:13:00 AM UTC 24 |
368118642 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.3573221769 |
|
|
Oct 12 04:10:39 AM UTC 24 |
Oct 12 04:13:02 AM UTC 24 |
24273709774 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.2095929912 |
|
|
Oct 12 04:10:37 AM UTC 24 |
Oct 12 04:13:13 AM UTC 24 |
7311414131 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_readback_err.2794389320 |
|
|
Oct 12 04:13:14 AM UTC 24 |
Oct 12 04:13:24 AM UTC 24 |
3136301406 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3718955280 |
|
|
Oct 12 04:13:25 AM UTC 24 |
Oct 12 04:13:43 AM UTC 24 |
320765328 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.1382470586 |
|
|
Oct 12 04:09:08 AM UTC 24 |
Oct 12 04:14:07 AM UTC 24 |
41228053424 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.693250665 |
|
|
Oct 12 04:12:11 AM UTC 24 |
Oct 12 04:14:14 AM UTC 24 |
24655106104 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.3368893773 |
|
|
Oct 12 04:13:03 AM UTC 24 |
Oct 12 04:14:23 AM UTC 24 |
1432282051 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all.716353778 |
|
|
Oct 12 03:25:53 AM UTC 24 |
Oct 12 04:14:37 AM UTC 24 |
127630919993 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_smoke.3065193921 |
|
|
Oct 12 04:14:11 AM UTC 24 |
Oct 12 04:14:38 AM UTC 24 |
1808646232 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access.3130079072 |
|
|
Oct 12 04:14:38 AM UTC 24 |
Oct 12 04:14:47 AM UTC 24 |
375609742 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_bijection.1179048173 |
|
|
Oct 12 03:39:45 AM UTC 24 |
Oct 12 04:15:02 AM UTC 24 |
182358679022 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.1091171660 |
|
|
Oct 12 04:14:48 AM UTC 24 |
Oct 12 04:15:04 AM UTC 24 |
2707481413 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.1028676572 |
|
|
Oct 12 04:11:39 AM UTC 24 |
Oct 12 04:15:12 AM UTC 24 |
3865006925 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.3168297210 |
|
|
Oct 12 04:15:03 AM UTC 24 |
Oct 12 04:15:14 AM UTC 24 |
890067278 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_bijection.1150837903 |
|
|
Oct 12 04:02:33 AM UTC 24 |
Oct 12 04:15:34 AM UTC 24 |
12320383182 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.1775826570 |
|
|
Oct 12 04:11:40 AM UTC 24 |
Oct 12 04:15:50 AM UTC 24 |
9209191224 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.764964929 |
|
|
Oct 12 04:15:51 AM UTC 24 |
Oct 12 04:15:57 AM UTC 24 |
363188401 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.2803553446 |
|
|
Oct 12 04:08:10 AM UTC 24 |
Oct 12 04:16:11 AM UTC 24 |
73888530680 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.3317887375 |
|
|
Oct 12 04:02:25 AM UTC 24 |
Oct 12 04:16:12 AM UTC 24 |
257685469598 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_readback_err.3289746050 |
|
|
Oct 12 04:16:13 AM UTC 24 |
Oct 12 04:16:25 AM UTC 24 |
2753539484 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_regwen.1916827928 |
|
|
Oct 12 04:05:49 AM UTC 24 |
Oct 12 04:16:27 AM UTC 24 |
57339184409 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.1828494105 |
|
|
Oct 12 04:15:05 AM UTC 24 |
Oct 12 04:16:34 AM UTC 24 |
27054009081 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_alert_test.1464677767 |
|
|
Oct 12 04:16:35 AM UTC 24 |
Oct 12 04:16:38 AM UTC 24 |
24472117 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_smoke.2916836100 |
|
|
Oct 12 04:16:38 AM UTC 24 |
Oct 12 04:16:45 AM UTC 24 |
677469873 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.605206118 |
|
|
Oct 12 04:08:45 AM UTC 24 |
Oct 12 04:16:59 AM UTC 24 |
76143882106 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_bijection.482958067 |
|
|
Oct 12 03:53:40 AM UTC 24 |
Oct 12 04:17:16 AM UTC 24 |
178596036097 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.2807256267 |
|
|
Oct 12 04:15:12 AM UTC 24 |
Oct 12 04:17:21 AM UTC 24 |
13029341267 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access.1950513200 |
|
|
Oct 12 04:17:21 AM UTC 24 |
Oct 12 04:17:43 AM UTC 24 |
3897942577 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.81473874 |
|
|
Oct 12 04:00:51 AM UTC 24 |
Oct 12 04:18:03 AM UTC 24 |
15919350216 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.1434171825 |
|
|
Oct 12 04:05:30 AM UTC 24 |
Oct 12 04:18:06 AM UTC 24 |
121261277497 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.439967010 |
|
|
Oct 12 04:14:40 AM UTC 24 |
Oct 12 04:18:12 AM UTC 24 |
3593495069 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.248407484 |
|
|
Oct 12 03:53:28 AM UTC 24 |
Oct 12 04:18:20 AM UTC 24 |
28403323629 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_executable.2533335715 |
|
|
Oct 12 04:12:41 AM UTC 24 |
Oct 12 04:18:25 AM UTC 24 |
26478377367 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.2879845238 |
|
|
Oct 12 04:18:07 AM UTC 24 |
Oct 12 04:18:37 AM UTC 24 |
815616695 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2116842207 |
|
|
Oct 12 04:16:26 AM UTC 24 |
Oct 12 04:18:40 AM UTC 24 |
23645931324 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.3064131193 |
|
|
Oct 12 04:18:13 AM UTC 24 |
Oct 12 04:18:41 AM UTC 24 |
2255633259 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.4154551927 |
|
|
Oct 12 04:06:51 AM UTC 24 |
Oct 12 04:18:41 AM UTC 24 |
156968432497 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_executable.3411662215 |
|
|
Oct 12 04:03:26 AM UTC 24 |
Oct 12 04:18:45 AM UTC 24 |
36553287755 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.135022196 |
|
|
Oct 12 04:18:41 AM UTC 24 |
Oct 12 04:18:48 AM UTC 24 |
1353971056 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.2187033015 |
|
|
Oct 12 04:18:03 AM UTC 24 |
Oct 12 04:18:52 AM UTC 24 |
735317306 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_readback_err.3426966396 |
|
|
Oct 12 04:18:46 AM UTC 24 |
Oct 12 04:18:58 AM UTC 24 |
689817699 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_alert_test.3658867385 |
|
|
Oct 12 04:18:59 AM UTC 24 |
Oct 12 04:19:01 AM UTC 24 |
26642009 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.1914521323 |
|
|
Oct 12 04:14:23 AM UTC 24 |
Oct 12 04:19:11 AM UTC 24 |
4939853845 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2428612153 |
|
|
Oct 12 04:18:49 AM UTC 24 |
Oct 12 04:19:12 AM UTC 24 |
427047393 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_executable.2251285530 |
|
|
Oct 12 04:05:49 AM UTC 24 |
Oct 12 04:19:13 AM UTC 24 |
82172818228 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.3140777825 |
|
|
Oct 12 04:13:00 AM UTC 24 |
Oct 12 04:19:14 AM UTC 24 |
57641984350 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.2969117900 |
|
|
Oct 12 04:16:12 AM UTC 24 |
Oct 12 04:19:15 AM UTC 24 |
5478671053 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.2059143082 |
|
|
Oct 12 04:09:17 AM UTC 24 |
Oct 12 04:19:26 AM UTC 24 |
87558026686 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access.1671448149 |
|
|
Oct 12 04:19:15 AM UTC 24 |
Oct 12 04:19:34 AM UTC 24 |
774313265 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_smoke.843202032 |
|
|
Oct 12 04:19:02 AM UTC 24 |
Oct 12 04:20:16 AM UTC 24 |
3391781962 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.811300874 |
|
|
Oct 12 04:19:27 AM UTC 24 |
Oct 12 04:20:20 AM UTC 24 |
1381188328 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_executable.746714027 |
|
|
Oct 12 04:07:52 AM UTC 24 |
Oct 12 04:20:48 AM UTC 24 |
9279000105 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.3873715454 |
|
|
Oct 12 04:19:34 AM UTC 24 |
Oct 12 04:21:03 AM UTC 24 |
3548699690 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.2246234498 |
|
|
Oct 12 03:56:04 AM UTC 24 |
Oct 12 04:21:07 AM UTC 24 |
11158081772 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_executable.3197537797 |
|
|
Oct 12 04:09:57 AM UTC 24 |
Oct 12 04:21:14 AM UTC 24 |
15208185191 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.227173700 |
|
|
Oct 12 04:21:08 AM UTC 24 |
Oct 12 04:21:14 AM UTC 24 |
1409627322 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.3519095765 |
|
|
Oct 12 04:18:42 AM UTC 24 |
Oct 12 04:21:43 AM UTC 24 |
1748140706 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_regwen.4152257371 |
|
|
Oct 12 04:18:38 AM UTC 24 |
Oct 12 04:21:45 AM UTC 24 |
5989609615 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_bijection.4057961286 |
|
|
Oct 12 03:56:35 AM UTC 24 |
Oct 12 04:21:52 AM UTC 24 |
222192053215 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_readback_err.212700536 |
|
|
Oct 12 04:21:44 AM UTC 24 |
Oct 12 04:21:57 AM UTC 24 |
1324626243 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.1065544683 |
|
|
Oct 12 04:18:42 AM UTC 24 |
Oct 12 04:21:57 AM UTC 24 |
27644231507 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_alert_test.2898903868 |
|
|
Oct 12 04:21:57 AM UTC 24 |
Oct 12 04:22:00 AM UTC 24 |
16644838 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.1047797403 |
|
|
Oct 12 04:20:17 AM UTC 24 |
Oct 12 04:22:11 AM UTC 24 |
10961861931 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1398279412 |
|
|
Oct 12 04:21:45 AM UTC 24 |
Oct 12 04:22:19 AM UTC 24 |
1045551692 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.3931815956 |
|
|
Oct 12 04:15:58 AM UTC 24 |
Oct 12 04:22:40 AM UTC 24 |
13850393595 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.2490712569 |
|
|
Oct 12 04:17:17 AM UTC 24 |
Oct 12 04:22:52 AM UTC 24 |
8799203697 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_bijection.1572383547 |
|
|
Oct 12 03:31:18 AM UTC 24 |
Oct 12 04:23:36 AM UTC 24 |
359065025227 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.3033923728 |
|
|
Oct 12 04:21:15 AM UTC 24 |
Oct 12 04:23:49 AM UTC 24 |
13144736453 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_executable.876130013 |
|
|
Oct 12 04:15:15 AM UTC 24 |
Oct 12 04:23:55 AM UTC 24 |
12954148446 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.3638463669 |
|
|
Oct 12 04:18:21 AM UTC 24 |
Oct 12 04:24:21 AM UTC 24 |
10617062024 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.3947925558 |
|
|
Oct 12 04:21:15 AM UTC 24 |
Oct 12 04:24:27 AM UTC 24 |
5070219286 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_bijection.2481404058 |
|
|
Oct 12 03:49:03 AM UTC 24 |
Oct 12 04:24:28 AM UTC 24 |
119706685435 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.1938233719 |
|
|
Oct 12 04:19:14 AM UTC 24 |
Oct 12 04:25:34 AM UTC 24 |
42476325232 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.2253266425 |
|
|
Oct 12 04:17:44 AM UTC 24 |
Oct 12 04:25:52 AM UTC 24 |
38839665164 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_regwen.2121546438 |
|
|
Oct 12 04:08:00 AM UTC 24 |
Oct 12 04:26:06 AM UTC 24 |
16505548137 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_bijection.505392684 |
|
|
Oct 12 04:09:07 AM UTC 24 |
Oct 12 04:26:06 AM UTC 24 |
184434466266 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.1715819547 |
|
|
Oct 12 04:11:12 AM UTC 24 |
Oct 12 04:26:14 AM UTC 24 |
14982227382 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all.1083799376 |
|
|
Oct 12 03:33:55 AM UTC 24 |
Oct 12 04:26:45 AM UTC 24 |
241268754318 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_executable.1677774094 |
|
|
Oct 12 04:18:26 AM UTC 24 |
Oct 12 04:27:11 AM UTC 24 |
12201888710 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all.1393853268 |
|
|
Oct 12 03:03:15 AM UTC 24 |
Oct 12 04:27:20 AM UTC 24 |
307018751154 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.3482822976 |
|
|
Oct 12 04:14:14 AM UTC 24 |
Oct 12 04:27:23 AM UTC 24 |
80466550816 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_bijection.2120311280 |
|
|
Oct 12 04:17:00 AM UTC 24 |
Oct 12 04:27:37 AM UTC 24 |
8556197235 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_executable.790225078 |
|
|
Oct 12 04:20:48 AM UTC 24 |
Oct 12 04:27:51 AM UTC 24 |
5385918996 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.370557404 |
|
|
Oct 12 04:07:51 AM UTC 24 |
Oct 12 04:28:17 AM UTC 24 |
61448394196 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.3105743821 |
|
|
Oct 12 04:19:15 AM UTC 24 |
Oct 12 04:28:25 AM UTC 24 |
16224024466 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.3244049841 |
|
|
Oct 12 02:43:23 AM UTC 24 |
Oct 12 04:29:19 AM UTC 24 |
538494175167 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all.2497739033 |
|
|
Oct 12 02:52:27 AM UTC 24 |
Oct 12 04:30:18 AM UTC 24 |
205152127172 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all.2468355741 |
|
|
Oct 12 03:44:32 AM UTC 24 |
Oct 12 04:30:57 AM UTC 24 |
441259367805 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_bijection.3951609581 |
|
|
Oct 12 04:04:30 AM UTC 24 |
Oct 12 04:31:12 AM UTC 24 |
345534878206 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_bijection.2951873154 |
|
|
Oct 12 03:47:17 AM UTC 24 |
Oct 12 04:31:49 AM UTC 24 |
822278527906 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_bijection.3656543063 |
|
|
Oct 12 04:11:14 AM UTC 24 |
Oct 12 04:32:03 AM UTC 24 |
98321834511 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all.2402970797 |
|
|
Oct 12 04:01:28 AM UTC 24 |
Oct 12 04:32:09 AM UTC 24 |
119472226969 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.3629926101 |
|
|
Oct 12 04:20:21 AM UTC 24 |
Oct 12 04:32:18 AM UTC 24 |
27524197227 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all.4107729679 |
|
|
Oct 12 03:42:15 AM UTC 24 |
Oct 12 04:32:37 AM UTC 24 |
811239392557 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.3676904519 |
|
|
Oct 12 04:16:45 AM UTC 24 |
Oct 12 04:33:25 AM UTC 24 |
51543998314 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_regwen.3502893308 |
|
|
Oct 12 04:12:52 AM UTC 24 |
Oct 12 04:35:20 AM UTC 24 |
61835651538 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all.3317927711 |
|
|
Oct 12 03:55:53 AM UTC 24 |
Oct 12 04:36:11 AM UTC 24 |
160530751261 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all.3566452178 |
|
|
Oct 12 03:17:44 AM UTC 24 |
Oct 12 04:36:49 AM UTC 24 |
362962241867 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.3215714056 |
|
|
Oct 12 04:12:25 AM UTC 24 |
Oct 12 04:38:07 AM UTC 24 |
65414834377 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.4125187525 |
|
|
Oct 12 04:19:12 AM UTC 24 |
Oct 12 04:38:38 AM UTC 24 |
33668842503 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_regwen.1762896229 |
|
|
Oct 12 04:21:03 AM UTC 24 |
Oct 12 04:39:32 AM UTC 24 |
79831074533 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_regwen.1419958122 |
|
|
Oct 12 04:15:34 AM UTC 24 |
Oct 12 04:40:03 AM UTC 24 |
27520856196 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_bijection.2048589397 |
|
|
Oct 12 03:59:44 AM UTC 24 |
Oct 12 04:44:21 AM UTC 24 |
509515759353 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_bijection.592363440 |
|
|
Oct 12 04:14:15 AM UTC 24 |
Oct 12 04:45:30 AM UTC 24 |
345126513391 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_bijection.1190140007 |
|
|
Oct 12 04:19:13 AM UTC 24 |
Oct 12 04:48:13 AM UTC 24 |
87436631267 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_bijection.1351694530 |
|
|
Oct 12 04:06:55 AM UTC 24 |
Oct 12 04:49:48 AM UTC 24 |
524335217998 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all.3898780099 |
|
|
Oct 12 04:08:29 AM UTC 24 |
Oct 12 04:55:26 AM UTC 24 |
307519795677 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all.4003403031 |
|
|
Oct 12 03:23:04 AM UTC 24 |
Oct 12 04:56:57 AM UTC 24 |
751526592911 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all.1842426640 |
|
|
Oct 12 03:47:05 AM UTC 24 |
Oct 12 04:59:01 AM UTC 24 |
1036894602416 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all.1894712530 |
|
|
Oct 12 03:53:18 AM UTC 24 |
Oct 12 05:00:34 AM UTC 24 |
117999213751 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all.2227105849 |
|
|
Oct 12 04:16:27 AM UTC 24 |
Oct 12 05:01:32 AM UTC 24 |
74395912378 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all.2349896909 |
|
|
Oct 12 04:21:53 AM UTC 24 |
Oct 12 05:05:02 AM UTC 24 |
345677244176 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all.2900615253 |
|
|
Oct 12 03:37:02 AM UTC 24 |
Oct 12 05:05:28 AM UTC 24 |
1044469552500 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all.3810636426 |
|
|
Oct 12 03:39:41 AM UTC 24 |
Oct 12 05:06:17 AM UTC 24 |
75658493199 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all.3564929230 |
|
|
Oct 12 04:13:44 AM UTC 24 |
Oct 12 05:11:13 AM UTC 24 |
35146116328 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all.3572628944 |
|
|
Oct 12 03:07:29 AM UTC 24 |
Oct 12 05:12:22 AM UTC 24 |
1283027210866 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all.200453617 |
|
|
Oct 12 04:06:21 AM UTC 24 |
Oct 12 05:24:11 AM UTC 24 |
96054949393 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all.2798457383 |
|
|
Oct 12 03:59:01 AM UTC 24 |
Oct 12 05:25:14 AM UTC 24 |
65162896348 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all.2509650249 |
|
|
Oct 12 03:51:17 AM UTC 24 |
Oct 12 05:30:13 AM UTC 24 |
558819101578 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all.3050630871 |
|
|
Oct 12 04:18:53 AM UTC 24 |
Oct 12 05:48:07 AM UTC 24 |
69561628099 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all.3746106660 |
|
|
Oct 12 04:04:13 AM UTC 24 |
Oct 12 05:58:51 AM UTC 24 |
251059972704 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all.1816823173 |
|
|
Oct 12 03:48:53 AM UTC 24 |
Oct 12 06:19:22 AM UTC 24 |
4680868908333 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1374918673 |
|
|
Oct 12 04:22:01 AM UTC 24 |
Oct 12 04:22:08 AM UTC 24 |
157842506 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1865542623 |
|
|
Oct 12 04:22:12 AM UTC 24 |
Oct 12 04:22:14 AM UTC 24 |
14570981 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.659400536 |
|
|
Oct 12 04:22:10 AM UTC 24 |
Oct 12 04:22:15 AM UTC 24 |
197928085 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.4137939884 |
|
|
Oct 12 04:22:15 AM UTC 24 |
Oct 12 04:22:17 AM UTC 24 |
18877345 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.836091657 |
|
|
Oct 12 04:22:18 AM UTC 24 |
Oct 12 04:22:21 AM UTC 24 |
40158016 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2961454932 |
|
|
Oct 12 04:22:16 AM UTC 24 |
Oct 12 04:22:21 AM UTC 24 |
346314171 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2123542280 |
|
|
Oct 12 04:22:20 AM UTC 24 |
Oct 12 04:22:23 AM UTC 24 |
41959396 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2592349479 |
|
|
Oct 12 04:22:22 AM UTC 24 |
Oct 12 04:22:30 AM UTC 24 |
1475115513 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.876978403 |
|
|
Oct 12 04:22:24 AM UTC 24 |
Oct 12 04:22:31 AM UTC 24 |
321501771 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.659146916 |
|
|
Oct 12 04:22:32 AM UTC 24 |
Oct 12 04:22:34 AM UTC 24 |
15328326 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2665699079 |
|
|
Oct 12 04:22:31 AM UTC 24 |
Oct 12 04:22:36 AM UTC 24 |
142113743 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2810510077 |
|
|
Oct 12 04:22:35 AM UTC 24 |
Oct 12 04:22:37 AM UTC 24 |
57467012 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2063650305 |
|
|
Oct 12 04:22:36 AM UTC 24 |
Oct 12 04:22:40 AM UTC 24 |
159386405 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1331450675 |
|
|
Oct 12 04:22:38 AM UTC 24 |
Oct 12 04:22:41 AM UTC 24 |
35125188 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1476789261 |
|
|
Oct 12 04:22:41 AM UTC 24 |
Oct 12 04:22:42 AM UTC 24 |
188125850 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2605418533 |
|
|
Oct 12 04:22:43 AM UTC 24 |
Oct 12 04:22:49 AM UTC 24 |
39767310 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.842147203 |
|
|
Oct 12 04:22:41 AM UTC 24 |
Oct 12 04:22:52 AM UTC 24 |
5776836114 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.651124039 |
|
|
Oct 12 04:22:50 AM UTC 24 |
Oct 12 04:22:53 AM UTC 24 |
73630008 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2511589792 |
|
|
Oct 12 04:21:59 AM UTC 24 |
Oct 12 04:22:55 AM UTC 24 |
7072440589 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1305269003 |
|
|
Oct 12 04:22:53 AM UTC 24 |
Oct 12 04:22:55 AM UTC 24 |
19184888 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3911990236 |
|
|
Oct 12 04:22:53 AM UTC 24 |
Oct 12 04:22:55 AM UTC 24 |
11911880 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1389670259 |
|
|
Oct 12 04:22:54 AM UTC 24 |
Oct 12 04:22:57 AM UTC 24 |
66374103 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.104476305 |
|
|
Oct 12 04:22:55 AM UTC 24 |
Oct 12 04:22:58 AM UTC 24 |
31092118 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.4010304823 |
|
|
Oct 12 04:22:56 AM UTC 24 |
Oct 12 04:22:58 AM UTC 24 |
30860652 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3602028509 |
|
|
Oct 12 04:22:59 AM UTC 24 |
Oct 12 04:23:02 AM UTC 24 |
79711516 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.365914161 |
|
|
Oct 12 04:22:56 AM UTC 24 |
Oct 12 04:23:03 AM UTC 24 |
1505909492 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1513893595 |
|
|
Oct 12 04:22:59 AM UTC 24 |
Oct 12 04:23:05 AM UTC 24 |
215434786 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.223956141 |
|
|
Oct 12 04:23:03 AM UTC 24 |
Oct 12 04:23:05 AM UTC 24 |
31062674 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.118584943 |
|
|
Oct 12 04:23:04 AM UTC 24 |
Oct 12 04:23:06 AM UTC 24 |
47029372 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.641208550 |
|
|
Oct 12 04:23:07 AM UTC 24 |
Oct 12 04:23:09 AM UTC 24 |
43213497 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.391025810 |
|
|
Oct 12 04:23:07 AM UTC 24 |
Oct 12 04:23:09 AM UTC 24 |
48631514 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.4034343920 |
|
|
Oct 12 04:23:05 AM UTC 24 |
Oct 12 04:23:09 AM UTC 24 |
91191358 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1742135138 |
|
|
Oct 12 04:23:10 AM UTC 24 |
Oct 12 04:23:16 AM UTC 24 |
83821656 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.67025025 |
|
|
Oct 12 04:23:10 AM UTC 24 |
Oct 12 04:23:16 AM UTC 24 |
345771876 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.4115024377 |
|
|
Oct 12 04:23:17 AM UTC 24 |
Oct 12 04:23:19 AM UTC 24 |
22300015 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3077079653 |
|
|
Oct 12 04:23:16 AM UTC 24 |
Oct 12 04:23:21 AM UTC 24 |
707049151 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.452996714 |
|
|
Oct 12 04:23:20 AM UTC 24 |
Oct 12 04:23:22 AM UTC 24 |
20735091 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.13888841 |
|
|
Oct 12 04:23:22 AM UTC 24 |
Oct 12 04:23:26 AM UTC 24 |
195531679 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.9980571 |
|
|
Oct 12 04:23:24 AM UTC 24 |
Oct 12 04:23:26 AM UTC 24 |
37771386 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3762700450 |
|
|
Oct 12 04:22:58 AM UTC 24 |
Oct 12 04:23:29 AM UTC 24 |
3697879415 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1044105089 |
|
|
Oct 12 04:23:27 AM UTC 24 |
Oct 12 04:23:29 AM UTC 24 |
63437591 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2397851702 |
|
|
Oct 12 04:23:27 AM UTC 24 |
Oct 12 04:23:35 AM UTC 24 |
750624500 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.134003910 |
|
|
Oct 12 04:22:22 AM UTC 24 |
Oct 12 04:23:37 AM UTC 24 |
7689759283 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2830847512 |
|
|
Oct 12 04:23:30 AM UTC 24 |
Oct 12 04:23:38 AM UTC 24 |
128421145 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.24836298 |
|
|
Oct 12 04:23:35 AM UTC 24 |
Oct 12 04:23:39 AM UTC 24 |
204654821 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.889589958 |
|
|
Oct 12 04:23:37 AM UTC 24 |
Oct 12 04:23:39 AM UTC 24 |
19738239 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3428775581 |
|
|
Oct 12 04:23:38 AM UTC 24 |
Oct 12 04:23:40 AM UTC 24 |
123550471 ps |