| T545 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_regwen.4236109657 |
|
|
Oct 12 03:24:59 AM UTC 24 |
Oct 12 03:29:27 AM UTC 24 |
5634557863 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.2800920064 |
|
|
Oct 12 03:29:20 AM UTC 24 |
Oct 12 03:29:31 AM UTC 24 |
2690635042 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1282098067 |
|
|
Oct 12 03:28:52 AM UTC 24 |
Oct 12 03:29:43 AM UTC 24 |
2817073709 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.648435803 |
|
|
Oct 12 03:28:02 AM UTC 24 |
Oct 12 03:29:52 AM UTC 24 |
16883007038 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.3449858929 |
|
|
Oct 12 03:25:58 AM UTC 24 |
Oct 12 03:30:04 AM UTC 24 |
23475080037 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_bijection.2797403403 |
|
|
Oct 12 03:07:45 AM UTC 24 |
Oct 12 03:30:09 AM UTC 24 |
18125988648 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.1130176089 |
|
|
Oct 12 03:30:04 AM UTC 24 |
Oct 12 03:30:11 AM UTC 24 |
1408441601 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.3074305697 |
|
|
Oct 12 03:29:14 AM UTC 24 |
Oct 12 03:30:38 AM UTC 24 |
792386883 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_readback_err.3873108166 |
|
|
Oct 12 03:30:39 AM UTC 24 |
Oct 12 03:30:50 AM UTC 24 |
1364129582 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.966231109 |
|
|
Oct 12 03:29:28 AM UTC 24 |
Oct 12 03:30:52 AM UTC 24 |
9470572307 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.765207038 |
|
|
Oct 12 03:28:32 AM UTC 24 |
Oct 12 03:30:53 AM UTC 24 |
11057385827 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_alert_test.696477514 |
|
|
Oct 12 03:30:54 AM UTC 24 |
Oct 12 03:30:56 AM UTC 24 |
16953122 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_regwen.4024808363 |
|
|
Oct 12 03:17:20 AM UTC 24 |
Oct 12 03:31:07 AM UTC 24 |
53021662793 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2313939393 |
|
|
Oct 12 03:30:51 AM UTC 24 |
Oct 12 03:31:17 AM UTC 24 |
2193867883 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_smoke.2648525927 |
|
|
Oct 12 03:30:57 AM UTC 24 |
Oct 12 03:31:30 AM UTC 24 |
1442303230 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.2538444660 |
|
|
Oct 12 03:28:30 AM UTC 24 |
Oct 12 03:31:33 AM UTC 24 |
41375488682 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.2279465093 |
|
|
Oct 12 03:30:13 AM UTC 24 |
Oct 12 03:31:50 AM UTC 24 |
2870118059 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.153414876 |
|
|
Oct 12 03:27:14 AM UTC 24 |
Oct 12 03:31:56 AM UTC 24 |
4356260309 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all.2482715876 |
|
|
Oct 12 03:09:26 AM UTC 24 |
Oct 12 03:32:14 AM UTC 24 |
490004105232 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access.311366861 |
|
|
Oct 12 03:31:34 AM UTC 24 |
Oct 12 03:32:26 AM UTC 24 |
819703037 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.1930605057 |
|
|
Oct 12 03:31:57 AM UTC 24 |
Oct 12 03:32:27 AM UTC 24 |
3759549850 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.4246143790 |
|
|
Oct 12 03:29:08 AM UTC 24 |
Oct 12 03:32:28 AM UTC 24 |
24027727568 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_bijection.1923011395 |
|
|
Oct 12 03:06:00 AM UTC 24 |
Oct 12 03:32:34 AM UTC 24 |
172697852978 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.973811447 |
|
|
Oct 12 03:32:15 AM UTC 24 |
Oct 12 03:33:07 AM UTC 24 |
12527173793 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.3972665413 |
|
|
Oct 12 03:33:08 AM UTC 24 |
Oct 12 03:33:18 AM UTC 24 |
4198785648 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.2682590336 |
|
|
Oct 12 03:26:40 AM UTC 24 |
Oct 12 03:33:20 AM UTC 24 |
129393709021 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_executable.867643243 |
|
|
Oct 12 03:10:40 AM UTC 24 |
Oct 12 03:33:34 AM UTC 24 |
10403772240 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_readback_err.963389623 |
|
|
Oct 12 03:33:35 AM UTC 24 |
Oct 12 03:33:46 AM UTC 24 |
721650417 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_regwen.4291072738 |
|
|
Oct 12 03:26:22 AM UTC 24 |
Oct 12 03:33:54 AM UTC 24 |
18093966900 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.2226431003 |
|
|
Oct 12 03:32:27 AM UTC 24 |
Oct 12 03:34:27 AM UTC 24 |
43890491214 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_alert_test.1555547645 |
|
|
Oct 12 03:34:28 AM UTC 24 |
Oct 12 03:34:30 AM UTC 24 |
27146166 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.2450757624 |
|
|
Oct 12 03:27:12 AM UTC 24 |
Oct 12 03:34:36 AM UTC 24 |
9961503271 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.3818704238 |
|
|
Oct 12 03:33:21 AM UTC 24 |
Oct 12 03:34:37 AM UTC 24 |
11112741518 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_smoke.1023095779 |
|
|
Oct 12 03:34:31 AM UTC 24 |
Oct 12 03:34:43 AM UTC 24 |
2810181788 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.73919831 |
|
|
Oct 12 03:31:31 AM UTC 24 |
Oct 12 03:35:01 AM UTC 24 |
3878899679 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.1457523059 |
|
|
Oct 12 03:27:34 AM UTC 24 |
Oct 12 03:35:12 AM UTC 24 |
29218331025 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3564149760 |
|
|
Oct 12 03:33:47 AM UTC 24 |
Oct 12 03:35:16 AM UTC 24 |
9218193045 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.1531349564 |
|
|
Oct 12 03:35:18 AM UTC 24 |
Oct 12 03:35:38 AM UTC 24 |
731477286 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.2332452048 |
|
|
Oct 12 03:29:32 AM UTC 24 |
Oct 12 03:35:43 AM UTC 24 |
22598889682 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_regwen.2162079622 |
|
|
Oct 12 03:28:09 AM UTC 24 |
Oct 12 03:35:59 AM UTC 24 |
25241851156 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_executable.2892284751 |
|
|
Oct 12 03:21:38 AM UTC 24 |
Oct 12 03:36:10 AM UTC 24 |
23307573320 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_bijection.2231103550 |
|
|
Oct 12 02:56:41 AM UTC 24 |
Oct 12 03:36:13 AM UTC 24 |
62356386032 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access.1804721909 |
|
|
Oct 12 03:35:02 AM UTC 24 |
Oct 12 03:36:24 AM UTC 24 |
1455581563 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.482021367 |
|
|
Oct 12 03:36:25 AM UTC 24 |
Oct 12 03:36:31 AM UTC 24 |
710190718 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.495434788 |
|
|
Oct 12 03:26:02 AM UTC 24 |
Oct 12 03:36:40 AM UTC 24 |
25660980446 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.2446201258 |
|
|
Oct 12 03:35:39 AM UTC 24 |
Oct 12 03:36:47 AM UTC 24 |
4481408722 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_readback_err.1898459604 |
|
|
Oct 12 03:36:48 AM UTC 24 |
Oct 12 03:36:59 AM UTC 24 |
662882258 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.2454052635 |
|
|
Oct 12 03:30:09 AM UTC 24 |
Oct 12 03:37:01 AM UTC 24 |
27646883351 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all.3632239399 |
|
|
Oct 12 03:11:13 AM UTC 24 |
Oct 12 03:37:17 AM UTC 24 |
18718784936 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_alert_test.245239961 |
|
|
Oct 12 03:37:18 AM UTC 24 |
Oct 12 03:37:21 AM UTC 24 |
24665166 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.2949060318 |
|
|
Oct 12 03:31:51 AM UTC 24 |
Oct 12 03:37:25 AM UTC 24 |
26449850722 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_smoke.4034724719 |
|
|
Oct 12 03:37:22 AM UTC 24 |
Oct 12 03:37:44 AM UTC 24 |
4360291630 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.1618264238 |
|
|
Oct 12 03:35:44 AM UTC 24 |
Oct 12 03:37:56 AM UTC 24 |
21965049548 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_regwen.1299057221 |
|
|
Oct 12 03:36:13 AM UTC 24 |
Oct 12 03:37:59 AM UTC 24 |
11198667813 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_executable.2801847851 |
|
|
Oct 12 03:26:20 AM UTC 24 |
Oct 12 03:38:28 AM UTC 24 |
14781438949 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.3324210727 |
|
|
Oct 12 03:36:41 AM UTC 24 |
Oct 12 03:38:32 AM UTC 24 |
17313141701 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access.3270419545 |
|
|
Oct 12 03:38:00 AM UTC 24 |
Oct 12 03:38:42 AM UTC 24 |
6094766605 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.3891376718 |
|
|
Oct 12 03:33:19 AM UTC 24 |
Oct 12 03:38:43 AM UTC 24 |
17730160618 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1297009655 |
|
|
Oct 12 03:36:59 AM UTC 24 |
Oct 12 03:38:47 AM UTC 24 |
7439124359 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_executable.2882251491 |
|
|
Oct 12 03:28:04 AM UTC 24 |
Oct 12 03:39:01 AM UTC 24 |
6284228459 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.428718117 |
|
|
Oct 12 03:38:43 AM UTC 24 |
Oct 12 03:39:03 AM UTC 24 |
2891825941 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_executable.2617714740 |
|
|
Oct 12 03:08:43 AM UTC 24 |
Oct 12 03:39:05 AM UTC 24 |
112049961574 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.1012173542 |
|
|
Oct 12 03:39:06 AM UTC 24 |
Oct 12 03:39:12 AM UTC 24 |
1473052690 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.1362750106 |
|
|
Oct 12 03:36:32 AM UTC 24 |
Oct 12 03:39:17 AM UTC 24 |
17528717586 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_executable.1345424553 |
|
|
Oct 12 03:18:54 AM UTC 24 |
Oct 12 03:39:32 AM UTC 24 |
114872834024 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.394026665 |
|
|
Oct 12 03:38:33 AM UTC 24 |
Oct 12 03:39:36 AM UTC 24 |
2992932566 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.1930619310 |
|
|
Oct 12 03:32:27 AM UTC 24 |
Oct 12 03:39:40 AM UTC 24 |
26952553198 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_readback_err.3192937346 |
|
|
Oct 12 03:39:33 AM UTC 24 |
Oct 12 03:39:42 AM UTC 24 |
696301087 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.3331751021 |
|
|
Oct 12 02:40:02 AM UTC 24 |
Oct 12 03:39:42 AM UTC 24 |
184446032207 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_regwen.3721595395 |
|
|
Oct 12 03:21:59 AM UTC 24 |
Oct 12 03:39:44 AM UTC 24 |
13223816913 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_alert_test.1247820967 |
|
|
Oct 12 03:39:43 AM UTC 24 |
Oct 12 03:39:45 AM UTC 24 |
53666802 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.3217293082 |
|
|
Oct 12 02:45:42 AM UTC 24 |
Oct 12 03:39:49 AM UTC 24 |
383861063487 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1261033017 |
|
|
Oct 12 03:39:37 AM UTC 24 |
Oct 12 03:39:50 AM UTC 24 |
564956471 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_smoke.2449554403 |
|
|
Oct 12 03:39:43 AM UTC 24 |
Oct 12 03:40:09 AM UTC 24 |
2825230649 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.721916656 |
|
|
Oct 12 03:38:44 AM UTC 24 |
Oct 12 03:40:18 AM UTC 24 |
11444430463 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_bijection.3203514509 |
|
|
Oct 12 03:17:52 AM UTC 24 |
Oct 12 03:40:26 AM UTC 24 |
72001057286 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.2182880611 |
|
|
Oct 12 03:40:19 AM UTC 24 |
Oct 12 03:40:31 AM UTC 24 |
2486161735 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.642628747 |
|
|
Oct 12 03:40:31 AM UTC 24 |
Oct 12 03:40:57 AM UTC 24 |
5869464890 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.1177381094 |
|
|
Oct 12 03:39:17 AM UTC 24 |
Oct 12 03:41:00 AM UTC 24 |
7305514072 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access.658564130 |
|
|
Oct 12 03:39:51 AM UTC 24 |
Oct 12 03:41:17 AM UTC 24 |
1224273426 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.3209128676 |
|
|
Oct 12 03:40:27 AM UTC 24 |
Oct 12 03:41:39 AM UTC 24 |
753115684 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.667669222 |
|
|
Oct 12 03:41:40 AM UTC 24 |
Oct 12 03:41:46 AM UTC 24 |
381879317 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all.1171646937 |
|
|
Oct 12 02:49:16 AM UTC 24 |
Oct 12 03:41:53 AM UTC 24 |
186808235496 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.1335625700 |
|
|
Oct 12 03:34:44 AM UTC 24 |
Oct 12 03:42:03 AM UTC 24 |
20370393211 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.3099722298 |
|
|
Oct 12 03:31:08 AM UTC 24 |
Oct 12 03:42:13 AM UTC 24 |
78296570960 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_readback_err.4011353181 |
|
|
Oct 12 03:42:04 AM UTC 24 |
Oct 12 03:42:15 AM UTC 24 |
8280405830 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all.581480705 |
|
|
Oct 12 03:00:46 AM UTC 24 |
Oct 12 03:42:21 AM UTC 24 |
677063004737 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_alert_test.2247189047 |
|
|
Oct 12 03:42:21 AM UTC 24 |
Oct 12 03:42:24 AM UTC 24 |
21073349 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_regwen.510009150 |
|
|
Oct 12 03:32:35 AM UTC 24 |
Oct 12 03:42:36 AM UTC 24 |
64764623999 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1781619004 |
|
|
Oct 12 03:42:13 AM UTC 24 |
Oct 12 03:42:36 AM UTC 24 |
8282203090 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_executable.1175255836 |
|
|
Oct 12 03:29:43 AM UTC 24 |
Oct 12 03:42:37 AM UTC 24 |
20150973269 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_regwen.2978046241 |
|
|
Oct 12 03:29:53 AM UTC 24 |
Oct 12 03:42:39 AM UTC 24 |
12689610021 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.396882029 |
|
|
Oct 12 03:29:03 AM UTC 24 |
Oct 12 03:42:48 AM UTC 24 |
8843474847 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.2311098970 |
|
|
Oct 12 03:29:11 AM UTC 24 |
Oct 12 03:42:56 AM UTC 24 |
120178882220 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.537707950 |
|
|
Oct 12 03:42:57 AM UTC 24 |
Oct 12 03:43:09 AM UTC 24 |
706906769 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.3152235068 |
|
|
Oct 12 03:43:10 AM UTC 24 |
Oct 12 03:43:23 AM UTC 24 |
1435278035 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.2115097248 |
|
|
Oct 12 03:37:57 AM UTC 24 |
Oct 12 03:43:41 AM UTC 24 |
33776519381 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_executable.3692917730 |
|
|
Oct 12 03:24:37 AM UTC 24 |
Oct 12 03:43:59 AM UTC 24 |
32388505915 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_smoke.2569092846 |
|
|
Oct 12 03:42:25 AM UTC 24 |
Oct 12 03:44:01 AM UTC 24 |
1870963397 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access.3030406395 |
|
|
Oct 12 03:42:40 AM UTC 24 |
Oct 12 03:44:02 AM UTC 24 |
4886022184 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.221563831 |
|
|
Oct 12 03:17:00 AM UTC 24 |
Oct 12 03:44:03 AM UTC 24 |
88813899670 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.2482437088 |
|
|
Oct 12 03:44:03 AM UTC 24 |
Oct 12 03:44:11 AM UTC 24 |
669373916 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.2518224624 |
|
|
Oct 12 03:41:54 AM UTC 24 |
Oct 12 03:44:18 AM UTC 24 |
2546718926 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.3440962060 |
|
|
Oct 12 03:43:25 AM UTC 24 |
Oct 12 03:44:18 AM UTC 24 |
5067331926 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_readback_err.3444874776 |
|
|
Oct 12 03:44:19 AM UTC 24 |
Oct 12 03:44:31 AM UTC 24 |
662558027 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.3625320273 |
|
|
Oct 12 03:39:50 AM UTC 24 |
Oct 12 03:44:36 AM UTC 24 |
2930026000 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_alert_test.3293951479 |
|
|
Oct 12 03:44:37 AM UTC 24 |
Oct 12 03:44:39 AM UTC 24 |
14398859 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_smoke.1147020610 |
|
|
Oct 12 03:44:40 AM UTC 24 |
Oct 12 03:44:51 AM UTC 24 |
1015949591 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.1580805965 |
|
|
Oct 12 03:38:28 AM UTC 24 |
Oct 12 03:44:52 AM UTC 24 |
27443267032 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.3266115163 |
|
|
Oct 12 03:35:13 AM UTC 24 |
Oct 12 03:45:08 AM UTC 24 |
19725945268 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.2496086330 |
|
|
Oct 12 03:42:38 AM UTC 24 |
Oct 12 03:45:20 AM UTC 24 |
9925361191 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access.3949707944 |
|
|
Oct 12 03:45:20 AM UTC 24 |
Oct 12 03:45:27 AM UTC 24 |
392362479 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.2543321392 |
|
|
Oct 12 03:28:02 AM UTC 24 |
Oct 12 03:45:31 AM UTC 24 |
18294987276 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.3993962975 |
|
|
Oct 12 03:39:13 AM UTC 24 |
Oct 12 03:45:43 AM UTC 24 |
19443615001 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.684786568 |
|
|
Oct 12 03:44:11 AM UTC 24 |
Oct 12 03:45:46 AM UTC 24 |
2681525899 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.3001737566 |
|
|
Oct 12 03:45:32 AM UTC 24 |
Oct 12 03:45:49 AM UTC 24 |
698960424 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.1137460930 |
|
|
Oct 12 03:43:42 AM UTC 24 |
Oct 12 03:46:17 AM UTC 24 |
11217826038 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.4193610017 |
|
|
Oct 12 03:38:48 AM UTC 24 |
Oct 12 03:46:25 AM UTC 24 |
34275380712 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.997777041 |
|
|
Oct 12 03:26:19 AM UTC 24 |
Oct 12 03:46:29 AM UTC 24 |
77886939256 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.54569349 |
|
|
Oct 12 03:46:30 AM UTC 24 |
Oct 12 03:46:37 AM UTC 24 |
353890688 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.3167927156 |
|
|
Oct 12 03:34:36 AM UTC 24 |
Oct 12 03:46:39 AM UTC 24 |
10033536749 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.3254630820 |
|
|
Oct 12 03:44:03 AM UTC 24 |
Oct 12 03:46:52 AM UTC 24 |
4035060262 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.1506567246 |
|
|
Oct 12 03:45:47 AM UTC 24 |
Oct 12 03:47:03 AM UTC 24 |
36995390967 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_readback_err.864215631 |
|
|
Oct 12 03:46:53 AM UTC 24 |
Oct 12 03:47:04 AM UTC 24 |
678597184 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.2540598328 |
|
|
Oct 12 03:36:00 AM UTC 24 |
Oct 12 03:47:06 AM UTC 24 |
6986216543 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_bijection.926548817 |
|
|
Oct 12 03:23:39 AM UTC 24 |
Oct 12 03:47:09 AM UTC 24 |
250027616035 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_alert_test.1005010023 |
|
|
Oct 12 03:47:07 AM UTC 24 |
Oct 12 03:47:09 AM UTC 24 |
22438271 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.2619624716 |
|
|
Oct 12 03:47:04 AM UTC 24 |
Oct 12 03:47:16 AM UTC 24 |
268172342 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_executable.2961394461 |
|
|
Oct 12 03:39:02 AM UTC 24 |
Oct 12 03:47:24 AM UTC 24 |
54204872847 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_bijection.1848022359 |
|
|
Oct 12 03:29:04 AM UTC 24 |
Oct 12 03:47:26 AM UTC 24 |
230930142977 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.562771227 |
|
|
Oct 12 03:44:20 AM UTC 24 |
Oct 12 03:47:31 AM UTC 24 |
17653158238 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_smoke.1841493477 |
|
|
Oct 12 03:47:09 AM UTC 24 |
Oct 12 03:47:34 AM UTC 24 |
862337276 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.1636010909 |
|
|
Oct 12 03:45:44 AM UTC 24 |
Oct 12 03:47:34 AM UTC 24 |
1204392058 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.4276254105 |
|
|
Oct 12 03:46:41 AM UTC 24 |
Oct 12 03:47:48 AM UTC 24 |
994954293 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access.2767825837 |
|
|
Oct 12 03:47:27 AM UTC 24 |
Oct 12 03:47:49 AM UTC 24 |
1598047009 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_bijection.2194720175 |
|
|
Oct 12 03:20:31 AM UTC 24 |
Oct 12 03:47:50 AM UTC 24 |
374390052171 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.1596706084 |
|
|
Oct 12 03:40:10 AM UTC 24 |
Oct 12 03:48:16 AM UTC 24 |
14190219655 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.1306880377 |
|
|
Oct 12 03:47:35 AM UTC 24 |
Oct 12 03:48:34 AM UTC 24 |
1526654879 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.2093320118 |
|
|
Oct 12 03:48:35 AM UTC 24 |
Oct 12 03:48:41 AM UTC 24 |
1682114409 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all.1683346126 |
|
|
Oct 12 02:56:28 AM UTC 24 |
Oct 12 03:48:44 AM UTC 24 |
98604671007 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.3516693375 |
|
|
Oct 12 03:21:34 AM UTC 24 |
Oct 12 03:48:46 AM UTC 24 |
147286679930 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.1717334522 |
|
|
Oct 12 03:46:39 AM UTC 24 |
Oct 12 03:48:49 AM UTC 24 |
4116509711 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.4248713889 |
|
|
Oct 12 03:47:35 AM UTC 24 |
Oct 12 03:48:52 AM UTC 24 |
825968584 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.4218659398 |
|
|
Oct 12 03:41:47 AM UTC 24 |
Oct 12 03:48:56 AM UTC 24 |
159216548694 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_readback_err.3695914667 |
|
|
Oct 12 03:48:47 AM UTC 24 |
Oct 12 03:48:58 AM UTC 24 |
954792226 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_alert_test.50997934 |
|
|
Oct 12 03:48:56 AM UTC 24 |
Oct 12 03:48:59 AM UTC 24 |
42430998 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all.3582905824 |
|
|
Oct 12 02:38:35 AM UTC 24 |
Oct 12 03:49:02 AM UTC 24 |
45437514550 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_smoke.3250416186 |
|
|
Oct 12 03:48:58 AM UTC 24 |
Oct 12 03:49:13 AM UTC 24 |
624849637 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.651729177 |
|
|
Oct 12 03:47:09 AM UTC 24 |
Oct 12 03:49:23 AM UTC 24 |
2210666640 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.4255356184 |
|
|
Oct 12 03:45:28 AM UTC 24 |
Oct 12 03:49:27 AM UTC 24 |
7779689974 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_executable.2511641981 |
|
|
Oct 12 03:36:11 AM UTC 24 |
Oct 12 03:49:33 AM UTC 24 |
32917959625 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1780345156 |
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|
Oct 12 03:48:50 AM UTC 24 |
Oct 12 03:49:38 AM UTC 24 |
1791410583 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access.3890033024 |
|
|
Oct 12 03:49:24 AM UTC 24 |
Oct 12 03:49:46 AM UTC 24 |
1588096492 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.3882034483 |
|
|
Oct 12 03:49:38 AM UTC 24 |
Oct 12 03:49:50 AM UTC 24 |
3057878395 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.3441853707 |
|
|
Oct 12 03:47:49 AM UTC 24 |
Oct 12 03:49:51 AM UTC 24 |
21908107506 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_executable.104933727 |
|
|
Oct 12 03:32:29 AM UTC 24 |
Oct 12 03:50:19 AM UTC 24 |
17290792236 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.3953781502 |
|
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Oct 12 03:48:45 AM UTC 24 |
Oct 12 03:50:34 AM UTC 24 |
52584000077 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.1878293106 |
|
|
Oct 12 03:50:35 AM UTC 24 |
Oct 12 03:50:42 AM UTC 24 |
1538959656 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.153955701 |
|
|
Oct 12 03:49:34 AM UTC 24 |
Oct 12 03:50:46 AM UTC 24 |
1535915406 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_regwen.1485749913 |
|
|
Oct 12 03:39:04 AM UTC 24 |
Oct 12 03:50:54 AM UTC 24 |
8622469922 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_readback_err.10320901 |
|
|
Oct 12 03:50:55 AM UTC 24 |
Oct 12 03:51:06 AM UTC 24 |
2632981692 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.1974826776 |
|
|
Oct 12 03:49:47 AM UTC 24 |
Oct 12 03:51:17 AM UTC 24 |
9133407940 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.1950228994 |
|
|
Oct 12 03:42:49 AM UTC 24 |
Oct 12 03:51:30 AM UTC 24 |
74886127244 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_executable.112158264 |
|
|
Oct 12 03:41:01 AM UTC 24 |
Oct 12 03:51:32 AM UTC 24 |
13499237115 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_alert_test.1112081163 |
|
|
Oct 12 03:51:31 AM UTC 24 |
Oct 12 03:51:33 AM UTC 24 |
66671192 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.2122227859 |
|
|
Oct 12 03:48:42 AM UTC 24 |
Oct 12 03:51:36 AM UTC 24 |
3950246804 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_smoke.3704897180 |
|
|
Oct 12 03:51:33 AM UTC 24 |
Oct 12 03:51:40 AM UTC 24 |
1449404892 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_executable.552959543 |
|
|
Oct 12 03:47:51 AM UTC 24 |
Oct 12 03:51:51 AM UTC 24 |
22875766153 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.3953040175 |
|
|
Oct 12 03:44:52 AM UTC 24 |
Oct 12 03:52:03 AM UTC 24 |
49073516712 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access.3613315598 |
|
|
Oct 12 03:51:51 AM UTC 24 |
Oct 12 03:52:03 AM UTC 24 |
531006686 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_bijection.3941833198 |
|
|
Oct 12 03:13:39 AM UTC 24 |
Oct 12 03:52:17 AM UTC 24 |
404879250376 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.4202005841 |
|
|
Oct 12 03:47:25 AM UTC 24 |
Oct 12 03:52:18 AM UTC 24 |
29499840439 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.4251742336 |
|
|
Oct 12 03:50:47 AM UTC 24 |
Oct 12 03:52:19 AM UTC 24 |
2749395997 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.2927179250 |
|
|
Oct 12 03:45:09 AM UTC 24 |
Oct 12 03:52:25 AM UTC 24 |
5585583102 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.3881580916 |
|
|
Oct 12 03:52:19 AM UTC 24 |
Oct 12 03:52:40 AM UTC 24 |
2546261327 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.2155249095 |
|
|
Oct 12 03:49:28 AM UTC 24 |
Oct 12 03:52:56 AM UTC 24 |
23399340005 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.109598569 |
|
|
Oct 12 03:51:07 AM UTC 24 |
Oct 12 03:52:58 AM UTC 24 |
2063693511 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.3936175737 |
|
|
Oct 12 03:52:56 AM UTC 24 |
Oct 12 03:53:01 AM UTC 24 |
706208319 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.1772985594 |
|
|
Oct 12 03:45:49 AM UTC 24 |
Oct 12 03:53:04 AM UTC 24 |
15431543686 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_executable.1571691600 |
|
|
Oct 12 03:49:52 AM UTC 24 |
Oct 12 03:53:12 AM UTC 24 |
11027053767 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_readback_err.2716209366 |
|
|
Oct 12 03:53:04 AM UTC 24 |
Oct 12 03:53:17 AM UTC 24 |
1368022723 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.743847033 |
|
|
Oct 12 03:52:04 AM UTC 24 |
Oct 12 03:53:24 AM UTC 24 |
4706030900 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.2435843094 |
|
|
Oct 12 03:37:26 AM UTC 24 |
Oct 12 03:53:25 AM UTC 24 |
19523086967 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_alert_test.3844576923 |
|
|
Oct 12 03:53:25 AM UTC 24 |
Oct 12 03:53:27 AM UTC 24 |
44668307 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.3588179595 |
|
|
Oct 12 04:07:20 AM UTC 24 |
Oct 12 04:14:13 AM UTC 24 |
8798148248 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.2325761144 |
|
|
Oct 12 03:40:58 AM UTC 24 |
Oct 12 03:53:39 AM UTC 24 |
14976783868 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.334492701 |
|
|
Oct 12 03:52:18 AM UTC 24 |
Oct 12 03:53:53 AM UTC 24 |
843132251 ps |
| T55 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3861495111 |
|
|
Oct 12 03:53:13 AM UTC 24 |
Oct 12 03:53:58 AM UTC 24 |
1045609282 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_executable.3073117864 |
|
|
Oct 12 03:44:00 AM UTC 24 |
Oct 12 03:54:01 AM UTC 24 |
20896252429 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.2658860235 |
|
|
Oct 12 03:47:32 AM UTC 24 |
Oct 12 03:54:29 AM UTC 24 |
31981665645 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access.3283953020 |
|
|
Oct 12 03:53:59 AM UTC 24 |
Oct 12 03:54:45 AM UTC 24 |
722983752 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_smoke.4024603052 |
|
|
Oct 12 03:53:26 AM UTC 24 |
Oct 12 03:54:56 AM UTC 24 |
3226996209 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.515271398 |
|
|
Oct 12 03:47:49 AM UTC 24 |
Oct 12 03:55:09 AM UTC 24 |
5323146414 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.2117168664 |
|
|
Oct 12 03:50:43 AM UTC 24 |
Oct 12 03:55:26 AM UTC 24 |
3946316154 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.1025908229 |
|
|
Oct 12 03:49:14 AM UTC 24 |
Oct 12 03:55:31 AM UTC 24 |
14703728181 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.2996098997 |
|
|
Oct 12 03:54:46 AM UTC 24 |
Oct 12 03:55:34 AM UTC 24 |
757534468 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.2316704634 |
|
|
Oct 12 03:53:02 AM UTC 24 |
Oct 12 03:55:35 AM UTC 24 |
6663264341 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all.3522483282 |
|
|
Oct 12 03:28:57 AM UTC 24 |
Oct 12 03:55:37 AM UTC 24 |
68304796959 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.2724873189 |
|
|
Oct 12 03:55:35 AM UTC 24 |
Oct 12 03:55:42 AM UTC 24 |
4815343296 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.1624864292 |
|
|
Oct 12 03:39:44 AM UTC 24 |
Oct 12 03:55:52 AM UTC 24 |
10398915991 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_readback_err.3624982267 |
|
|
Oct 12 03:55:43 AM UTC 24 |
Oct 12 03:55:52 AM UTC 24 |
681653021 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.2670099459 |
|
|
Oct 12 03:54:57 AM UTC 24 |
Oct 12 03:55:54 AM UTC 24 |
8190004830 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_alert_test.484800560 |
|
|
Oct 12 03:55:55 AM UTC 24 |
Oct 12 03:55:57 AM UTC 24 |
15121670 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.2752119672 |
|
|
Oct 12 03:54:31 AM UTC 24 |
Oct 12 03:56:04 AM UTC 24 |
3330502632 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.2822901974 |
|
|
Oct 12 03:51:41 AM UTC 24 |
Oct 12 03:56:35 AM UTC 24 |
13813065752 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_bijection.1394254287 |
|
|
Oct 12 03:34:37 AM UTC 24 |
Oct 12 03:56:48 AM UTC 24 |
230754770802 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3649172168 |
|
|
Oct 12 03:55:53 AM UTC 24 |
Oct 12 03:56:59 AM UTC 24 |
5714284043 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access.10433533 |
|
|
Oct 12 03:57:00 AM UTC 24 |
Oct 12 03:57:09 AM UTC 24 |
456352654 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_bijection.2844894490 |
|
|
Oct 12 03:03:40 AM UTC 24 |
Oct 12 03:57:21 AM UTC 24 |
948256717023 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.2612528300 |
|
|
Oct 12 03:57:22 AM UTC 24 |
Oct 12 03:57:50 AM UTC 24 |
2809852440 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.1100440510 |
|
|
Oct 12 03:57:51 AM UTC 24 |
Oct 12 03:58:02 AM UTC 24 |
683336377 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_smoke.3494842098 |
|
|
Oct 12 03:55:58 AM UTC 24 |
Oct 12 03:58:07 AM UTC 24 |
5707771101 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.2800534599 |
|
|
Oct 12 03:58:02 AM UTC 24 |
Oct 12 03:58:15 AM UTC 24 |
2835629137 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.3957209679 |
|
|
Oct 12 03:54:02 AM UTC 24 |
Oct 12 03:58:22 AM UTC 24 |
8398876730 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.3810635213 |
|
|
Oct 12 03:48:59 AM UTC 24 |
Oct 12 03:58:28 AM UTC 24 |
14703149497 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.1849042226 |
|
|
Oct 12 03:58:29 AM UTC 24 |
Oct 12 03:58:36 AM UTC 24 |
682196828 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.31030769 |
|
|
Oct 12 03:55:38 AM UTC 24 |
Oct 12 03:58:42 AM UTC 24 |
10179935989 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_executable.1707429784 |
|
|
Oct 12 03:46:18 AM UTC 24 |
Oct 12 03:58:46 AM UTC 24 |
43160467410 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_regwen.2114039189 |
|
|
Oct 12 03:48:17 AM UTC 24 |
Oct 12 03:58:59 AM UTC 24 |
6043687137 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_readback_err.1078695070 |
|
|
Oct 12 03:58:47 AM UTC 24 |
Oct 12 03:58:59 AM UTC 24 |
2809873697 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_bijection.2443317189 |
|
|
Oct 12 03:44:53 AM UTC 24 |
Oct 12 03:59:28 AM UTC 24 |
202174618357 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_alert_test.1733008817 |
|
|
Oct 12 03:59:30 AM UTC 24 |
Oct 12 03:59:32 AM UTC 24 |
40393841 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2022175464 |
|
|
Oct 12 03:59:00 AM UTC 24 |
Oct 12 03:59:36 AM UTC 24 |
1295908656 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.1412182887 |
|
|
Oct 12 03:49:51 AM UTC 24 |
Oct 12 03:59:43 AM UTC 24 |
14896366401 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_regwen.3165959391 |
|
|
Oct 12 03:55:32 AM UTC 24 |
Oct 12 03:59:51 AM UTC 24 |
4583680193 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_smoke.1619519234 |
|
|
Oct 12 03:59:33 AM UTC 24 |
Oct 12 04:00:00 AM UTC 24 |
3744002274 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.6364312 |
|
|
Oct 12 03:55:37 AM UTC 24 |
Oct 12 04:00:25 AM UTC 24 |
5360483459 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.3169101127 |
|
|
Oct 12 03:52:03 AM UTC 24 |
Oct 12 04:00:27 AM UTC 24 |
20905332716 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access.4244300154 |
|
|
Oct 12 04:00:00 AM UTC 24 |
Oct 12 04:00:34 AM UTC 24 |
3560118009 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_executable.135522655 |
|
|
Oct 12 03:52:26 AM UTC 24 |
Oct 12 04:00:38 AM UTC 24 |
12962948715 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.1652616336 |
|
|
Oct 12 04:00:28 AM UTC 24 |
Oct 12 04:00:50 AM UTC 24 |
9896079608 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all.2763026545 |
|
|
Oct 12 03:20:08 AM UTC 24 |
Oct 12 04:00:51 AM UTC 24 |
513708018813 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.2023554765 |
|
|
Oct 12 03:58:42 AM UTC 24 |
Oct 12 04:00:58 AM UTC 24 |
1597480352 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.3251444277 |
|
|
Oct 12 04:00:35 AM UTC 24 |
Oct 12 04:01:07 AM UTC 24 |
1542240821 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_regwen.2217546530 |
|
|
Oct 12 03:41:18 AM UTC 24 |
Oct 12 04:01:12 AM UTC 24 |
3417552290 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.3415214326 |
|
|
Oct 12 04:01:09 AM UTC 24 |
Oct 12 04:01:14 AM UTC 24 |
346528325 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all.3648096987 |
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Oct 12 03:30:53 AM UTC 24 |
Oct 12 04:01:14 AM UTC 24 |
141205350805 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.2447807098 |
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Oct 12 03:52:58 AM UTC 24 |
Oct 12 04:01:19 AM UTC 24 |
82727608588 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_readback_err.37667780 |
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Oct 12 04:01:16 AM UTC 24 |
Oct 12 04:01:28 AM UTC 24 |
666974104 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.2996975616 |
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Oct 12 03:53:54 AM UTC 24 |
Oct 12 04:02:12 AM UTC 24 |
5406865791 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_alert_test.1794351019 |
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Oct 12 04:02:14 AM UTC 24 |
Oct 12 04:02:16 AM UTC 24 |
38692469 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_regwen.1486918235 |
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Oct 12 03:50:20 AM UTC 24 |
Oct 12 04:02:24 AM UTC 24 |
17698407665 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.3572294760 |
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Oct 12 04:01:15 AM UTC 24 |
Oct 12 04:02:32 AM UTC 24 |
5025765455 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.96467414 |
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Oct 12 03:56:49 AM UTC 24 |
Oct 12 04:02:33 AM UTC 24 |
24706751565 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_smoke.2214146806 |
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Oct 12 04:02:17 AM UTC 24 |
Oct 12 04:02:35 AM UTC 24 |
838955813 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.4021365569 |
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Oct 12 04:00:39 AM UTC 24 |
Oct 12 04:02:42 AM UTC 24 |
31801004090 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3888429549 |
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Oct 12 04:01:20 AM UTC 24 |
Oct 12 04:02:48 AM UTC 24 |
3145401548 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.860139593 |
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Oct 12 04:02:49 AM UTC 24 |
Oct 12 04:02:56 AM UTC 24 |
746173503 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_regwen.68390338 |
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Oct 12 03:46:25 AM UTC 24 |
Oct 12 04:03:09 AM UTC 24 |
6335211577 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_executable.1090809091 |
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Oct 12 03:58:16 AM UTC 24 |
Oct 12 04:03:15 AM UTC 24 |
10431750804 ps |