SRAM_CTRL/RET Simulation Results

Thursday May 18 2023 07:04:58 UTC

GitHub Revision: ac0bef2ce

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2907120974

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.489m	1.261ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.670s	23.093us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.690s	22.289us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.160s	1.507ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.690s	11.613us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.480s	303.768us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.690s	22.289us	20	20	100.00
		sram_ctrl_csr_aliasing	0.690s	11.613us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	10.330s	1.827ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.540s	653.677us	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	27.940m	45.951ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.401m	16.869ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.501m	2.290ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	26.182m	5.638ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	15.510s	1.194ms	50	50	100.00
V2	executable	sram_ctrl_executable	26.325m	60.045ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.060m	755.049us	50	50	100.00
		sram_ctrl_partial_access_b2b	9.599m	146.343ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.682m	586.894us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.253m	456.021us	50	50	100.00
V2	regwen	sram_ctrl_regwen	26.104m	86.385ms	48	50	96.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.010s	60.562us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.878h	357.299ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	0.750s	177.236us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.590s	505.853us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.590s	505.853us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.670s	23.093us	5	5	100.00
		sram_ctrl_csr_rw	0.690s	22.289us	20	20	100.00
		sram_ctrl_csr_aliasing	0.690s	11.613us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.850s	58.563us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.670s	23.093us	5	5	100.00
		sram_ctrl_csr_rw	0.690s	22.289us	20	20	100.00
		sram_ctrl_csr_aliasing	0.690s	11.613us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.850s	58.563us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	10.170s	1.604ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.930s	346.946us	5	5	100.00
		sram_ctrl_tl_intg_err	2.510s	277.363us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.930s	346.946us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.510s	277.363us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	26.104m	86.385ms	48	50	96.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.690s	22.289us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	26.325m	60.045ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	26.325m	60.045ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	26.325m	60.045ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	15.510s	1.194ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	10.170s	1.604ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.489m	1.261ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.489m	1.261ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	26.325m	60.045ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.930s	346.946us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	15.510s	1.194ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.930s	346.946us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.930s	346.946us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.489m	1.261ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.930s	346.946us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.719h	1.743ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1038	1040	99.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	15	93.75
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.26	99.16	93.54	100.00	70.00	97.41	99.70	100.00

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 2 failures:
  • Test sram_ctrl_regwen has 2 failures.

    • 22.sram_ctrl_regwen.3225838652
      Line 287, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_regwen/latest/run.log

        UVM_FATAL @ 144749416565 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xe8378a8b
        UVM_INFO @ 144749416565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 26.sram_ctrl_regwen.351010345
      Line 251, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/26.sram_ctrl_regwen/latest/run.log

        UVM_FATAL @ 36433432706 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x337493b0
        UVM_INFO @ 36433432706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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