Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3197150	1			T2	7996		T5	438		T9	1
auto[1]	10361100	1			T1	4368		T2	1922		T4	126130
auto[2]	2558550	1			T2	7276		T5	281		T9	4
auto[3]	9789300	1			T1	4420		T2	1101		T4	126816

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	16843650	1			T1	5918		T2	14407		T4	210881
auto[1]	2514100	1			T1	1312		T2	2003		T4	20086
auto[2]	2329050	1			T1	1304		T2	1676		T4	20164
auto[3]	4219300	1			T1	254		T2	209		T4	1815

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7674200

1

T1

8778

T2

18274

T5

1294

auto[1]

18231900

1

T1

10

T2

21

T4

252946

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1167800	1			T2	6617		T5	21		T9	1
auto[0]	auto[0]	auto[1]	116450	1			T2	648		T5	66		T12	648
auto[0]	auto[0]	auto[2]	118550	1			T2	657		T5	64		T12	657
auto[0]	auto[0]	auto[3]	32500	1			T2	68		T5	286		T12	68
auto[0]	auto[1]	auto[0]	2003000	1			T1	2946		T2	1085		T5	1
auto[0]	auto[1]	auto[1]	293450	1			T1	650		T2	661		T5	65
auto[0]	auto[1]	auto[2]	194500	1			T1	643		T2	113		T5	6
auto[0]	auto[1]	auto[3]	52850	1			T1	126		T2	59		T5	275
auto[0]	auto[2]	auto[0]	1076250	1			T2	6163		T5	9		T9	3
auto[0]	auto[2]	auto[1]	109800	1			T2	640		T5	49		T12	640
auto[0]	auto[2]	auto[2]	80850	1			T2	422		T5	41		T9	1
auto[0]	auto[2]	auto[3]	20950	1			T2	42		T5	182		T12	42
auto[0]	auto[3]	auto[0]	1917650	1			T1	2969		T2	526		T5	1
auto[0]	auto[3]	auto[1]	194950	1			T1	660		T2	53		T5	7
auto[0]	auto[3]	auto[2]	250550	1			T1	656		T2	482		T5	47
auto[0]	auto[3]	auto[3]	44100	1			T1	128		T2	38		T5	174
auto[1]	auto[0]	auto[0]	58050	1			T2	5		T12	5		T66	1134
auto[1]	auto[0]	auto[1]	265000	1			T66	5300		T70	5300		T92	5300
auto[1]	auto[0]	auto[2]	266550	1			T13	1		T66	5328		T70	5328
auto[1]	auto[0]	auto[3]	1172250	1			T2	1		T5	1		T12	1
auto[1]	auto[1]	auto[0]	5272750	1			T1	2		T2	3		T4	105219
auto[1]	auto[1]	auto[1]	740650	1			T1	1		T2	1		T4	9471
auto[1]	auto[1]	auto[2]	574200	1			T4	10544		T15	10544		T66	936
auto[1]	auto[1]	auto[3]	1229700	1			T4	896		T15	896		T66	23698
auto[1]	auto[2]	auto[0]	57900	1			T2	7		T12	7		T66	1131
auto[1]	auto[2]	auto[1]	239500	1			T66	4790		T70	4790		T92	4790
auto[1]	auto[2]	auto[2]	178050	1			T2	1		T12	1		T66	3559
auto[1]	auto[2]	auto[3]	795250	1			T2	1		T12	1		T66	15904
auto[1]	auto[3]	auto[0]	5290250	1			T1	1		T2	1		T4	105662
auto[1]	auto[3]	auto[1]	554300	1			T1	1		T4	10615		T15	10615
auto[1]	auto[3]	auto[2]	665800	1			T1	5		T2	1		T4	9620
auto[1]	auto[3]	auto[3]	871700	1			T4	919		T5	1		T14	1