Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.11	100.00	93.90	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	707139925	78680	0	0
ctrl_regwen_rd_A	707139925	10330	0	0
exec_rd_A	707139925	7790	0	0
exec_regwen_rd_A	707139925	11035	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707139925	78680	0	0
T6	55202	0	0	0
T9	34962	1414	0	0
T10	33085	0	0	0
T11	517974	0	0	0
T12	122906	0	0	0
T13	23960	0	0	0
T14	24931	0	0	0
T15	363519	0	0	0
T16	34962	1414	0	0
T17	0	1414	0	0
T46	0	2	0	0
T48	0	1414	0	0
T49	0	1414	0	0
T50	0	390	0	0
T51	0	7	0	0
T52	0	7	0	0
T53	0	390	0	0
T57	9305	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707139925	10330	0	0
T6	55202	0	0	0
T9	34962	153	0	0
T10	33085	0	0	0
T11	517974	0	0	0
T12	122906	0	0	0
T13	23960	0	0	0
T14	24931	0	0	0
T15	363519	0	0	0
T16	34962	153	0	0
T17	0	153	0	0
T27	0	22	0	0
T28	0	15	0	0
T45	0	22	0	0
T46	0	11	0	0
T48	0	153	0	0
T49	0	153	0	0
T50	0	33	0	0
T57	9305	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707139925	7790	0	0
T6	55202	0	0	0
T9	34962	94	0	0
T10	33085	0	0	0
T11	517974	0	0	0
T12	122906	0	0	0
T13	23960	0	0	0
T14	24931	0	0	0
T15	363519	0	0	0
T16	34962	94	0	0
T17	0	94	0	0
T27	0	35	0	0
T28	0	2	0	0
T45	0	35	0	0
T46	0	34	0	0
T48	0	94	0	0
T49	0	94	0	0
T50	0	40	0	0
T57	9305	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707139925	11035	0	0
T6	55202	0	0	0
T9	34962	168	0	0
T10	33085	0	0	0
T11	517974	0	0	0
T12	122906	0	0	0
T13	23960	0	0	0
T14	24931	0	0	0
T15	363519	0	0	0
T16	34962	168	0	0
T17	0	168	0	0
T27	0	26	0	0
T28	0	4	0	0
T45	0	26	0	0
T46	0	46	0	0
T48	0	168	0	0
T49	0	168	0	0
T50	0	19	0	0
T57	9305	0	0	0