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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.65 100.00 98.13 100.00 100.00 99.71 99.70 100.00


Total test records in report: 1028
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T505 /workspace/coverage/default/30.sram_ctrl_stress_all.2008901061 Dec 20 01:00:27 PM PST 23 Dec 20 01:10:24 PM PST 23 15125647096 ps
T506 /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.704932515 Dec 20 12:58:08 PM PST 23 Dec 20 01:00:01 PM PST 23 1269914181 ps
T507 /workspace/coverage/default/15.sram_ctrl_partial_access.1530414626 Dec 20 12:58:50 PM PST 23 Dec 20 01:00:01 PM PST 23 707279607 ps
T508 /workspace/coverage/default/10.sram_ctrl_access_during_key_req.1066933832 Dec 20 12:58:32 PM PST 23 Dec 20 01:13:05 PM PST 23 4466841341 ps
T509 /workspace/coverage/default/15.sram_ctrl_stress_pipeline.3524895833 Dec 20 12:59:00 PM PST 23 Dec 20 01:01:50 PM PST 23 6472370088 ps
T510 /workspace/coverage/default/17.sram_ctrl_partial_access.4024731550 Dec 20 12:58:58 PM PST 23 Dec 20 01:01:32 PM PST 23 212252787 ps
T511 /workspace/coverage/default/16.sram_ctrl_mem_walk.1337327849 Dec 20 12:58:59 PM PST 23 Dec 20 12:59:21 PM PST 23 597578285 ps
T512 /workspace/coverage/default/36.sram_ctrl_stress_all.3187781201 Dec 20 01:01:03 PM PST 23 Dec 20 01:31:15 PM PST 23 6439166811 ps
T513 /workspace/coverage/default/35.sram_ctrl_multiple_keys.150680721 Dec 20 01:00:58 PM PST 23 Dec 20 01:21:20 PM PST 23 6356177796 ps
T514 /workspace/coverage/default/41.sram_ctrl_executable.3281829975 Dec 20 01:01:34 PM PST 23 Dec 20 01:22:13 PM PST 23 2586190008 ps
T515 /workspace/coverage/default/36.sram_ctrl_mem_partial_access.4017704619 Dec 20 01:00:48 PM PST 23 Dec 20 01:01:15 PM PST 23 164938465 ps
T516 /workspace/coverage/default/37.sram_ctrl_regwen.4099127828 Dec 20 01:01:22 PM PST 23 Dec 20 01:14:46 PM PST 23 29587848023 ps
T517 /workspace/coverage/default/25.sram_ctrl_alert_test.1447633226 Dec 20 01:00:09 PM PST 23 Dec 20 01:00:23 PM PST 23 35607235 ps
T518 /workspace/coverage/default/44.sram_ctrl_bijection.2486717401 Dec 20 01:02:02 PM PST 23 Dec 20 01:03:05 PM PST 23 1264985612 ps
T519 /workspace/coverage/default/43.sram_ctrl_partial_access.1641152933 Dec 20 01:01:29 PM PST 23 Dec 20 01:02:19 PM PST 23 941669792 ps
T520 /workspace/coverage/default/44.sram_ctrl_alert_test.3980946866 Dec 20 01:01:48 PM PST 23 Dec 20 01:02:32 PM PST 23 37176366 ps
T521 /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.835586473 Dec 20 12:58:06 PM PST 23 Dec 20 12:58:30 PM PST 23 320106398 ps
T522 /workspace/coverage/default/37.sram_ctrl_access_during_key_req.2690203220 Dec 20 01:01:24 PM PST 23 Dec 20 01:13:44 PM PST 23 2278339061 ps
T523 /workspace/coverage/default/46.sram_ctrl_executable.1199716988 Dec 20 01:02:28 PM PST 23 Dec 20 01:17:00 PM PST 23 3199771787 ps
T524 /workspace/coverage/default/43.sram_ctrl_ram_cfg.2083382602 Dec 20 01:01:47 PM PST 23 Dec 20 01:02:31 PM PST 23 123023203 ps
T525 /workspace/coverage/default/27.sram_ctrl_smoke.2803162753 Dec 20 01:00:10 PM PST 23 Dec 20 01:00:34 PM PST 23 970149530 ps
T526 /workspace/coverage/default/12.sram_ctrl_ram_cfg.2469441554 Dec 20 12:58:36 PM PST 23 Dec 20 12:58:55 PM PST 23 46476073 ps
T527 /workspace/coverage/default/12.sram_ctrl_lc_escalation.2804469302 Dec 20 12:58:21 PM PST 23 Dec 20 12:58:49 PM PST 23 416415313 ps
T528 /workspace/coverage/default/18.sram_ctrl_multiple_keys.2128246108 Dec 20 12:58:51 PM PST 23 Dec 20 01:04:29 PM PST 23 594483085 ps
T529 /workspace/coverage/default/30.sram_ctrl_max_throughput.1847894440 Dec 20 01:00:24 PM PST 23 Dec 20 01:00:40 PM PST 23 51609118 ps
T530 /workspace/coverage/default/44.sram_ctrl_stress_all.4146534265 Dec 20 01:01:47 PM PST 23 Dec 20 01:22:12 PM PST 23 80035427964 ps
T531 /workspace/coverage/default/4.sram_ctrl_multiple_keys.870907791 Dec 20 12:58:20 PM PST 23 Dec 20 01:01:39 PM PST 23 4183483688 ps
T532 /workspace/coverage/default/8.sram_ctrl_ram_cfg.3632396669 Dec 20 12:58:03 PM PST 23 Dec 20 12:58:18 PM PST 23 81005333 ps
T533 /workspace/coverage/default/14.sram_ctrl_multiple_keys.2632483547 Dec 20 12:58:33 PM PST 23 Dec 20 01:14:42 PM PST 23 58842173383 ps
T534 /workspace/coverage/default/16.sram_ctrl_lc_escalation.2277204001 Dec 20 12:58:57 PM PST 23 Dec 20 12:59:11 PM PST 23 115502151 ps
T535 /workspace/coverage/default/15.sram_ctrl_bijection.2659178134 Dec 20 12:58:54 PM PST 23 Dec 20 01:00:03 PM PST 23 56333510529 ps
T536 /workspace/coverage/default/30.sram_ctrl_alert_test.1877948101 Dec 20 01:00:16 PM PST 23 Dec 20 01:00:31 PM PST 23 14908904 ps
T537 /workspace/coverage/default/36.sram_ctrl_lc_escalation.714042782 Dec 20 01:01:02 PM PST 23 Dec 20 01:01:45 PM PST 23 902505913 ps
T538 /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.3639111770 Dec 20 01:01:28 PM PST 23 Dec 20 01:07:59 PM PST 23 13986837561 ps
T539 /workspace/coverage/default/17.sram_ctrl_max_throughput.3884353930 Dec 20 12:58:54 PM PST 23 Dec 20 12:59:19 PM PST 23 239808853 ps
T540 /workspace/coverage/default/11.sram_ctrl_executable.1297306742 Dec 20 12:58:37 PM PST 23 Dec 20 01:05:46 PM PST 23 101362576266 ps
T541 /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.3636933576 Dec 20 01:01:34 PM PST 23 Dec 20 01:09:11 PM PST 23 61006229218 ps
T542 /workspace/coverage/default/29.sram_ctrl_regwen.3337663941 Dec 20 01:00:32 PM PST 23 Dec 20 01:11:56 PM PST 23 5225118792 ps
T543 /workspace/coverage/default/20.sram_ctrl_alert_test.1215119546 Dec 20 12:59:33 PM PST 23 Dec 20 12:59:46 PM PST 23 42489277 ps
T544 /workspace/coverage/default/28.sram_ctrl_access_during_key_req.1535286600 Dec 20 01:00:31 PM PST 23 Dec 20 01:19:15 PM PST 23 2852432859 ps
T545 /workspace/coverage/default/17.sram_ctrl_mem_walk.4210588554 Dec 20 12:58:56 PM PST 23 Dec 20 12:59:18 PM PST 23 269282706 ps
T546 /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.3830640561 Dec 20 12:59:08 PM PST 23 Dec 20 01:06:40 PM PST 23 160872153289 ps
T547 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.1404509804 Dec 20 01:01:43 PM PST 23 Dec 20 01:07:34 PM PST 23 3339656831 ps
T548 /workspace/coverage/default/43.sram_ctrl_max_throughput.2477981515 Dec 20 01:01:47 PM PST 23 Dec 20 01:02:32 PM PST 23 142301159 ps
T549 /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.4192486940 Dec 20 12:58:09 PM PST 23 Dec 20 01:03:04 PM PST 23 29541674289 ps
T550 /workspace/coverage/default/39.sram_ctrl_executable.3613212640 Dec 20 01:01:28 PM PST 23 Dec 20 01:18:29 PM PST 23 3282420241 ps
T551 /workspace/coverage/default/20.sram_ctrl_multiple_keys.1531804139 Dec 20 12:59:06 PM PST 23 Dec 20 01:14:16 PM PST 23 13987285389 ps
T552 /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1363739292 Dec 20 01:01:00 PM PST 23 Dec 20 01:03:50 PM PST 23 172164964 ps
T553 /workspace/coverage/default/49.sram_ctrl_access_during_key_req.3308451958 Dec 20 01:02:30 PM PST 23 Dec 20 01:16:59 PM PST 23 53087119090 ps
T554 /workspace/coverage/default/37.sram_ctrl_max_throughput.921954255 Dec 20 01:01:13 PM PST 23 Dec 20 01:02:00 PM PST 23 42893771 ps
T555 /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.695386608 Dec 20 12:59:09 PM PST 23 Dec 20 01:24:46 PM PST 23 223057491 ps
T556 /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1323933193 Dec 20 12:58:26 PM PST 23 Dec 20 01:14:17 PM PST 23 883279978 ps
T557 /workspace/coverage/default/38.sram_ctrl_bijection.2648992516 Dec 20 01:01:23 PM PST 23 Dec 20 01:02:48 PM PST 23 2838742064 ps
T558 /workspace/coverage/default/46.sram_ctrl_bijection.2174843752 Dec 20 01:02:24 PM PST 23 Dec 20 01:03:27 PM PST 23 599506209 ps
T559 /workspace/coverage/default/3.sram_ctrl_smoke.3885874568 Dec 20 12:58:08 PM PST 23 Dec 20 12:59:10 PM PST 23 855463645 ps
T560 /workspace/coverage/default/49.sram_ctrl_mem_walk.108245973 Dec 20 01:02:49 PM PST 23 Dec 20 01:03:22 PM PST 23 263937736 ps
T561 /workspace/coverage/default/20.sram_ctrl_executable.3501434057 Dec 20 12:59:14 PM PST 23 Dec 20 01:06:23 PM PST 23 2363995670 ps
T562 /workspace/coverage/default/49.sram_ctrl_bijection.2941756080 Dec 20 01:02:32 PM PST 23 Dec 20 01:03:20 PM PST 23 1664007933 ps
T563 /workspace/coverage/default/14.sram_ctrl_lc_escalation.2897150097 Dec 20 12:58:39 PM PST 23 Dec 20 12:58:59 PM PST 23 70193487 ps
T564 /workspace/coverage/default/30.sram_ctrl_lc_escalation.3176857182 Dec 20 01:00:16 PM PST 23 Dec 20 01:00:35 PM PST 23 819889060 ps
T565 /workspace/coverage/default/6.sram_ctrl_max_throughput.2736200453 Dec 20 12:58:27 PM PST 23 Dec 20 01:00:20 PM PST 23 721430311 ps
T566 /workspace/coverage/default/20.sram_ctrl_mem_walk.3218194670 Dec 20 12:59:05 PM PST 23 Dec 20 12:59:24 PM PST 23 688080692 ps
T567 /workspace/coverage/default/40.sram_ctrl_alert_test.1376534150 Dec 20 01:01:27 PM PST 23 Dec 20 01:02:05 PM PST 23 21529898 ps
T568 /workspace/coverage/default/36.sram_ctrl_ram_cfg.3834649151 Dec 20 01:00:41 PM PST 23 Dec 20 01:00:56 PM PST 23 79543195 ps
T569 /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1751049101 Dec 20 12:58:11 PM PST 23 Dec 20 01:02:22 PM PST 23 3236748166 ps
T570 /workspace/coverage/default/34.sram_ctrl_mem_partial_access.1818883128 Dec 20 01:00:57 PM PST 23 Dec 20 01:01:39 PM PST 23 161489780 ps
T571 /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.1263635358 Dec 20 12:59:53 PM PST 23 Dec 20 01:07:58 PM PST 23 42629698562 ps
T572 /workspace/coverage/default/29.sram_ctrl_multiple_keys.1878189127 Dec 20 01:00:40 PM PST 23 Dec 20 01:17:39 PM PST 23 40460493134 ps
T573 /workspace/coverage/default/6.sram_ctrl_executable.4093547052 Dec 20 12:58:30 PM PST 23 Dec 20 01:21:13 PM PST 23 31081092562 ps
T574 /workspace/coverage/default/9.sram_ctrl_multiple_keys.3676799085 Dec 20 12:58:09 PM PST 23 Dec 20 01:12:42 PM PST 23 7726190559 ps
T575 /workspace/coverage/default/47.sram_ctrl_ram_cfg.2803085012 Dec 20 01:02:40 PM PST 23 Dec 20 01:03:05 PM PST 23 74349237 ps
T576 /workspace/coverage/default/18.sram_ctrl_bijection.188160883 Dec 20 12:58:59 PM PST 23 Dec 20 01:00:22 PM PST 23 9495205235 ps
T577 /workspace/coverage/default/40.sram_ctrl_mem_walk.3604589488 Dec 20 01:01:38 PM PST 23 Dec 20 01:02:30 PM PST 23 544015826 ps
T578 /workspace/coverage/default/44.sram_ctrl_stress_pipeline.3761400771 Dec 20 01:02:02 PM PST 23 Dec 20 01:05:42 PM PST 23 1850295116 ps
T579 /workspace/coverage/default/47.sram_ctrl_regwen.2519409121 Dec 20 01:02:39 PM PST 23 Dec 20 01:13:53 PM PST 23 10451059511 ps
T580 /workspace/coverage/default/34.sram_ctrl_partial_access.3900085717 Dec 20 01:00:45 PM PST 23 Dec 20 01:01:16 PM PST 23 2610982749 ps
T581 /workspace/coverage/default/18.sram_ctrl_ram_cfg.2975351857 Dec 20 12:59:01 PM PST 23 Dec 20 12:59:14 PM PST 23 104462503 ps
T582 /workspace/coverage/default/39.sram_ctrl_stress_pipeline.270090862 Dec 20 01:01:25 PM PST 23 Dec 20 01:07:08 PM PST 23 12686832657 ps
T583 /workspace/coverage/default/1.sram_ctrl_stress_pipeline.998574957 Dec 20 12:58:38 PM PST 23 Dec 20 01:05:44 PM PST 23 4402981994 ps
T584 /workspace/coverage/default/22.sram_ctrl_mem_partial_access.2141867029 Dec 20 12:59:26 PM PST 23 Dec 20 12:59:42 PM PST 23 354408825 ps
T585 /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.1711100832 Dec 20 01:00:38 PM PST 23 Dec 20 01:00:53 PM PST 23 78971627 ps
T586 /workspace/coverage/default/6.sram_ctrl_access_during_key_req.623869380 Dec 20 12:58:11 PM PST 23 Dec 20 12:59:42 PM PST 23 1371846936 ps
T587 /workspace/coverage/default/11.sram_ctrl_partial_access.702138892 Dec 20 12:58:40 PM PST 23 Dec 20 12:59:27 PM PST 23 257753595 ps
T588 /workspace/coverage/default/39.sram_ctrl_mem_walk.534210642 Dec 20 01:01:34 PM PST 23 Dec 20 01:02:21 PM PST 23 1344102813 ps
T589 /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.772745973 Dec 20 01:01:02 PM PST 23 Dec 20 01:07:03 PM PST 23 17864291325 ps
T590 /workspace/coverage/default/2.sram_ctrl_stress_pipeline.2346307002 Dec 20 12:57:59 PM PST 23 Dec 20 01:02:23 PM PST 23 2679955330 ps
T591 /workspace/coverage/default/29.sram_ctrl_ram_cfg.3833964282 Dec 20 01:00:50 PM PST 23 Dec 20 01:01:18 PM PST 23 30571215 ps
T592 /workspace/coverage/default/42.sram_ctrl_stress_pipeline.2590797455 Dec 20 01:01:30 PM PST 23 Dec 20 01:04:15 PM PST 23 5115903210 ps
T593 /workspace/coverage/default/17.sram_ctrl_executable.2367922148 Dec 20 12:59:10 PM PST 23 Dec 20 01:06:22 PM PST 23 4829579548 ps
T594 /workspace/coverage/default/33.sram_ctrl_mem_walk.3398512195 Dec 20 01:01:05 PM PST 23 Dec 20 01:01:54 PM PST 23 274304979 ps
T595 /workspace/coverage/default/11.sram_ctrl_bijection.1230919411 Dec 20 12:58:31 PM PST 23 Dec 20 12:59:09 PM PST 23 1285253896 ps
T25 /workspace/coverage/default/0.sram_ctrl_sec_cm.546995986 Dec 20 12:58:16 PM PST 23 Dec 20 12:58:36 PM PST 23 205697305 ps
T596 /workspace/coverage/default/26.sram_ctrl_mem_partial_access.736907280 Dec 20 01:00:07 PM PST 23 Dec 20 01:00:22 PM PST 23 172620756 ps
T597 /workspace/coverage/default/11.sram_ctrl_multiple_keys.427491758 Dec 20 12:58:16 PM PST 23 Dec 20 12:58:47 PM PST 23 2305922060 ps
T598 /workspace/coverage/default/0.sram_ctrl_mem_walk.992875862 Dec 20 12:58:24 PM PST 23 Dec 20 12:58:48 PM PST 23 443848523 ps
T599 /workspace/coverage/default/34.sram_ctrl_regwen.265633708 Dec 20 01:00:59 PM PST 23 Dec 20 01:02:20 PM PST 23 10225604320 ps
T600 /workspace/coverage/default/29.sram_ctrl_partial_access.82282106 Dec 20 01:00:12 PM PST 23 Dec 20 01:00:45 PM PST 23 1195722574 ps
T601 /workspace/coverage/default/13.sram_ctrl_partial_access.4000648889 Dec 20 12:58:18 PM PST 23 Dec 20 12:58:38 PM PST 23 53055535 ps
T602 /workspace/coverage/default/47.sram_ctrl_alert_test.3069442961 Dec 20 01:03:05 PM PST 23 Dec 20 01:03:30 PM PST 23 12289680 ps
T603 /workspace/coverage/default/49.sram_ctrl_lc_escalation.3202765644 Dec 20 01:02:28 PM PST 23 Dec 20 01:02:57 PM PST 23 1333226384 ps
T604 /workspace/coverage/default/43.sram_ctrl_mem_partial_access.2305833576 Dec 20 01:01:48 PM PST 23 Dec 20 01:02:35 PM PST 23 85572696 ps
T605 /workspace/coverage/default/30.sram_ctrl_mem_partial_access.1559686147 Dec 20 01:00:35 PM PST 23 Dec 20 01:00:52 PM PST 23 125999815 ps
T606 /workspace/coverage/default/1.sram_ctrl_multiple_keys.642662914 Dec 20 12:58:36 PM PST 23 Dec 20 01:01:51 PM PST 23 3470532344 ps
T607 /workspace/coverage/default/25.sram_ctrl_partial_access.3975964207 Dec 20 01:00:25 PM PST 23 Dec 20 01:00:37 PM PST 23 262832217 ps
T608 /workspace/coverage/default/35.sram_ctrl_mem_partial_access.552091982 Dec 20 01:00:59 PM PST 23 Dec 20 01:01:41 PM PST 23 584272106 ps
T609 /workspace/coverage/default/2.sram_ctrl_max_throughput.1373395789 Dec 20 12:58:02 PM PST 23 Dec 20 12:59:23 PM PST 23 115151936 ps
T610 /workspace/coverage/default/18.sram_ctrl_stress_pipeline.2149436290 Dec 20 12:59:02 PM PST 23 Dec 20 01:03:18 PM PST 23 5004215802 ps
T611 /workspace/coverage/default/4.sram_ctrl_partial_access.3624683312 Dec 20 12:57:58 PM PST 23 Dec 20 12:58:28 PM PST 23 2900862126 ps
T612 /workspace/coverage/default/17.sram_ctrl_bijection.1621980684 Dec 20 12:59:02 PM PST 23 Dec 20 12:59:43 PM PST 23 9642839589 ps
T613 /workspace/coverage/default/36.sram_ctrl_executable.2034433268 Dec 20 01:00:43 PM PST 23 Dec 20 01:23:02 PM PST 23 16971984776 ps
T614 /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3384692677 Dec 20 01:01:29 PM PST 23 Dec 20 01:02:09 PM PST 23 185611860 ps
T615 /workspace/coverage/default/30.sram_ctrl_regwen.2941649391 Dec 20 01:00:16 PM PST 23 Dec 20 01:18:50 PM PST 23 85385569073 ps
T616 /workspace/coverage/default/37.sram_ctrl_ram_cfg.1794219370 Dec 20 01:01:12 PM PST 23 Dec 20 01:01:58 PM PST 23 115412307 ps
T617 /workspace/coverage/default/3.sram_ctrl_mem_walk.4079715121 Dec 20 12:58:18 PM PST 23 Dec 20 12:58:45 PM PST 23 1315987001 ps
T618 /workspace/coverage/default/45.sram_ctrl_access_during_key_req.2744486826 Dec 20 01:02:10 PM PST 23 Dec 20 01:10:22 PM PST 23 11431721284 ps
T619 /workspace/coverage/default/10.sram_ctrl_bijection.1302223561 Dec 20 12:58:21 PM PST 23 Dec 20 12:59:12 PM PST 23 570248895 ps
T620 /workspace/coverage/default/23.sram_ctrl_stress_pipeline.173820282 Dec 20 12:59:36 PM PST 23 Dec 20 01:04:46 PM PST 23 11681310009 ps
T621 /workspace/coverage/default/25.sram_ctrl_executable.4097044529 Dec 20 12:59:57 PM PST 23 Dec 20 01:13:34 PM PST 23 10080599540 ps
T622 /workspace/coverage/default/38.sram_ctrl_partial_access.3176480602 Dec 20 01:01:13 PM PST 23 Dec 20 01:02:14 PM PST 23 308745613 ps
T623 /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.1479133956 Dec 20 01:00:06 PM PST 23 Dec 20 01:29:36 PM PST 23 2291257908 ps
T624 /workspace/coverage/default/20.sram_ctrl_mem_partial_access.1012212525 Dec 20 12:59:25 PM PST 23 Dec 20 12:59:41 PM PST 23 170745653 ps
T625 /workspace/coverage/default/1.sram_ctrl_executable.1038313280 Dec 20 12:58:37 PM PST 23 Dec 20 01:05:00 PM PST 23 25858286663 ps
T626 /workspace/coverage/default/33.sram_ctrl_executable.2435189292 Dec 20 01:00:58 PM PST 23 Dec 20 01:14:44 PM PST 23 26045076486 ps
T627 /workspace/coverage/default/13.sram_ctrl_regwen.1849406927 Dec 20 12:58:21 PM PST 23 Dec 20 01:10:56 PM PST 23 1792208463 ps
T628 /workspace/coverage/default/0.sram_ctrl_mem_partial_access.2949087021 Dec 20 12:58:21 PM PST 23 Dec 20 12:58:43 PM PST 23 585741966 ps
T629 /workspace/coverage/default/9.sram_ctrl_bijection.610754097 Dec 20 12:58:26 PM PST 23 Dec 20 12:59:55 PM PST 23 16463350546 ps
T630 /workspace/coverage/default/32.sram_ctrl_alert_test.1503356512 Dec 20 01:01:01 PM PST 23 Dec 20 01:01:41 PM PST 23 11623110 ps
T631 /workspace/coverage/default/13.sram_ctrl_bijection.697905533 Dec 20 12:58:23 PM PST 23 Dec 20 12:59:16 PM PST 23 6400514144 ps
T632 /workspace/coverage/default/4.sram_ctrl_smoke.2402310779 Dec 20 12:58:00 PM PST 23 Dec 20 12:58:21 PM PST 23 679308367 ps
T633 /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3544586681 Dec 20 01:02:28 PM PST 23 Dec 20 01:57:52 PM PST 23 381850422 ps
T634 /workspace/coverage/default/22.sram_ctrl_stress_pipeline.3316633084 Dec 20 12:59:32 PM PST 23 Dec 20 01:03:54 PM PST 23 3822071033 ps
T635 /workspace/coverage/default/9.sram_ctrl_smoke.1676181071 Dec 20 12:58:11 PM PST 23 Dec 20 12:59:53 PM PST 23 129369903 ps
T636 /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2071832836 Dec 20 01:00:37 PM PST 23 Dec 20 01:41:58 PM PST 23 3577383494 ps
T637 /workspace/coverage/default/11.sram_ctrl_access_during_key_req.1006166364 Dec 20 12:58:40 PM PST 23 Dec 20 01:01:07 PM PST 23 1639941640 ps
T638 /workspace/coverage/default/22.sram_ctrl_bijection.2531435997 Dec 20 12:59:29 PM PST 23 Dec 20 01:00:14 PM PST 23 6775478788 ps
T639 /workspace/coverage/default/33.sram_ctrl_regwen.1324856582 Dec 20 01:01:08 PM PST 23 Dec 20 01:05:16 PM PST 23 2560673221 ps
T640 /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2408224581 Dec 20 01:01:35 PM PST 23 Dec 20 01:43:11 PM PST 23 2053680637 ps
T641 /workspace/coverage/default/39.sram_ctrl_max_throughput.264069864 Dec 20 01:01:34 PM PST 23 Dec 20 01:03:34 PM PST 23 303194175 ps
T642 /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.1246446063 Dec 20 01:01:12 PM PST 23 Dec 20 01:02:27 PM PST 23 111553971 ps
T643 /workspace/coverage/default/5.sram_ctrl_mem_walk.2436728241 Dec 20 12:58:12 PM PST 23 Dec 20 12:58:35 PM PST 23 77662260 ps
T644 /workspace/coverage/default/41.sram_ctrl_alert_test.3861211969 Dec 20 01:01:39 PM PST 23 Dec 20 01:02:23 PM PST 23 32604145 ps
T645 /workspace/coverage/default/44.sram_ctrl_mem_partial_access.684300860 Dec 20 01:01:46 PM PST 23 Dec 20 01:02:32 PM PST 23 96181607 ps
T646 /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3341448385 Dec 20 01:01:10 PM PST 23 Dec 20 01:35:15 PM PST 23 188915564 ps
T647 /workspace/coverage/default/37.sram_ctrl_mem_partial_access.1040410073 Dec 20 01:01:10 PM PST 23 Dec 20 01:01:56 PM PST 23 1016539418 ps
T648 /workspace/coverage/default/28.sram_ctrl_multiple_keys.2703944891 Dec 20 01:00:49 PM PST 23 Dec 20 01:20:55 PM PST 23 23334099360 ps
T649 /workspace/coverage/default/44.sram_ctrl_access_during_key_req.1055716992 Dec 20 01:01:45 PM PST 23 Dec 20 01:15:15 PM PST 23 10219606859 ps
T650 /workspace/coverage/default/13.sram_ctrl_ram_cfg.2518662116 Dec 20 12:58:16 PM PST 23 Dec 20 12:58:35 PM PST 23 81235019 ps
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T731 /workspace/coverage/default/10.sram_ctrl_mem_partial_access.2250560131 Dec 20 12:58:24 PM PST 23 Dec 20 12:58:46 PM PST 23 242649968 ps
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T739 /workspace/coverage/default/46.sram_ctrl_partial_access.4003508959 Dec 20 01:02:22 PM PST 23 Dec 20 01:03:05 PM PST 23 1250771523 ps
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T741 /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.4202758674 Dec 20 12:58:24 PM PST 23 Dec 20 01:03:15 PM PST 23 28327945240 ps
T742 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.4236414085 Dec 20 01:01:00 PM PST 23 Dec 20 01:18:56 PM PST 23 5522922247 ps
T743 /workspace/coverage/default/44.sram_ctrl_regwen.564995351 Dec 20 01:01:44 PM PST 23 Dec 20 01:10:34 PM PST 23 7009471255 ps
T744 /workspace/coverage/default/3.sram_ctrl_ram_cfg.1160105347 Dec 20 12:58:02 PM PST 23 Dec 20 12:58:17 PM PST 23 103670187 ps
T745 /workspace/coverage/default/45.sram_ctrl_stress_pipeline.108905191 Dec 20 01:01:50 PM PST 23 Dec 20 01:06:33 PM PST 23 15342133208 ps
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T747 /workspace/coverage/default/0.sram_ctrl_lc_escalation.161409337 Dec 20 12:58:13 PM PST 23 Dec 20 12:58:38 PM PST 23 1044024339 ps
T748 /workspace/coverage/default/14.sram_ctrl_ram_cfg.1124953933 Dec 20 12:58:28 PM PST 23 Dec 20 12:58:48 PM PST 23 28195384 ps
T749 /workspace/coverage/default/42.sram_ctrl_regwen.1486248213 Dec 20 01:01:34 PM PST 23 Dec 20 01:25:14 PM PST 23 47856898566 ps
T750 /workspace/coverage/default/41.sram_ctrl_bijection.712645196 Dec 20 01:01:30 PM PST 23 Dec 20 01:02:24 PM PST 23 982615325 ps
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T752 /workspace/coverage/default/32.sram_ctrl_access_during_key_req.4244924375 Dec 20 01:00:40 PM PST 23 Dec 20 01:14:50 PM PST 23 2042726255 ps
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