| T503 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.3357328666 |
|
|
Dec 24 12:36:40 PM PST 23 |
Dec 24 01:01:22 PM PST 23 |
10718926631 ps |
| T504 |
/workspace/coverage/default/42.sram_ctrl_regwen.329627962 |
|
|
Dec 24 12:37:13 PM PST 23 |
Dec 24 01:10:44 PM PST 23 |
31990646839 ps |
| T505 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.4116709455 |
|
|
Dec 24 12:35:15 PM PST 23 |
Dec 24 12:35:47 PM PST 23 |
86281399 ps |
| T506 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.265602170 |
|
|
Dec 24 12:36:11 PM PST 23 |
Dec 24 12:36:40 PM PST 23 |
681637792 ps |
| T507 |
/workspace/coverage/default/34.sram_ctrl_regwen.4024127179 |
|
|
Dec 24 12:36:29 PM PST 23 |
Dec 24 12:37:42 PM PST 23 |
6605518360 ps |
| T508 |
/workspace/coverage/default/21.sram_ctrl_regwen.81864568 |
|
|
Dec 24 12:36:06 PM PST 23 |
Dec 24 12:51:08 PM PST 23 |
12344637607 ps |
| T509 |
/workspace/coverage/default/38.sram_ctrl_regwen.2184640606 |
|
|
Dec 24 12:36:49 PM PST 23 |
Dec 24 01:02:30 PM PST 23 |
67372840927 ps |
| T510 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.2601771381 |
|
|
Dec 24 12:36:27 PM PST 23 |
Dec 24 12:36:47 PM PST 23 |
29878934 ps |
| T511 |
/workspace/coverage/default/7.sram_ctrl_stress_all.1271503163 |
|
|
Dec 24 12:35:20 PM PST 23 |
Dec 24 01:28:42 PM PST 23 |
86110121239 ps |
| T512 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.1390948989 |
|
|
Dec 24 12:36:34 PM PST 23 |
Dec 24 12:36:55 PM PST 23 |
890589634 ps |
| T513 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3841920439 |
|
|
Dec 24 12:35:54 PM PST 23 |
Dec 24 12:36:41 PM PST 23 |
99438492 ps |
| T514 |
/workspace/coverage/default/8.sram_ctrl_bijection.264139644 |
|
|
Dec 24 12:35:28 PM PST 23 |
Dec 24 12:36:10 PM PST 23 |
274483388 ps |
| T515 |
/workspace/coverage/default/35.sram_ctrl_smoke.4233033802 |
|
|
Dec 24 12:36:28 PM PST 23 |
Dec 24 12:36:50 PM PST 23 |
130652876 ps |
| T516 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.2664803053 |
|
|
Dec 24 12:35:15 PM PST 23 |
Dec 24 12:35:51 PM PST 23 |
958429563 ps |
| T517 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2862549514 |
|
|
Dec 24 12:37:18 PM PST 23 |
Dec 24 01:53:36 PM PST 23 |
3183798637 ps |
| T518 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.616156114 |
|
|
Dec 24 12:36:01 PM PST 23 |
Dec 24 12:36:22 PM PST 23 |
84979429 ps |
| T519 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.1129657456 |
|
|
Dec 24 12:35:32 PM PST 23 |
Dec 24 12:36:09 PM PST 23 |
5551159856 ps |
| T520 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2146985111 |
|
|
Dec 24 12:35:23 PM PST 23 |
Dec 24 12:36:01 PM PST 23 |
5076287453 ps |
| T521 |
/workspace/coverage/default/46.sram_ctrl_bijection.3439322632 |
|
|
Dec 24 12:37:43 PM PST 23 |
Dec 24 12:38:25 PM PST 23 |
4923291047 ps |
| T522 |
/workspace/coverage/default/3.sram_ctrl_smoke.2530132590 |
|
|
Dec 24 12:35:03 PM PST 23 |
Dec 24 12:36:40 PM PST 23 |
438312598 ps |
| T523 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.2404862858 |
|
|
Dec 24 12:36:18 PM PST 23 |
Dec 24 12:37:23 PM PST 23 |
484497422 ps |
| T524 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.3586708058 |
|
|
Dec 24 12:37:09 PM PST 23 |
Dec 24 12:37:24 PM PST 23 |
85801386 ps |
| T525 |
/workspace/coverage/default/5.sram_ctrl_alert_test.2714588376 |
|
|
Dec 24 12:35:13 PM PST 23 |
Dec 24 12:35:44 PM PST 23 |
18863706 ps |
| T526 |
/workspace/coverage/default/43.sram_ctrl_stress_all.3607956627 |
|
|
Dec 24 12:37:01 PM PST 23 |
Dec 24 01:12:48 PM PST 23 |
39146436739 ps |
| T527 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.603305109 |
|
|
Dec 24 12:35:28 PM PST 23 |
Dec 24 12:35:54 PM PST 23 |
32272382 ps |
| T528 |
/workspace/coverage/default/26.sram_ctrl_stress_all.1454556928 |
|
|
Dec 24 12:36:14 PM PST 23 |
Dec 24 02:26:21 PM PST 23 |
208606317644 ps |
| T529 |
/workspace/coverage/default/40.sram_ctrl_smoke.1611307666 |
|
|
Dec 24 12:36:50 PM PST 23 |
Dec 24 12:37:28 PM PST 23 |
3989040794 ps |
| T530 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.931862381 |
|
|
Dec 24 12:35:46 PM PST 23 |
Dec 24 12:37:08 PM PST 23 |
221071515 ps |
| T531 |
/workspace/coverage/default/20.sram_ctrl_regwen.2528648755 |
|
|
Dec 24 12:36:26 PM PST 23 |
Dec 24 12:55:12 PM PST 23 |
11188093950 ps |
| T532 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.4001205253 |
|
|
Dec 24 12:36:20 PM PST 23 |
Dec 24 12:36:42 PM PST 23 |
154502135 ps |
| T533 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3061394513 |
|
|
Dec 24 12:37:02 PM PST 23 |
Dec 24 12:37:57 PM PST 23 |
115733014 ps |
| T534 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2163472101 |
|
|
Dec 24 12:35:23 PM PST 23 |
Dec 24 01:01:08 PM PST 23 |
738419240 ps |
| T535 |
/workspace/coverage/default/10.sram_ctrl_executable.3175843387 |
|
|
Dec 24 12:35:32 PM PST 23 |
Dec 24 12:42:57 PM PST 23 |
2188700911 ps |
| T536 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.3348780831 |
|
|
Dec 24 12:36:41 PM PST 23 |
Dec 24 12:43:43 PM PST 23 |
15988871415 ps |
| T537 |
/workspace/coverage/default/46.sram_ctrl_alert_test.2016340354 |
|
|
Dec 24 12:37:22 PM PST 23 |
Dec 24 12:37:35 PM PST 23 |
11708224 ps |
| T538 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2220651420 |
|
|
Dec 24 12:37:25 PM PST 23 |
Dec 24 12:38:10 PM PST 23 |
110228625 ps |
| T539 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.3694381203 |
|
|
Dec 24 12:34:58 PM PST 23 |
Dec 24 12:35:34 PM PST 23 |
37149840 ps |
| T540 |
/workspace/coverage/default/47.sram_ctrl_alert_test.3516422264 |
|
|
Dec 24 12:37:40 PM PST 23 |
Dec 24 12:37:47 PM PST 23 |
17636887 ps |
| T541 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2446921780 |
|
|
Dec 24 12:36:46 PM PST 23 |
Dec 24 12:37:55 PM PST 23 |
453873392 ps |
| T542 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.951887185 |
|
|
Dec 24 12:36:55 PM PST 23 |
Dec 24 12:47:39 PM PST 23 |
405543000424 ps |
| T543 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.2233935257 |
|
|
Dec 24 12:36:59 PM PST 23 |
Dec 24 12:47:21 PM PST 23 |
2894909258 ps |
| T544 |
/workspace/coverage/default/27.sram_ctrl_regwen.3184717466 |
|
|
Dec 24 12:36:13 PM PST 23 |
Dec 24 12:46:58 PM PST 23 |
28193580244 ps |
| T545 |
/workspace/coverage/default/7.sram_ctrl_alert_test.3344855191 |
|
|
Dec 24 12:35:35 PM PST 23 |
Dec 24 12:36:01 PM PST 23 |
39785192 ps |
| T546 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.218533890 |
|
|
Dec 24 12:36:01 PM PST 23 |
Dec 24 12:36:25 PM PST 23 |
230739182 ps |
| T547 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.2810811402 |
|
|
Dec 24 12:36:07 PM PST 23 |
Dec 24 01:02:13 PM PST 23 |
72487888622 ps |
| T548 |
/workspace/coverage/default/9.sram_ctrl_executable.2882176936 |
|
|
Dec 24 12:35:42 PM PST 23 |
Dec 24 12:36:26 PM PST 23 |
1088874286 ps |
| T549 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.2559706663 |
|
|
Dec 24 12:36:17 PM PST 23 |
Dec 24 12:36:40 PM PST 23 |
281120901 ps |
| T550 |
/workspace/coverage/default/15.sram_ctrl_alert_test.98732340 |
|
|
Dec 24 12:36:07 PM PST 23 |
Dec 24 12:36:27 PM PST 23 |
21138038 ps |
| T551 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.2470547654 |
|
|
Dec 24 12:35:38 PM PST 23 |
Dec 24 12:36:03 PM PST 23 |
719061772 ps |
| T552 |
/workspace/coverage/default/9.sram_ctrl_regwen.2315907823 |
|
|
Dec 24 12:36:00 PM PST 23 |
Dec 24 12:42:45 PM PST 23 |
8542159228 ps |
| T553 |
/workspace/coverage/default/29.sram_ctrl_stress_all.2498769079 |
|
|
Dec 24 12:36:20 PM PST 23 |
Dec 24 01:12:53 PM PST 23 |
153609164568 ps |
| T554 |
/workspace/coverage/default/24.sram_ctrl_alert_test.532769424 |
|
|
Dec 24 12:36:14 PM PST 23 |
Dec 24 12:36:32 PM PST 23 |
33368601 ps |
| T555 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.3789915464 |
|
|
Dec 24 12:36:53 PM PST 23 |
Dec 24 12:38:53 PM PST 23 |
2242266087 ps |
| T556 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.733389733 |
|
|
Dec 24 12:36:29 PM PST 23 |
Dec 24 12:45:10 PM PST 23 |
1179729681 ps |
| T557 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.2605600182 |
|
|
Dec 24 12:36:58 PM PST 23 |
Dec 24 12:37:19 PM PST 23 |
608317984 ps |
| T558 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.2563849917 |
|
|
Dec 24 12:36:12 PM PST 23 |
Dec 24 12:36:31 PM PST 23 |
233536916 ps |
| T559 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3422041887 |
|
|
Dec 24 12:35:39 PM PST 23 |
Dec 24 12:36:31 PM PST 23 |
200835228 ps |
| T560 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.2706692746 |
|
|
Dec 24 12:35:38 PM PST 23 |
Dec 24 12:36:05 PM PST 23 |
45120924 ps |
| T561 |
/workspace/coverage/default/33.sram_ctrl_stress_all.3216512151 |
|
|
Dec 24 12:36:41 PM PST 23 |
Dec 24 01:34:19 PM PST 23 |
35438654730 ps |
| T562 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.1450127860 |
|
|
Dec 24 12:36:19 PM PST 23 |
Dec 24 01:13:50 PM PST 23 |
227584658 ps |
| T563 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.4115730205 |
|
|
Dec 24 12:37:33 PM PST 23 |
Dec 24 12:43:06 PM PST 23 |
13732126935 ps |
| T564 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.127775580 |
|
|
Dec 24 12:37:52 PM PST 23 |
Dec 24 12:37:58 PM PST 23 |
321362113 ps |
| T565 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2092922263 |
|
|
Dec 24 12:37:31 PM PST 23 |
Dec 24 01:58:33 PM PST 23 |
1607904487 ps |
| T566 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.4114505394 |
|
|
Dec 24 12:36:14 PM PST 23 |
Dec 24 12:47:11 PM PST 23 |
20007039326 ps |
| T567 |
/workspace/coverage/default/34.sram_ctrl_smoke.1816796454 |
|
|
Dec 24 12:36:45 PM PST 23 |
Dec 24 12:37:20 PM PST 23 |
4617318048 ps |
| T568 |
/workspace/coverage/default/48.sram_ctrl_stress_all.3839277109 |
|
|
Dec 24 12:37:43 PM PST 23 |
Dec 24 02:07:19 PM PST 23 |
367413288436 ps |
| T569 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.3415605744 |
|
|
Dec 24 12:35:22 PM PST 23 |
Dec 24 12:35:51 PM PST 23 |
37414160 ps |
| T570 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.1635127278 |
|
|
Dec 24 12:37:07 PM PST 23 |
Dec 24 12:50:26 PM PST 23 |
38048551458 ps |
| T571 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.4000304124 |
|
|
Dec 24 12:35:25 PM PST 23 |
Dec 24 12:35:56 PM PST 23 |
305075853 ps |
| T572 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.2522317319 |
|
|
Dec 24 12:35:46 PM PST 23 |
Dec 24 12:36:15 PM PST 23 |
4018065607 ps |
| T573 |
/workspace/coverage/default/13.sram_ctrl_regwen.451308439 |
|
|
Dec 24 12:35:22 PM PST 23 |
Dec 24 01:03:28 PM PST 23 |
52046535594 ps |
| T574 |
/workspace/coverage/default/40.sram_ctrl_partial_access.2296040890 |
|
|
Dec 24 12:37:11 PM PST 23 |
Dec 24 12:38:11 PM PST 23 |
524419202 ps |
| T575 |
/workspace/coverage/default/22.sram_ctrl_alert_test.3570047713 |
|
|
Dec 24 12:35:58 PM PST 23 |
Dec 24 12:36:18 PM PST 23 |
41043030 ps |
| T576 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.3504495175 |
|
|
Dec 24 12:35:20 PM PST 23 |
Dec 24 12:40:22 PM PST 23 |
23426577892 ps |
| T577 |
/workspace/coverage/default/47.sram_ctrl_partial_access.521421411 |
|
|
Dec 24 12:37:35 PM PST 23 |
Dec 24 12:37:57 PM PST 23 |
1332127225 ps |
| T578 |
/workspace/coverage/default/33.sram_ctrl_bijection.1828419753 |
|
|
Dec 24 12:36:25 PM PST 23 |
Dec 24 12:37:18 PM PST 23 |
2138837903 ps |
| T579 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.3067019142 |
|
|
Dec 24 12:35:23 PM PST 23 |
Dec 24 12:36:53 PM PST 23 |
453960992 ps |
| T580 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2838915664 |
|
|
Dec 24 12:35:36 PM PST 23 |
Dec 24 12:37:33 PM PST 23 |
299713060 ps |
| T581 |
/workspace/coverage/default/18.sram_ctrl_partial_access.4239432664 |
|
|
Dec 24 12:35:52 PM PST 23 |
Dec 24 12:36:28 PM PST 23 |
1753788608 ps |
| T582 |
/workspace/coverage/default/5.sram_ctrl_partial_access.3465277843 |
|
|
Dec 24 12:35:24 PM PST 23 |
Dec 24 12:36:32 PM PST 23 |
1734599901 ps |
| T583 |
/workspace/coverage/default/13.sram_ctrl_stress_all.237044969 |
|
|
Dec 24 12:35:40 PM PST 23 |
Dec 24 01:19:15 PM PST 23 |
27732067759 ps |
| T584 |
/workspace/coverage/default/9.sram_ctrl_smoke.567556538 |
|
|
Dec 24 12:35:37 PM PST 23 |
Dec 24 12:36:37 PM PST 23 |
1639485541 ps |
| T585 |
/workspace/coverage/default/8.sram_ctrl_smoke.4246342417 |
|
|
Dec 24 12:35:36 PM PST 23 |
Dec 24 12:36:04 PM PST 23 |
307321296 ps |
| T586 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1793401219 |
|
|
Dec 24 12:35:47 PM PST 23 |
Dec 24 01:29:55 PM PST 23 |
2532663783 ps |
| T587 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.2473634909 |
|
|
Dec 24 12:35:57 PM PST 23 |
Dec 24 12:50:40 PM PST 23 |
20172614116 ps |
| T588 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.3106551737 |
|
|
Dec 24 12:36:25 PM PST 23 |
Dec 24 12:36:52 PM PST 23 |
141884022 ps |
| T589 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.1372662441 |
|
|
Dec 24 12:35:55 PM PST 23 |
Dec 24 12:36:29 PM PST 23 |
81301051 ps |
| T590 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.4293126595 |
|
|
Dec 24 12:36:11 PM PST 23 |
Dec 24 12:38:08 PM PST 23 |
573281288 ps |
| T591 |
/workspace/coverage/default/7.sram_ctrl_executable.2120522851 |
|
|
Dec 24 12:35:18 PM PST 23 |
Dec 24 01:00:01 PM PST 23 |
3971114262 ps |
| T592 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3152340749 |
|
|
Dec 24 12:35:09 PM PST 23 |
Dec 24 12:45:53 PM PST 23 |
2629377933 ps |
| T593 |
/workspace/coverage/default/28.sram_ctrl_bijection.1069922359 |
|
|
Dec 24 12:36:09 PM PST 23 |
Dec 24 12:37:16 PM PST 23 |
35188760861 ps |
| T594 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.1783582395 |
|
|
Dec 24 12:36:09 PM PST 23 |
Dec 24 12:36:29 PM PST 23 |
40141871 ps |
| T595 |
/workspace/coverage/default/49.sram_ctrl_alert_test.1475672899 |
|
|
Dec 24 12:37:39 PM PST 23 |
Dec 24 12:37:47 PM PST 23 |
15049118 ps |
| T596 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1874495341 |
|
|
Dec 24 12:37:26 PM PST 23 |
Dec 24 12:37:46 PM PST 23 |
125763240 ps |
| T597 |
/workspace/coverage/default/6.sram_ctrl_partial_access.3152671993 |
|
|
Dec 24 12:35:24 PM PST 23 |
Dec 24 12:35:54 PM PST 23 |
134541238 ps |
| T598 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.206794666 |
|
|
Dec 24 12:35:25 PM PST 23 |
Dec 24 12:47:08 PM PST 23 |
4421442797 ps |
| T599 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.619366245 |
|
|
Dec 24 12:36:08 PM PST 23 |
Dec 24 12:37:25 PM PST 23 |
1081233240 ps |
| T600 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.3262625816 |
|
|
Dec 24 12:35:10 PM PST 23 |
Dec 24 12:50:56 PM PST 23 |
18812317668 ps |
| T601 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.1339388303 |
|
|
Dec 24 12:37:11 PM PST 23 |
Dec 24 12:37:26 PM PST 23 |
27058643 ps |
| T602 |
/workspace/coverage/default/0.sram_ctrl_bijection.2205864825 |
|
|
Dec 24 12:35:25 PM PST 23 |
Dec 24 12:36:16 PM PST 23 |
421849266 ps |
| T603 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.3865008198 |
|
|
Dec 24 12:35:35 PM PST 23 |
Dec 24 12:36:04 PM PST 23 |
502978806 ps |
| T604 |
/workspace/coverage/default/22.sram_ctrl_smoke.2443123655 |
|
|
Dec 24 12:36:06 PM PST 23 |
Dec 24 12:36:29 PM PST 23 |
248955904 ps |
| T605 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.79918783 |
|
|
Dec 24 12:36:58 PM PST 23 |
Dec 24 12:37:24 PM PST 23 |
2915424249 ps |
| T606 |
/workspace/coverage/default/23.sram_ctrl_smoke.3255808543 |
|
|
Dec 24 12:36:12 PM PST 23 |
Dec 24 12:36:33 PM PST 23 |
66616927 ps |
| T607 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1741723633 |
|
|
Dec 24 12:35:08 PM PST 23 |
Dec 24 12:43:42 PM PST 23 |
4979558650 ps |
| T608 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.1778189417 |
|
|
Dec 24 12:36:06 PM PST 23 |
Dec 24 12:38:54 PM PST 23 |
1015379919 ps |
| T609 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.85033769 |
|
|
Dec 24 12:37:05 PM PST 23 |
Dec 24 12:44:21 PM PST 23 |
123105173185 ps |
| T610 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.2894336436 |
|
|
Dec 24 12:36:05 PM PST 23 |
Dec 24 12:36:29 PM PST 23 |
336026154 ps |
| T611 |
/workspace/coverage/default/19.sram_ctrl_partial_access.607669328 |
|
|
Dec 24 12:35:58 PM PST 23 |
Dec 24 12:36:27 PM PST 23 |
598640120 ps |
| T612 |
/workspace/coverage/default/39.sram_ctrl_bijection.1471615522 |
|
|
Dec 24 12:37:14 PM PST 23 |
Dec 24 12:38:43 PM PST 23 |
3598558865 ps |
| T613 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.2812627812 |
|
|
Dec 24 12:36:55 PM PST 23 |
Dec 24 01:05:52 PM PST 23 |
4166014668 ps |
| T614 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.3646764038 |
|
|
Dec 24 12:36:57 PM PST 23 |
Dec 24 12:37:16 PM PST 23 |
79861595 ps |
| T615 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.2590075501 |
|
|
Dec 24 12:35:59 PM PST 23 |
Dec 24 12:37:32 PM PST 23 |
132799274 ps |
| T616 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.2326988657 |
|
|
Dec 24 12:36:05 PM PST 23 |
Dec 24 12:36:36 PM PST 23 |
735884499 ps |
| T617 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.4005562960 |
|
|
Dec 24 12:36:37 PM PST 23 |
Dec 24 12:37:00 PM PST 23 |
332020537 ps |
| T618 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.1775768307 |
|
|
Dec 24 12:36:25 PM PST 23 |
Dec 24 12:37:07 PM PST 23 |
1437242063 ps |
| T619 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.2327616370 |
|
|
Dec 24 12:36:08 PM PST 23 |
Dec 24 12:36:28 PM PST 23 |
80268692 ps |
| T620 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.1086889518 |
|
|
Dec 24 12:36:25 PM PST 23 |
Dec 24 01:00:16 PM PST 23 |
10023630971 ps |
| T621 |
/workspace/coverage/default/6.sram_ctrl_regwen.391897431 |
|
|
Dec 24 12:35:26 PM PST 23 |
Dec 24 12:50:50 PM PST 23 |
9533932209 ps |
| T622 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1038339044 |
|
|
Dec 24 12:35:13 PM PST 23 |
Dec 24 12:36:26 PM PST 23 |
440292899 ps |
| T623 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2911623990 |
|
|
Dec 24 12:35:21 PM PST 23 |
Dec 24 12:42:01 PM PST 23 |
16663760671 ps |
| T624 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.2730569379 |
|
|
Dec 24 12:36:36 PM PST 23 |
Dec 24 12:36:56 PM PST 23 |
144423064 ps |
| T625 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.2132071060 |
|
|
Dec 24 12:36:23 PM PST 23 |
Dec 24 12:36:42 PM PST 23 |
299952725 ps |
| T626 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.201802215 |
|
|
Dec 24 12:36:22 PM PST 23 |
Dec 24 12:40:42 PM PST 23 |
6972392724 ps |
| T627 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.156406539 |
|
|
Dec 24 12:35:20 PM PST 23 |
Dec 24 12:35:54 PM PST 23 |
4090753606 ps |
| T628 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.955296847 |
|
|
Dec 24 12:35:13 PM PST 23 |
Dec 24 12:40:22 PM PST 23 |
3183073198 ps |
| T629 |
/workspace/coverage/default/8.sram_ctrl_alert_test.42448929 |
|
|
Dec 24 12:35:54 PM PST 23 |
Dec 24 12:36:15 PM PST 23 |
22947547 ps |
| T630 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.1799150973 |
|
|
Dec 24 12:36:27 PM PST 23 |
Dec 24 12:36:51 PM PST 23 |
76462884 ps |
| T631 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.2801334238 |
|
|
Dec 24 12:35:16 PM PST 23 |
Dec 24 12:49:24 PM PST 23 |
3309984846 ps |
| T632 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3200849572 |
|
|
Dec 24 12:37:07 PM PST 23 |
Dec 24 01:08:08 PM PST 23 |
238276151 ps |
| T633 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.1705247730 |
|
|
Dec 24 12:35:16 PM PST 23 |
Dec 24 12:39:07 PM PST 23 |
1729482297 ps |
| T634 |
/workspace/coverage/default/45.sram_ctrl_regwen.3816793057 |
|
|
Dec 24 12:37:15 PM PST 23 |
Dec 24 12:49:55 PM PST 23 |
10423475779 ps |
| T635 |
/workspace/coverage/default/29.sram_ctrl_smoke.525048221 |
|
|
Dec 24 12:36:26 PM PST 23 |
Dec 24 12:36:53 PM PST 23 |
554806982 ps |
| T636 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.746837618 |
|
|
Dec 24 12:36:34 PM PST 23 |
Dec 24 12:36:58 PM PST 23 |
647077697 ps |
| T637 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.3854029908 |
|
|
Dec 24 12:35:07 PM PST 23 |
Dec 24 12:36:15 PM PST 23 |
336247916 ps |
| T638 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.891629247 |
|
|
Dec 24 12:37:49 PM PST 23 |
Dec 24 12:54:50 PM PST 23 |
350498860 ps |
| T639 |
/workspace/coverage/default/35.sram_ctrl_stress_all.1218909597 |
|
|
Dec 24 12:36:16 PM PST 23 |
Dec 24 01:18:28 PM PST 23 |
29857171209 ps |
| T640 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.2285742284 |
|
|
Dec 24 12:36:37 PM PST 23 |
Dec 24 12:37:49 PM PST 23 |
1024801798 ps |
| T641 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3477319898 |
|
|
Dec 24 12:35:34 PM PST 23 |
Dec 24 12:55:30 PM PST 23 |
44018288215 ps |
| T642 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.2295148510 |
|
|
Dec 24 12:36:41 PM PST 23 |
Dec 24 12:37:10 PM PST 23 |
6145467236 ps |
| T643 |
/workspace/coverage/default/28.sram_ctrl_alert_test.671214786 |
|
|
Dec 24 12:36:31 PM PST 23 |
Dec 24 12:36:51 PM PST 23 |
58729903 ps |
| T644 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.3005100459 |
|
|
Dec 24 12:36:02 PM PST 23 |
Dec 24 12:36:30 PM PST 23 |
311606190 ps |
| T645 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.2170606121 |
|
|
Dec 24 12:35:30 PM PST 23 |
Dec 24 12:49:28 PM PST 23 |
30125852889 ps |
| T646 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1673324758 |
|
|
Dec 24 12:36:13 PM PST 23 |
Dec 24 12:42:28 PM PST 23 |
55247744299 ps |
| T647 |
/workspace/coverage/default/49.sram_ctrl_partial_access.1778897769 |
|
|
Dec 24 12:37:30 PM PST 23 |
Dec 24 12:37:57 PM PST 23 |
327323252 ps |
| T648 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.929972173 |
|
|
Dec 24 12:36:27 PM PST 23 |
Dec 24 12:36:49 PM PST 23 |
96118964 ps |
| T649 |
/workspace/coverage/default/17.sram_ctrl_stress_all.3077961231 |
|
|
Dec 24 12:36:04 PM PST 23 |
Dec 24 12:51:17 PM PST 23 |
53013310750 ps |
| T650 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.1367849977 |
|
|
Dec 24 12:36:52 PM PST 23 |
Dec 24 12:37:16 PM PST 23 |
521019761 ps |
| T651 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.1473732177 |
|
|
Dec 24 12:35:19 PM PST 23 |
Dec 24 12:35:51 PM PST 23 |
281225840 ps |
| T652 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.188522669 |
|
|
Dec 24 12:36:38 PM PST 23 |
Dec 24 12:37:00 PM PST 23 |
1132933332 ps |
| T653 |
/workspace/coverage/default/36.sram_ctrl_executable.4229441275 |
|
|
Dec 24 12:36:57 PM PST 23 |
Dec 24 12:40:20 PM PST 23 |
1088583970 ps |
| T654 |
/workspace/coverage/default/46.sram_ctrl_partial_access.478336688 |
|
|
Dec 24 12:37:40 PM PST 23 |
Dec 24 12:37:51 PM PST 23 |
169694861 ps |
| T655 |
/workspace/coverage/default/20.sram_ctrl_alert_test.3623150198 |
|
|
Dec 24 12:36:15 PM PST 23 |
Dec 24 12:36:33 PM PST 23 |
22242249 ps |
| T656 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.1212513787 |
|
|
Dec 24 12:36:20 PM PST 23 |
Dec 24 12:36:37 PM PST 23 |
31317702 ps |
| T657 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3461369303 |
|
|
Dec 24 12:36:35 PM PST 23 |
Dec 24 01:12:07 PM PST 23 |
1516140714 ps |
| T658 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.1324892622 |
|
|
Dec 24 12:36:02 PM PST 23 |
Dec 24 12:36:27 PM PST 23 |
406012731 ps |
| T659 |
/workspace/coverage/default/16.sram_ctrl_partial_access.2227459515 |
|
|
Dec 24 12:35:59 PM PST 23 |
Dec 24 12:36:34 PM PST 23 |
1198568054 ps |
| T660 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.2588738072 |
|
|
Dec 24 12:35:29 PM PST 23 |
Dec 24 12:37:24 PM PST 23 |
551972958 ps |
| T661 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.3813219854 |
|
|
Dec 24 12:36:27 PM PST 23 |
Dec 24 12:40:12 PM PST 23 |
8330995459 ps |
| T662 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.1320889589 |
|
|
Dec 24 12:35:44 PM PST 23 |
Dec 24 12:36:14 PM PST 23 |
1015964116 ps |
| T663 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.2181104129 |
|
|
Dec 24 12:37:02 PM PST 23 |
Dec 24 12:37:21 PM PST 23 |
41094886 ps |
| T664 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.599921967 |
|
|
Dec 24 12:37:04 PM PST 23 |
Dec 24 01:14:09 PM PST 23 |
1517791191 ps |
| T665 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.1342153967 |
|
|
Dec 24 12:37:06 PM PST 23 |
Dec 24 12:55:04 PM PST 23 |
17483171932 ps |
| T666 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.4143789005 |
|
|
Dec 24 12:37:35 PM PST 23 |
Dec 24 12:47:51 PM PST 23 |
38115650258 ps |
| T667 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.382401086 |
|
|
Dec 24 12:37:12 PM PST 23 |
Dec 24 12:37:37 PM PST 23 |
75324029 ps |
| T668 |
/workspace/coverage/default/29.sram_ctrl_partial_access.2944669548 |
|
|
Dec 24 12:36:32 PM PST 23 |
Dec 24 12:38:03 PM PST 23 |
2124919132 ps |
| T669 |
/workspace/coverage/default/38.sram_ctrl_executable.2853795824 |
|
|
Dec 24 12:36:58 PM PST 23 |
Dec 24 01:03:52 PM PST 23 |
84627306223 ps |
| T670 |
/workspace/coverage/default/41.sram_ctrl_smoke.903447016 |
|
|
Dec 24 12:37:07 PM PST 23 |
Dec 24 12:37:25 PM PST 23 |
772364996 ps |
| T671 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.4240637458 |
|
|
Dec 24 12:36:06 PM PST 23 |
Dec 24 12:36:31 PM PST 23 |
56533505 ps |
| T672 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.294350114 |
|
|
Dec 24 12:36:08 PM PST 23 |
Dec 24 12:36:32 PM PST 23 |
446978969 ps |
| T673 |
/workspace/coverage/default/35.sram_ctrl_bijection.151620216 |
|
|
Dec 24 12:36:43 PM PST 23 |
Dec 24 12:37:55 PM PST 23 |
2687371190 ps |
| T674 |
/workspace/coverage/default/44.sram_ctrl_regwen.662474240 |
|
|
Dec 24 12:37:20 PM PST 23 |
Dec 24 12:41:51 PM PST 23 |
35456017159 ps |
| T675 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.4026778748 |
|
|
Dec 24 12:36:01 PM PST 23 |
Dec 24 12:36:29 PM PST 23 |
137969060 ps |
| T676 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.2395225434 |
|
|
Dec 24 12:35:42 PM PST 23 |
Dec 24 12:36:08 PM PST 23 |
71488932 ps |
| T677 |
/workspace/coverage/default/25.sram_ctrl_smoke.4099052502 |
|
|
Dec 24 12:36:18 PM PST 23 |
Dec 24 12:36:41 PM PST 23 |
1016789825 ps |
| T678 |
/workspace/coverage/default/19.sram_ctrl_stress_all.3230507402 |
|
|
Dec 24 12:36:11 PM PST 23 |
Dec 24 01:02:04 PM PST 23 |
330175216264 ps |
| T679 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.3284579715 |
|
|
Dec 24 12:37:01 PM PST 23 |
Dec 24 12:39:30 PM PST 23 |
131100214 ps |
| T680 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.165623783 |
|
|
Dec 24 12:36:20 PM PST 23 |
Dec 24 01:58:42 PM PST 23 |
3288072794 ps |
| T681 |
/workspace/coverage/default/34.sram_ctrl_partial_access.2427316381 |
|
|
Dec 24 12:36:31 PM PST 23 |
Dec 24 12:37:05 PM PST 23 |
2830590922 ps |
| T682 |
/workspace/coverage/default/1.sram_ctrl_smoke.2415025888 |
|
|
Dec 24 12:35:26 PM PST 23 |
Dec 24 12:36:39 PM PST 23 |
209975769 ps |
| T683 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1296052297 |
|
|
Dec 24 12:36:52 PM PST 23 |
Dec 24 12:38:33 PM PST 23 |
505196127 ps |
| T684 |
/workspace/coverage/default/19.sram_ctrl_executable.3147144526 |
|
|
Dec 24 12:36:05 PM PST 23 |
Dec 24 01:00:04 PM PST 23 |
161589731041 ps |
| T685 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.893333519 |
|
|
Dec 24 12:37:17 PM PST 23 |
Dec 24 12:50:56 PM PST 23 |
1748516604 ps |
| T686 |
/workspace/coverage/default/43.sram_ctrl_executable.1300549825 |
|
|
Dec 24 12:37:00 PM PST 23 |
Dec 24 12:43:47 PM PST 23 |
1909702251 ps |
| T687 |
/workspace/coverage/default/5.sram_ctrl_bijection.390643054 |
|
|
Dec 24 12:35:15 PM PST 23 |
Dec 24 12:36:12 PM PST 23 |
16549689369 ps |
| T688 |
/workspace/coverage/default/37.sram_ctrl_alert_test.562417875 |
|
|
Dec 24 12:36:50 PM PST 23 |
Dec 24 12:37:06 PM PST 23 |
17042513 ps |
| T689 |
/workspace/coverage/default/30.sram_ctrl_alert_test.688579022 |
|
|
Dec 24 12:36:16 PM PST 23 |
Dec 24 12:36:34 PM PST 23 |
20386799 ps |
| T690 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.1981438634 |
|
|
Dec 24 12:35:19 PM PST 23 |
Dec 24 12:48:09 PM PST 23 |
8127408691 ps |
| T691 |
/workspace/coverage/default/48.sram_ctrl_alert_test.3453382873 |
|
|
Dec 24 12:37:30 PM PST 23 |
Dec 24 12:37:40 PM PST 23 |
14443787 ps |
| T692 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.14032359 |
|
|
Dec 24 12:37:09 PM PST 23 |
Dec 24 12:37:33 PM PST 23 |
1835392731 ps |
| T693 |
/workspace/coverage/default/14.sram_ctrl_smoke.3060084752 |
|
|
Dec 24 12:35:13 PM PST 23 |
Dec 24 12:35:48 PM PST 23 |
607722672 ps |
| T694 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.3217457581 |
|
|
Dec 24 12:35:19 PM PST 23 |
Dec 24 12:37:50 PM PST 23 |
134309114 ps |
| T695 |
/workspace/coverage/default/41.sram_ctrl_alert_test.3439631609 |
|
|
Dec 24 12:36:59 PM PST 23 |
Dec 24 12:37:15 PM PST 23 |
38478526 ps |
| T696 |
/workspace/coverage/default/10.sram_ctrl_partial_access.3645433169 |
|
|
Dec 24 12:35:33 PM PST 23 |
Dec 24 12:36:05 PM PST 23 |
1021747485 ps |
| T697 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.2159222508 |
|
|
Dec 24 12:35:21 PM PST 23 |
Dec 24 12:35:50 PM PST 23 |
82639839 ps |
| T698 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.2678328478 |
|
|
Dec 24 12:35:55 PM PST 23 |
Dec 24 12:39:41 PM PST 23 |
10590159743 ps |
| T699 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.458690978 |
|
|
Dec 24 12:35:28 PM PST 23 |
Dec 24 02:05:09 PM PST 23 |
2650940837 ps |
| T700 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.2674838588 |
|
|
Dec 24 12:35:45 PM PST 23 |
Dec 24 12:37:21 PM PST 23 |
764608079 ps |
| T701 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.582540604 |
|
|
Dec 24 12:36:04 PM PST 23 |
Dec 24 12:38:46 PM PST 23 |
310394530 ps |
| T702 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2597427873 |
|
|
Dec 24 12:37:04 PM PST 23 |
Dec 24 12:48:42 PM PST 23 |
648730175 ps |
| T703 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.509274711 |
|
|
Dec 24 12:35:33 PM PST 23 |
Dec 24 12:36:07 PM PST 23 |
446679536 ps |
| T704 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.3997080576 |
|
|
Dec 24 12:37:13 PM PST 23 |
Dec 24 12:55:51 PM PST 23 |
4213397712 ps |
| T705 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.350314683 |
|
|
Dec 24 12:36:32 PM PST 23 |
Dec 24 12:38:20 PM PST 23 |
146705515 ps |
| T706 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2901378493 |
|
|
Dec 24 12:36:03 PM PST 23 |
Dec 24 12:43:13 PM PST 23 |
31428192470 ps |
| T707 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1254257241 |
|
|
Dec 24 12:35:22 PM PST 23 |
Dec 24 02:02:12 PM PST 23 |
5561744025 ps |
| T708 |
/workspace/coverage/default/39.sram_ctrl_partial_access.1302834433 |
|
|
Dec 24 12:36:58 PM PST 23 |
Dec 24 12:37:28 PM PST 23 |
272766208 ps |
| T709 |
/workspace/coverage/default/21.sram_ctrl_bijection.3414437108 |
|
|
Dec 24 12:36:02 PM PST 23 |
Dec 24 12:37:36 PM PST 23 |
9784108627 ps |
| T710 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.302363013 |
|
|
Dec 24 12:34:59 PM PST 23 |
Dec 24 12:51:58 PM PST 23 |
13613633190 ps |
| T711 |
/workspace/coverage/default/0.sram_ctrl_partial_access.3285113462 |
|
|
Dec 24 12:35:13 PM PST 23 |
Dec 24 12:35:46 PM PST 23 |
158937823 ps |
| T712 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.971413760 |
|
|
Dec 24 12:36:43 PM PST 23 |
Dec 24 12:40:56 PM PST 23 |
9764311969 ps |
| T713 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.3263075635 |
|
|
Dec 24 12:35:35 PM PST 23 |
Dec 24 12:36:03 PM PST 23 |
256245135 ps |
| T714 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.4026662740 |
|
|
Dec 24 12:37:16 PM PST 23 |
Dec 24 12:37:36 PM PST 23 |
1145053930 ps |
| T715 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.1785058996 |
|
|
Dec 24 12:35:56 PM PST 23 |
Dec 24 12:36:20 PM PST 23 |
89539468 ps |
| T716 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.2475240788 |
|
|
Dec 24 12:36:05 PM PST 23 |
Dec 24 12:36:27 PM PST 23 |
120524247 ps |
| T717 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.1273948160 |
|
|
Dec 24 12:36:08 PM PST 23 |
Dec 24 01:01:26 PM PST 23 |
4089661948 ps |
| T718 |
/workspace/coverage/default/9.sram_ctrl_alert_test.1770633948 |
|
|
Dec 24 12:35:32 PM PST 23 |
Dec 24 12:35:58 PM PST 23 |
13235823 ps |
| T719 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.1646512704 |
|
|
Dec 24 12:36:06 PM PST 23 |
Dec 24 12:36:34 PM PST 23 |
276711708 ps |
| T720 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.2493793366 |
|
|
Dec 24 12:35:36 PM PST 23 |
Dec 24 12:40:25 PM PST 23 |
2823670411 ps |
| T721 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.2316359666 |
|
|
Dec 24 12:37:18 PM PST 23 |
Dec 24 12:37:38 PM PST 23 |
548850906 ps |
| T722 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.148747948 |
|
|
Dec 24 12:36:20 PM PST 23 |
Dec 24 12:36:37 PM PST 23 |
28375516 ps |
| T723 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.3424231298 |
|
|
Dec 24 12:36:42 PM PST 23 |
Dec 24 12:37:02 PM PST 23 |
450789598 ps |
| T724 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.743169031 |
|
|
Dec 24 12:37:15 PM PST 23 |
Dec 24 12:39:43 PM PST 23 |
2407104861 ps |
| T725 |
/workspace/coverage/default/36.sram_ctrl_stress_all.1913003967 |
|
|
Dec 24 12:37:05 PM PST 23 |
Dec 24 01:31:01 PM PST 23 |
393664291302 ps |
| T726 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.2392403297 |
|
|
Dec 24 12:35:57 PM PST 23 |
Dec 24 12:36:19 PM PST 23 |
145700839 ps |
| T727 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3439263511 |
|
|
Dec 24 12:36:00 PM PST 23 |
Dec 24 12:40:01 PM PST 23 |
18714708152 ps |
| T728 |
/workspace/coverage/default/29.sram_ctrl_regwen.938854161 |
|
|
Dec 24 12:36:14 PM PST 23 |
Dec 24 12:46:26 PM PST 23 |
10182750555 ps |
| T729 |
/workspace/coverage/default/42.sram_ctrl_partial_access.2658325080 |
|
|
Dec 24 12:36:54 PM PST 23 |
Dec 24 12:38:43 PM PST 23 |
1228662483 ps |
| T730 |
/workspace/coverage/default/11.sram_ctrl_smoke.1001791021 |
|
|
Dec 24 12:35:23 PM PST 23 |
Dec 24 12:36:02 PM PST 23 |
1744708992 ps |
| T731 |
/workspace/coverage/default/45.sram_ctrl_alert_test.1458547322 |
|
|
Dec 24 12:37:36 PM PST 23 |
Dec 24 12:37:45 PM PST 23 |
13499842 ps |
| T732 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.3620400112 |
|
|
Dec 24 12:36:26 PM PST 23 |
Dec 24 12:36:46 PM PST 23 |
34390522 ps |
| T733 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.87892711 |
|
|
Dec 24 12:36:04 PM PST 23 |
Dec 24 12:36:28 PM PST 23 |
176929032 ps |
| T734 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.4032006238 |
|
|
Dec 24 12:35:39 PM PST 23 |
Dec 24 12:42:55 PM PST 23 |
32092003822 ps |
| T735 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.782796944 |
|
|
Dec 24 12:35:50 PM PST 23 |
Dec 24 12:55:10 PM PST 23 |
24311174114 ps |
| T736 |
/workspace/coverage/default/48.sram_ctrl_partial_access.2998445721 |
|
|
Dec 24 12:37:34 PM PST 23 |
Dec 24 12:38:03 PM PST 23 |
456858196 ps |
| T737 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.42662712 |
|
|
Dec 24 12:35:36 PM PST 23 |
Dec 24 12:36:09 PM PST 23 |
139248511 ps |
| T738 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.1589438127 |
|
|
Dec 24 12:36:18 PM PST 23 |
Dec 24 12:41:40 PM PST 23 |
3112515699 ps |
| T739 |
/workspace/coverage/default/34.sram_ctrl_stress_all.1565265678 |
|
|
Dec 24 12:36:20 PM PST 23 |
Dec 24 12:51:21 PM PST 23 |
35110968150 ps |
| T740 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.411313592 |
|
|
Dec 24 12:35:57 PM PST 23 |
Dec 24 12:36:19 PM PST 23 |
37007497 ps |
| T741 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1981729268 |
|
|
Dec 24 12:36:51 PM PST 23 |
Dec 24 12:41:56 PM PST 23 |
11444550414 ps |
| T742 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1205892212 |
|
|
Dec 24 12:37:33 PM PST 23 |
Dec 24 12:37:46 PM PST 23 |
265173030 ps |
| T743 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.232583596 |
|
|
Dec 24 12:36:10 PM PST 23 |
Dec 24 12:51:13 PM PST 23 |
1456696530 ps |
| T744 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3574531532 |
|
|
Dec 24 12:37:19 PM PST 23 |
Dec 24 12:41:38 PM PST 23 |
9980592341 ps |
| T745 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2145135561 |
|
|
Dec 24 12:35:01 PM PST 23 |
Dec 24 01:09:50 PM PST 23 |
519226952 ps |
| T746 |
/workspace/coverage/default/27.sram_ctrl_smoke.537455378 |
|
|
Dec 24 12:36:27 PM PST 23 |
Dec 24 12:36:50 PM PST 23 |
123392717 ps |
| T747 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3791897327 |
|
|
Dec 24 12:36:18 PM PST 23 |
Dec 24 01:42:39 PM PST 23 |
2368748114 ps |
| T748 |
/workspace/coverage/default/30.sram_ctrl_bijection.851347073 |
|
|
Dec 24 12:36:31 PM PST 23 |
Dec 24 12:37:48 PM PST 23 |
13171107851 ps |
| T749 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.228326119 |
|
|
Dec 24 12:35:23 PM PST 23 |
Dec 24 12:40:36 PM PST 23 |
4177700216 ps |
| T750 |
/workspace/coverage/default/36.sram_ctrl_regwen.3591028304 |
|
|
Dec 24 12:36:50 PM PST 23 |
Dec 24 12:46:13 PM PST 23 |
12677886058 ps |
| T751 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.2405284270 |
|
|
Dec 24 12:35:23 PM PST 23 |
Dec 24 12:35:58 PM PST 23 |
136939624 ps |
| T752 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.628024584 |
|
|
Dec 24 12:37:23 PM PST 23 |
Dec 24 12:50:04 PM PST 23 |
4122290731 ps |