SRAM_CTRL/RET Simulation Results

Sunday December 24 2023 20:02:26 UTC

GitHub Revision: `671f2b57e2`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 96716765175854174075659971574604807242747408006700796360560480210023744343645

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.901m	999.924us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.760s	44.635us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.680s	16.734us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.000s	160.428us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.750s	26.410us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.320s	112.931us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.680s	16.734us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	26.410us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	11.090s	2.621ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.510s	691.612us	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	30.473m	20.707ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	8.030m	4.980ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.577m	45.159ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	28.683m	4.166ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	35.260s	1.083ms	45	50	90.00
V2	executable	sram_ctrl_executable	37.530m	18.300ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.630m	2.605ms	49	50	98.00
		sram_ctrl_partial_access_b2b	10.457m	405.543ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.555m	475.172us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.671m	588.971us	50	50	100.00
V2	regwen	sram_ctrl_regwen	33.280m	31.991ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.550s	71.489us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.830h	208.606ms	46	50	92.00
V2	alert_test	sram_ctrl_alert_test	0.690s	161.151us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.680s	249.538us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.680s	249.538us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.760s	44.635us	5	5	100.00
		sram_ctrl_csr_rw	0.680s	16.734us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	26.410us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.780s	77.854us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.760s	44.635us	5	5	100.00
		sram_ctrl_csr_rw	0.680s	16.734us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	26.410us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.780s	77.854us	20	20	100.00
V2		TOTAL			729	740	98.51
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	12.770s	561.404us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.580s	2.537ms	5	5	100.00
		sram_ctrl_tl_intg_err	2.420s	1.947ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.580s	2.537ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.420s	1.947ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	33.280m	31.991ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.680s	16.734us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	37.530m	18.300ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	37.530m	18.300ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	37.530m	18.300ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	35.260s	1.083ms	45	50	90.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	12.770s	561.404us	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.901m	999.924us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.901m	999.924us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	37.530m	18.300ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.580s	2.537ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	35.260s	1.083ms	45	50	90.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.580s	2.537ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.580s	2.537ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.901m	999.924us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.580s	2.537ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.666h	7.689ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1029	1040	98.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	12	75.00
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.65	100.00	98.13	100.00	100.00	99.71	99.70	100.00

Failure Buckets

UVM_ERROR (sram_ctrl_scoreboard.sv:369) [scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= * (* [*] vs * [*]) has 9 failures:

Test sram_ctrl_lc_escalation has 5 failures.

1.sram_ctrl_lc_escalation.5133642445224435334058151173143302688508324901408684096831277979368455579949
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @  32765184 ps: (sram_ctrl_scoreboard.sv:369) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @  32765184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.sram_ctrl_lc_escalation.768660941288932937156173749883057246794329237600710713743014431722310034696
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 377567741 ps: (sram_ctrl_scoreboard.sv:369) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 377567741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test sram_ctrl_stress_all has 4 failures.

4.sram_ctrl_stress_all.47561244880850298425673708308742781718435796153030483029926467753514653490874
Line 439, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 32153331639 ps: (sram_ctrl_scoreboard.sv:369) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 32153331639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.sram_ctrl_stress_all.77820076646154243693494247352378004520261513238929892041367635768205995380485
Line 471, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 7970540721 ps: (sram_ctrl_scoreboard.sv:369) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 7970540721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 10.sram_ctrl_multiple_keys.57468098603432876930874403590417086811989548459205742137387290370731833637073
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 10397355264 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x56bc3c97
  UVM_INFO @ 10397355264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_partial_access has 1 failures.
  - 33.sram_ctrl_partial_access.71035626163962673911686918767832356252994228290046800449520245151469413208389
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/33.sram_ctrl_partial_access/latest/run.log
```
  UVM_FATAL @ 10291873681 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x22769e6
  UVM_INFO @ 10291873681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```