Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14388506	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

61112735

1

T1

596749

T2

759

T3

4532

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37634305	1			T1	324662		T2	1996		T3	2786
values[0x0]	17493736	1			T1	156988		T2	728		T3	1243
values[0x1]	20373200	1			T1	167514		T2	1357		T3	1504

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7169951	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

68331290

1

T1

622994

T2

2414

T3

5040

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	257024	1			T2	14		T3	24		T4	521
valid_sources[0x01]	302740	1			T2	16		T3	19		T4	553
valid_sources[0x02]	288944	1			T1	4013		T2	20		T3	21
valid_sources[0x03]	274575	1			T1	10		T2	20		T3	23
valid_sources[0x04]	332346	1			T2	14		T3	21		T4	595
valid_sources[0x05]	310814	1			T2	21		T3	25		T4	604
valid_sources[0x06]	288706	1			T2	13		T3	26		T4	556
valid_sources[0x07]	303104	1			T1	35		T2	13		T3	20
valid_sources[0x08]	268927	1			T2	21		T3	26		T4	551
valid_sources[0x09]	255677	1			T2	21		T3	25		T4	598
valid_sources[0x0a]	280884	1			T2	20		T3	19		T4	583
valid_sources[0x0b]	321365	1			T2	12		T3	11		T4	594
valid_sources[0x0c]	304970	1			T2	12		T3	30		T4	521
valid_sources[0x0d]	288162	1			T2	24		T3	31		T4	609
valid_sources[0x0e]	297844	1			T1	42		T2	15		T3	15
valid_sources[0x0f]	293333	1			T1	2482		T2	23		T3	20
valid_sources[0x10]	289080	1			T2	9		T3	30		T4	627
valid_sources[0x11]	266027	1			T2	13		T3	33		T4	643
valid_sources[0x12]	254906	1			T2	15		T3	30		T4	575
valid_sources[0x13]	317815	1			T1	49		T2	18		T3	28
valid_sources[0x14]	308213	1			T2	18		T3	15		T4	605
valid_sources[0x15]	324678	1			T1	22974		T2	15		T3	20
valid_sources[0x16]	273283	1			T1	4539		T2	25		T3	21
valid_sources[0x17]	301633	1			T2	9		T3	28		T4	604
valid_sources[0x18]	329539	1			T2	20		T3	16		T4	537
valid_sources[0x19]	304752	1			T2	8		T3	19		T4	596
valid_sources[0x1a]	290917	1			T2	21		T3	17		T4	584
valid_sources[0x1b]	270071	1			T2	18		T3	19		T4	579
valid_sources[0x1c]	301517	1			T2	10		T3	25		T4	580
valid_sources[0x1d]	306363	1			T2	14		T3	14		T4	596
valid_sources[0x1e]	328455	1			T2	14		T3	21		T4	553
valid_sources[0x1f]	322908	1			T2	8		T3	16		T4	588
valid_sources[0x20]	259342	1			T2	24		T3	17		T4	581
valid_sources[0x21]	318871	1			T2	11		T3	16		T4	631
valid_sources[0x22]	280375	1			T2	9		T3	23		T4	597
valid_sources[0x23]	313492	1			T2	14		T3	22		T4	577
valid_sources[0x24]	371615	1			T1	29		T2	21		T3	17
valid_sources[0x25]	298562	1			T2	16		T3	16		T4	648
valid_sources[0x26]	322563	1			T1	3828		T2	23		T3	27
valid_sources[0x27]	313051	1			T1	121		T2	19		T3	18
valid_sources[0x28]	296825	1			T2	23		T3	17		T4	611
valid_sources[0x29]	441264	1			T1	164587		T2	19		T3	19
valid_sources[0x2a]	276720	1			T1	102		T2	12		T3	20
valid_sources[0x2b]	294031	1			T1	33		T2	9		T3	17
valid_sources[0x2c]	340633	1			T2	5		T3	14		T4	625
valid_sources[0x2d]	349429	1			T1	76		T2	14		T3	19
valid_sources[0x2e]	295702	1			T2	14		T3	22		T4	590
valid_sources[0x2f]	270381	1			T1	7761		T2	17		T3	22
valid_sources[0x30]	272731	1			T2	23		T3	17		T4	553
valid_sources[0x31]	265844	1			T2	13		T3	21		T4	651
valid_sources[0x32]	293820	1			T1	104		T2	13		T3	20
valid_sources[0x33]	275411	1			T2	19		T3	25		T4	586
valid_sources[0x34]	323372	1			T1	73		T2	13		T3	26
valid_sources[0x35]	276798	1			T2	22		T3	17		T4	584
valid_sources[0x36]	283984	1			T2	18		T3	22		T4	589
valid_sources[0x37]	276876	1			T2	12		T3	16		T4	621
valid_sources[0x38]	289534	1			T2	25		T3	25		T4	634
valid_sources[0x39]	305346	1			T2	18		T3	22		T4	602
valid_sources[0x3a]	272808	1			T1	9		T2	9		T3	13
valid_sources[0x3b]	285586	1			T2	24		T3	27		T4	647
valid_sources[0x3c]	287696	1			T1	7551		T2	25		T3	16
valid_sources[0x3d]	347397	1			T2	18		T3	22		T4	620
valid_sources[0x3e]	284744	1			T2	16		T3	23		T4	620
valid_sources[0x3f]	278414	1			T1	13		T2	18		T3	24
valid_sources[0x40]	266703	1			T2	19		T3	27		T4	592
valid_sources[0x41]	275234	1			T1	76		T2	24		T3	29
valid_sources[0x42]	320499	1			T2	4		T3	23		T4	596
valid_sources[0x43]	348567	1			T1	8869		T2	21		T3	29
valid_sources[0x44]	322885	1			T2	14		T3	23		T4	607
valid_sources[0x45]	272599	1			T2	10		T3	17		T4	563
valid_sources[0x46]	277442	1			T2	12		T3	30		T4	590
valid_sources[0x47]	313980	1			T2	10		T3	24		T4	609
valid_sources[0x48]	283947	1			T2	20		T3	26		T4	580
valid_sources[0x49]	289923	1			T2	21		T3	17		T4	582
valid_sources[0x4a]	298787	1			T1	13979		T2	17		T3	24
valid_sources[0x4b]	273929	1			T2	10		T3	18		T4	547
valid_sources[0x4c]	278351	1			T1	3495		T2	5		T3	20
valid_sources[0x4d]	295996	1			T1	2611		T2	16		T3	20
valid_sources[0x4e]	326654	1			T2	18		T3	27		T4	625
valid_sources[0x4f]	255504	1			T2	18		T3	17		T4	610
valid_sources[0x50]	307434	1			T1	123		T2	21		T3	19
valid_sources[0x51]	275052	1			T2	24		T3	19		T4	607
valid_sources[0x52]	302757	1			T2	20		T3	19		T4	587
valid_sources[0x53]	278600	1			T2	20		T3	16		T4	576
valid_sources[0x54]	301814	1			T2	20		T3	27		T4	577
valid_sources[0x55]	301991	1			T2	20		T3	20		T4	632
valid_sources[0x56]	283645	1			T2	10		T3	24		T4	577
valid_sources[0x57]	318938	1			T2	13		T3	15		T4	602
valid_sources[0x58]	351700	1			T2	14		T3	24		T4	615
valid_sources[0x59]	273758	1			T2	18		T3	26		T4	606
valid_sources[0x5a]	277191	1			T2	13		T3	21		T4	597
valid_sources[0x5b]	268320	1			T1	26		T2	6		T3	20
valid_sources[0x5c]	265365	1			T2	19		T3	19		T4	564
valid_sources[0x5d]	278828	1			T2	19		T3	22		T4	598
valid_sources[0x5e]	267859	1			T1	950		T2	23		T3	23
valid_sources[0x5f]	272083	1			T2	7		T3	19		T4	616
valid_sources[0x60]	322974	1			T1	12579		T2	19		T3	25
valid_sources[0x61]	352455	1			T1	23		T2	20		T3	15
valid_sources[0x62]	305946	1			T2	16		T3	17		T4	611
valid_sources[0x63]	264927	1			T1	116		T2	22		T3	24
valid_sources[0x64]	362707	1			T2	16		T3	24		T4	576
valid_sources[0x65]	279115	1			T2	14		T3	16		T4	563
valid_sources[0x66]	291806	1			T1	56		T2	19		T3	22
valid_sources[0x67]	308985	1			T2	22		T3	19		T4	612
valid_sources[0x68]	331088	1			T2	21		T3	27		T4	620
valid_sources[0x69]	351887	1			T2	22		T3	28		T4	577
valid_sources[0x6a]	259877	1			T2	9		T3	28		T4	633
valid_sources[0x6b]	316799	1			T1	42165		T2	17		T3	22
valid_sources[0x6c]	316908	1			T1	8		T2	23		T3	27
valid_sources[0x6d]	310128	1			T2	21		T3	30		T4	621
valid_sources[0x6e]	304107	1			T2	15		T3	19		T4	556
valid_sources[0x6f]	314892	1			T1	19		T2	6		T3	23
valid_sources[0x70]	348621	1			T2	13		T3	17		T4	608
valid_sources[0x71]	274803	1			T2	15		T3	28		T4	576
valid_sources[0x72]	260991	1			T2	14		T3	22		T4	614
valid_sources[0x73]	291647	1			T2	17		T3	28		T4	518
valid_sources[0x74]	342873	1			T1	200		T2	6		T3	15
valid_sources[0x75]	280426	1			T2	17		T3	22		T4	589
valid_sources[0x76]	284401	1			T2	8		T3	23		T4	611
valid_sources[0x77]	360919	1			T1	73554		T2	21		T3	23
valid_sources[0x78]	252272	1			T2	17		T3	19		T4	582
valid_sources[0x79]	283437	1			T2	18		T3	13		T4	608
valid_sources[0x7a]	288562	1			T1	56		T2	14		T3	17
valid_sources[0x7b]	282088	1			T2	21		T3	24		T4	647
valid_sources[0x7c]	295359	1			T2	6		T3	19		T4	593
valid_sources[0x7d]	349627	1			T2	14		T3	19		T4	604
valid_sources[0x7e]	315675	1			T2	27		T3	29		T4	539
valid_sources[0x7f]	278660	1			T2	14		T3	21		T4	581
valid_sources[0x80]	266788	1			T2	25		T3	23		T4	569

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30443046

1

T1

298333

T2

360

T3

2292

values[0x0]

all_enables

biggest_size

15334682

1

T1

149151

T2

200

T3

1103

values[0x1]

all_enables

biggest_size

15335007

1

T1

149265

T2

199

T3

1137

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2251455	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

140168

1

T1

40

T4

8

T5

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2268130	1			T1	10295		T2	519		T3	2153
values[0x0]	59951	1			T1	52		T3	1		T4	19
values[0x1]	63542	1			T1	60		T2	1		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1504470	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

887153

1

T1

3445

T2

182

T3

718

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8853	1			T1	40		T9	6		T14	5
valid_sources[0x01]	7662	1			T1	37		T5	1		T9	9
valid_sources[0x02]	7294	1			T1	39		T5	1		T8	1
valid_sources[0x03]	8927	1			T1	59		T8	2		T9	8
valid_sources[0x04]	7243	1			T1	56		T5	1		T8	5
valid_sources[0x05]	7893	1			T1	25		T8	2		T9	5
valid_sources[0x06]	10628	1			T1	20		T8	2		T9	6
valid_sources[0x07]	7617	1			T1	42		T5	3		T8	6
valid_sources[0x08]	9299	1			T1	56		T8	3		T9	3
valid_sources[0x09]	18652	1			T1	44		T5	2		T8	3
valid_sources[0x0a]	7427	1			T1	31		T8	7		T9	4
valid_sources[0x0b]	9481	1			T1	34		T5	2		T8	5
valid_sources[0x0c]	8276	1			T1	37		T5	2		T8	5
valid_sources[0x0d]	7827	1			T1	38		T8	4		T9	6
valid_sources[0x0e]	7237	1			T1	38		T5	3		T8	5
valid_sources[0x0f]	9269	1			T1	51		T8	2		T9	5
valid_sources[0x10]	7438	1			T1	34		T8	4		T9	2
valid_sources[0x11]	8270	1			T1	39		T8	3		T9	4
valid_sources[0x12]	8446	1			T1	41		T5	4		T8	7
valid_sources[0x13]	6861	1			T1	35		T5	1		T8	5
valid_sources[0x14]	7980	1			T1	53		T5	1		T8	6
valid_sources[0x15]	9246	1			T1	36		T8	6		T9	5
valid_sources[0x16]	7926	1			T1	54		T5	1		T8	1
valid_sources[0x17]	7783	1			T1	35		T5	1		T8	3
valid_sources[0x18]	7258	1			T1	37		T5	2		T8	4
valid_sources[0x19]	6902	1			T1	51		T5	2		T8	2
valid_sources[0x1a]	13628	1			T1	43		T8	1		T9	1
valid_sources[0x1b]	8005	1			T1	45		T5	1		T8	5
valid_sources[0x1c]	10721	1			T1	52		T8	5		T9	6
valid_sources[0x1d]	7212	1			T1	23		T9	7		T70	2
valid_sources[0x1e]	8022	1			T1	50		T8	3		T9	4
valid_sources[0x1f]	7115	1			T1	29		T5	4		T9	4
valid_sources[0x20]	8616	1			T1	46		T5	1		T8	2
valid_sources[0x21]	8204	1			T1	29		T5	1		T8	1
valid_sources[0x22]	13311	1			T1	39		T5	1		T8	2
valid_sources[0x23]	8005	1			T1	36		T8	1		T9	2
valid_sources[0x24]	15831	1			T1	32		T8	2		T9	5
valid_sources[0x25]	14650	1			T1	44		T8	3		T9	3
valid_sources[0x26]	7632	1			T1	37		T5	2		T8	7
valid_sources[0x27]	10073	1			T1	50		T8	4		T9	5
valid_sources[0x28]	7964	1			T1	40		T8	5		T9	4
valid_sources[0x29]	6863	1			T1	53		T8	1		T9	8
valid_sources[0x2a]	8551	1			T1	48		T5	5		T8	1
valid_sources[0x2b]	8159	1			T1	39		T8	3		T9	5
valid_sources[0x2c]	8232	1			T1	41		T5	1		T8	3
valid_sources[0x2d]	7050	1			T1	26		T5	1		T8	6
valid_sources[0x2e]	10566	1			T1	55		T8	2		T9	2
valid_sources[0x2f]	16843	1			T1	41		T8	3		T9	8
valid_sources[0x30]	9636	1			T1	38		T5	1		T8	1
valid_sources[0x31]	7563	1			T1	21		T5	3		T8	6
valid_sources[0x32]	8553	1			T1	39		T5	2		T8	4
valid_sources[0x33]	9156	1			T1	26		T5	1		T8	1
valid_sources[0x34]	8174	1			T1	41		T5	1		T8	1
valid_sources[0x35]	8166	1			T1	40		T8	1		T9	5
valid_sources[0x36]	7463	1			T1	44		T5	1		T8	6
valid_sources[0x37]	7107	1			T1	27		T5	1		T8	7
valid_sources[0x38]	7901	1			T1	55		T5	2		T8	3
valid_sources[0x39]	7229	1			T1	29		T5	4		T8	6
valid_sources[0x3a]	7501	1			T1	25		T5	2		T8	2
valid_sources[0x3b]	8668	1			T1	31		T5	2		T8	2
valid_sources[0x3c]	7873	1			T1	31		T5	2		T8	5
valid_sources[0x3d]	8719	1			T1	38		T5	1		T8	2
valid_sources[0x3e]	12795	1			T1	50		T5	2		T8	2
valid_sources[0x3f]	8216	1			T1	44		T9	3		T29	1
valid_sources[0x40]	7369	1			T1	38		T8	1		T9	4
valid_sources[0x41]	8641	1			T1	45		T5	1		T8	5
valid_sources[0x42]	9466	1			T1	26		T8	5		T9	7
valid_sources[0x43]	9796	1			T1	29		T8	7		T9	9
valid_sources[0x44]	8104	1			T1	58		T8	3		T9	7
valid_sources[0x45]	8331	1			T1	38		T5	2		T8	6
valid_sources[0x46]	10211	1			T1	31		T5	1		T8	3
valid_sources[0x47]	7208	1			T1	22		T8	3		T9	3
valid_sources[0x48]	7030	1			T1	45		T8	1		T9	5
valid_sources[0x49]	16098	1			T1	58		T5	1		T8	1
valid_sources[0x4a]	7534	1			T1	19		T5	2		T8	4
valid_sources[0x4b]	9429	1			T1	44		T8	1		T9	8
valid_sources[0x4c]	7402	1			T1	37		T5	1		T8	1
valid_sources[0x4d]	8213	1			T1	33		T5	1		T8	1
valid_sources[0x4e]	7615	1			T1	31		T5	1		T8	2
valid_sources[0x4f]	7387	1			T1	65		T8	5		T9	11
valid_sources[0x50]	7557	1			T1	49		T5	2		T8	2
valid_sources[0x51]	13430	1			T1	33		T8	1		T9	5
valid_sources[0x52]	11019	1			T1	30		T5	2		T8	2
valid_sources[0x53]	8576	1			T1	34		T5	1		T8	2
valid_sources[0x54]	18587	1			T1	40		T5	1		T8	2
valid_sources[0x55]	7459	1			T1	36		T8	4		T9	6
valid_sources[0x56]	8043	1			T1	49		T5	1		T8	6
valid_sources[0x57]	7995	1			T1	40		T5	3		T8	2
valid_sources[0x58]	15337	1			T1	29		T8	2		T9	6
valid_sources[0x59]	7187	1			T1	51		T8	9		T9	4
valid_sources[0x5a]	7516	1			T1	42		T5	2		T8	2
valid_sources[0x5b]	7696	1			T1	38		T2	520		T8	6
valid_sources[0x5c]	8945	1			T1	56		T5	1		T8	7
valid_sources[0x5d]	7781	1			T1	41		T5	1		T8	2
valid_sources[0x5e]	7318	1			T1	49		T5	1		T8	3
valid_sources[0x5f]	9067	1			T1	48		T5	1		T8	4
valid_sources[0x60]	7668	1			T1	60		T5	2		T8	1
valid_sources[0x61]	8377	1			T1	43		T5	1		T8	2
valid_sources[0x62]	8086	1			T1	28		T5	2		T8	2
valid_sources[0x63]	7346	1			T1	40		T8	1		T9	7
valid_sources[0x64]	7460	1			T1	30		T5	3		T8	9
valid_sources[0x65]	7547	1			T1	41		T5	1		T8	1
valid_sources[0x66]	40613	1			T1	47		T5	2		T8	3
valid_sources[0x67]	7993	1			T1	36		T5	3		T8	5
valid_sources[0x68]	7328	1			T1	46		T5	1		T8	10
valid_sources[0x69]	9875	1			T1	29		T5	1		T8	4
valid_sources[0x6a]	7442	1			T1	26		T5	3		T8	1
valid_sources[0x6b]	7441	1			T1	44		T8	5		T9	8
valid_sources[0x6c]	7132	1			T1	58		T5	3		T8	3
valid_sources[0x6d]	6756	1			T1	36		T8	1		T9	5
valid_sources[0x6e]	9040	1			T1	52		T5	1		T8	6
valid_sources[0x6f]	7095	1			T1	46		T5	1		T8	5
valid_sources[0x70]	7396	1			T1	36		T5	2		T8	6
valid_sources[0x71]	9256	1			T1	52		T5	2		T8	5
valid_sources[0x72]	8110	1			T1	36		T5	4		T8	5
valid_sources[0x73]	11067	1			T1	47		T8	1		T9	2
valid_sources[0x74]	8597	1			T1	45		T5	1		T8	6
valid_sources[0x75]	7286	1			T1	35		T5	1		T8	5
valid_sources[0x76]	8357	1			T1	38		T5	1		T8	3
valid_sources[0x77]	7199	1			T1	26		T8	5		T9	5
valid_sources[0x78]	8974	1			T1	25		T5	1		T8	3
valid_sources[0x79]	7774	1			T1	38		T8	3		T9	5
valid_sources[0x7a]	8239	1			T1	49		T8	3		T9	5
valid_sources[0x7b]	7138	1			T1	59		T8	3		T9	4
valid_sources[0x7c]	7553	1			T1	43		T8	3		T9	8
valid_sources[0x7d]	9271	1			T1	24		T5	1		T8	5
valid_sources[0x7e]	7476	1			T1	55		T5	1		T9	1
valid_sources[0x7f]	9373	1			T1	44		T9	5		T10	4
valid_sources[0x80]	16337	1			T1	41		T8	6		T9	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

37666

1

T1

16

T5

1

T6

26

values[0x0]

all_enables

biggest_size

52124

1

T1

17

T4

5

T5

4

values[0x1]

all_enables

biggest_size

50378

1

T1

7

T4

3

T9

1