Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14056464

1

T1

52110

T2

3322

T3

1001

full_word

55810806

1

T1

593942

T2

759

T3

4532

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	69866970	1			T1	646052		T2	4081		T3	5533
auto[TlIntgErrCmd]	92	1			T28	4		T44	6		T45	3
auto[TlIntgErrData]	103	1			T28	8		T44	2		T45	5
auto[TlIntgErrBoth]	105	1			T28	8		T44	2		T45	12

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31915047

1

T1

323093

T2

1996

T3

2786

auto[1]

37952223

1

T1

322959

T2

2085

T3

2747

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6706764	1			T1	26181		T2	1636		T3	494
auto[TlIntgErrNone]	partial	auto[1]	7349422	1			T1	25929		T2	1686		T3	507
auto[TlIntgErrNone]	full_word	auto[0]	25208144	1			T1	296912		T2	360		T3	2292
auto[TlIntgErrNone]	full_word	auto[1]	30602640	1			T1	297030		T2	399		T3	2240
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T28	1		T44	2		T47	1
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T28	3		T44	3		T45	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T122	1		T124	1		T119	2
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T44	1		T47	1		T118	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T28	1		T44	2		T45	1
auto[TlIntgErrData]	partial	auto[1]	50	1			T28	7		T45	3		T47	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T45	1		T120	1		T119	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T125	1		T126	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T28	3		T44	2		T45	7
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T28	5		T45	5		T47	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T121	1		T122	1		T119	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T59	1		T122	1		T126	1