Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	626349	1			T4	1567		T5	106		T6	4674
auto[1]	10222548	1			T1	6714		T2	11		T3	2783
auto[2]	525294	1			T4	1415		T5	66		T6	2988
auto[3]	10135213	1			T1	6606		T2	18		T3	2746

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14038097	1			T1	9262		T2	4		T3	3738
auto[1]	2065714	1			T1	1945		T2	4		T3	790
auto[2]	2055167	1			T1	1819		T2	4		T3	808
auto[3]	3350426	1			T1	294		T2	17		T3	193

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8643513

1

T1

13305

T2

29

T3

5523

auto[1]

12865891

1

T1

15

T3

6

T4

6

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	329495	1			T4	1286		T5	93		T6	3835
auto[0]	auto[0]	auto[1]	33494	1			T4	132		T5	4		T6	409
auto[0]	auto[0]	auto[2]	33354	1			T4	138		T5	7		T6	389
auto[0]	auto[0]	auto[3]	6778	1			T4	9		T5	2		T6	36
auto[0]	auto[1]	auto[0]	3216962	1			T1	4643		T2	1		T3	1915
auto[0]	auto[1]	auto[1]	346746	1			T1	1428		T2	1		T3	372
auto[0]	auto[1]	auto[2]	323898	1			T1	485		T2	2		T3	390
auto[0]	auto[1]	auto[3]	79612	1			T1	149		T2	7		T3	103
auto[0]	auto[2]	auto[0]	289826	1			T4	1158		T5	52		T6	2294
auto[0]	auto[2]	auto[1]	29682	1			T4	123		T5	7		T6	227
auto[0]	auto[2]	auto[2]	26222	1			T4	120		T5	7		T6	420
auto[0]	auto[2]	auto[3]	5156	1			T4	11		T6	43		T12	2
auto[0]	auto[3]	auto[0]	3175368	1			T1	4610		T2	3		T3	1819
auto[0]	auto[3]	auto[1]	321849	1			T1	516		T2	3		T3	418
auto[0]	auto[3]	auto[2]	341516	1			T1	1330		T2	2		T3	417
auto[0]	auto[3]	auto[3]	83555	1			T1	144		T2	10		T3	89
auto[1]	auto[0]	auto[0]	7676	1			T4	1		T6	4		T12	542
auto[1]	auto[0]	auto[1]	33378	1			T6	1		T12	2450		T57	6507
auto[1]	auto[0]	auto[2]	33403	1			T4	1		T12	2495		T57	6465
auto[1]	auto[0]	auto[3]	148771	1			T12	11047		T57	28676		T26	2
auto[1]	auto[1]	auto[0]	3503384	1			T1	5		T3	2		T4	1
auto[1]	auto[1]	auto[1]	650150	1			T1	1		T12	2498		T14	1
auto[1]	auto[1]	auto[2]	627302	1			T1	2		T12	426		T7	2
auto[1]	auto[1]	auto[3]	1474494	1			T1	1		T3	1		T12	11153
auto[1]	auto[2]	auto[0]	6691	1			T4	2		T6	4		T12	485
auto[1]	auto[2]	auto[1]	29593	1			T4	1		T12	2356		T78	1
auto[1]	auto[2]	auto[2]	25023	1			T12	1663		T78	1		T57	4308
auto[1]	auto[2]	auto[3]	113101	1			T12	7506		T57	19329		T92	1
auto[1]	auto[3]	auto[0]	3508695	1			T1	4		T3	2		T12	58
auto[1]	auto[3]	auto[1]	620822	1			T12	242		T15	2		T7	1
auto[1]	auto[3]	auto[2]	644449	1			T1	2		T3	1		T12	1687
auto[1]	auto[3]	auto[3]	1438959	1			T12	7734		T15	2		T79	9430