Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.85	100.00	97.56	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	343030953	167276	0	0
ctrl_regwen_rd_A	343030953	6018	0	0
exec_rd_A	343030953	5529	0	0
exec_regwen_rd_A	343030953	5890	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	343030953	167276	0	0
T25	75230	3694	0	0
T27	65522	2453	0	0
T28	19088	6	0	0
T43	0	584	0	0
T44	0	4	0	0
T45	0	6	0	0
T46	0	249	0	0
T47	0	1	0	0
T48	0	331	0	0
T52	542809	0	0	0
T53	1879	0	0	0
T54	101317	0	0	0
T55	10132	0	0	0
T56	55628	0	0	0
T57	290764	0	0	0
T58	110402	0	0	0
T59	0	2	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	343030953	6018	0	0
T49	12213	32	0	0
T50	12889	94	0	0
T51	5911	28	0	0
T60	5743	29	0	0
T63	1075	11	0	0
T69	36993	0	0	0
T74	1366	0	0	0
T83	817	0	0	0
T84	6724	116	0	0
T85	1504	0	0	0
T111	0	28	0	0
T112	0	8	0	0
T113	0	12	0	0
T114	0	32	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	343030953	5529	0	0
T49	12213	35	0	0
T50	12889	116	0	0
T51	5911	57	0	0
T60	5743	31	0	0
T63	1075	13	0	0
T69	36993	0	0	0
T74	1366	0	0	0
T83	817	0	0	0
T84	6724	125	0	0
T85	1504	0	0	0
T111	0	7	0	0
T112	0	34	0	0
T113	0	25	0	0
T114	0	22	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	343030953	5890	0	0
T49	12213	41	0	0
T50	12889	79	0	0
T51	5911	30	0	0
T60	5743	22	0	0
T63	1075	6	0	0
T69	36993	0	0	0
T74	1366	0	0	0
T83	817	0	0	0
T84	6724	159	0	0
T85	1504	0	0	0
T111	0	20	0	0
T112	0	23	0	0
T114	0	13	0	0
T115	0	5	0	0