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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.65 100.00 98.13 100.00 100.00 99.71 99.70 100.00


Total test records in report: 1025
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T517 /workspace/coverage/default/34.sram_ctrl_alert_test.800686684 Dec 31 12:29:04 PM PST 23 Dec 31 12:29:12 PM PST 23 62299603 ps
T518 /workspace/coverage/default/19.sram_ctrl_partial_access.3370326759 Dec 31 12:28:52 PM PST 23 Dec 31 12:29:14 PM PST 23 7731927061 ps
T519 /workspace/coverage/default/4.sram_ctrl_max_throughput.1205678127 Dec 31 12:27:35 PM PST 23 Dec 31 12:28:08 PM PST 23 843530220 ps
T520 /workspace/coverage/default/8.sram_ctrl_mem_partial_access.2999223352 Dec 31 12:28:42 PM PST 23 Dec 31 12:28:54 PM PST 23 161937397 ps
T521 /workspace/coverage/default/33.sram_ctrl_bijection.1236375174 Dec 31 12:30:34 PM PST 23 Dec 31 12:31:20 PM PST 23 1724605754 ps
T522 /workspace/coverage/default/25.sram_ctrl_regwen.1366496306 Dec 31 12:28:30 PM PST 23 Dec 31 12:38:20 PM PST 23 1823444661 ps
T523 /workspace/coverage/default/19.sram_ctrl_max_throughput.24203961 Dec 31 12:29:07 PM PST 23 Dec 31 12:29:26 PM PST 23 78439697 ps
T524 /workspace/coverage/default/4.sram_ctrl_stress_pipeline.227189610 Dec 31 12:27:52 PM PST 23 Dec 31 12:31:51 PM PST 23 2595684048 ps
T525 /workspace/coverage/default/3.sram_ctrl_alert_test.2701588331 Dec 31 12:29:02 PM PST 23 Dec 31 12:29:10 PM PST 23 13641624 ps
T526 /workspace/coverage/default/29.sram_ctrl_partial_access.1203377585 Dec 31 12:28:34 PM PST 23 Dec 31 12:28:54 PM PST 23 738171135 ps
T527 /workspace/coverage/default/47.sram_ctrl_stress_all.1113352352 Dec 31 12:29:40 PM PST 23 Dec 31 01:32:09 PM PST 23 65966694197 ps
T528 /workspace/coverage/default/9.sram_ctrl_executable.1065009042 Dec 31 12:28:56 PM PST 23 Dec 31 12:40:11 PM PST 23 31637707054 ps
T529 /workspace/coverage/default/28.sram_ctrl_max_throughput.1889350838 Dec 31 12:28:39 PM PST 23 Dec 31 12:29:03 PM PST 23 140704890 ps
T530 /workspace/coverage/default/19.sram_ctrl_mem_walk.3254377539 Dec 31 12:28:24 PM PST 23 Dec 31 12:28:31 PM PST 23 241712244 ps
T531 /workspace/coverage/default/13.sram_ctrl_executable.1813763513 Dec 31 12:28:37 PM PST 23 Dec 31 12:51:21 PM PST 23 211821631416 ps
T532 /workspace/coverage/default/25.sram_ctrl_mem_walk.1965546562 Dec 31 12:28:36 PM PST 23 Dec 31 12:28:55 PM PST 23 1317295569 ps
T533 /workspace/coverage/default/18.sram_ctrl_mem_walk.1976717907 Dec 31 12:28:03 PM PST 23 Dec 31 12:28:18 PM PST 23 676103159 ps
T534 /workspace/coverage/default/5.sram_ctrl_ram_cfg.2684748384 Dec 31 12:29:11 PM PST 23 Dec 31 12:29:18 PM PST 23 29222513 ps
T535 /workspace/coverage/default/5.sram_ctrl_bijection.1589615768 Dec 31 12:28:02 PM PST 23 Dec 31 12:29:08 PM PST 23 63787588483 ps
T536 /workspace/coverage/default/9.sram_ctrl_smoke.3917066243 Dec 31 12:27:50 PM PST 23 Dec 31 12:27:56 PM PST 23 707783877 ps
T537 /workspace/coverage/default/20.sram_ctrl_regwen.3084574635 Dec 31 12:29:35 PM PST 23 Dec 31 12:40:23 PM PST 23 3049471890 ps
T538 /workspace/coverage/default/38.sram_ctrl_access_during_key_req.2713239930 Dec 31 12:29:06 PM PST 23 Dec 31 12:37:36 PM PST 23 5515330733 ps
T539 /workspace/coverage/default/34.sram_ctrl_lc_escalation.3990268884 Dec 31 12:28:56 PM PST 23 Dec 31 12:29:09 PM PST 23 956507766 ps
T540 /workspace/coverage/default/9.sram_ctrl_stress_pipeline.1025476753 Dec 31 12:29:29 PM PST 23 Dec 31 12:33:57 PM PST 23 12079529350 ps
T541 /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.4127444154 Dec 31 12:29:08 PM PST 23 Dec 31 12:30:32 PM PST 23 1642885871 ps
T542 /workspace/coverage/default/6.sram_ctrl_stress_pipeline.2036212585 Dec 31 12:27:52 PM PST 23 Dec 31 12:32:31 PM PST 23 12161741333 ps
T543 /workspace/coverage/default/18.sram_ctrl_stress_pipeline.2141691956 Dec 31 12:28:22 PM PST 23 Dec 31 12:32:46 PM PST 23 10819120467 ps
T544 /workspace/coverage/default/35.sram_ctrl_multiple_keys.65331338 Dec 31 12:29:17 PM PST 23 Dec 31 12:47:01 PM PST 23 67646141961 ps
T545 /workspace/coverage/default/23.sram_ctrl_mem_partial_access.2608828530 Dec 31 12:28:08 PM PST 23 Dec 31 12:28:16 PM PST 23 174267748 ps
T546 /workspace/coverage/default/42.sram_ctrl_regwen.2251471846 Dec 31 12:29:05 PM PST 23 Dec 31 12:43:55 PM PST 23 52315932341 ps
T547 /workspace/coverage/default/24.sram_ctrl_stress_all.4042851861 Dec 31 12:28:21 PM PST 23 Dec 31 12:54:25 PM PST 23 115233051476 ps
T548 /workspace/coverage/default/12.sram_ctrl_stress_pipeline.3582369683 Dec 31 12:28:28 PM PST 23 Dec 31 12:33:22 PM PST 23 6315751094 ps
T549 /workspace/coverage/default/15.sram_ctrl_max_throughput.4271495588 Dec 31 12:30:26 PM PST 23 Dec 31 12:31:38 PM PST 23 737830947 ps
T550 /workspace/coverage/default/22.sram_ctrl_executable.1287122170 Dec 31 12:28:09 PM PST 23 Dec 31 12:41:03 PM PST 23 9890043881 ps
T551 /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.4261627942 Dec 31 12:29:37 PM PST 23 Dec 31 01:03:02 PM PST 23 4054156407 ps
T552 /workspace/coverage/default/13.sram_ctrl_lc_escalation.1165692077 Dec 31 12:28:19 PM PST 23 Dec 31 12:28:22 PM PST 23 100479717 ps
T553 /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.2459902349 Dec 31 12:28:52 PM PST 23 Dec 31 01:11:58 PM PST 23 3866313049 ps
T554 /workspace/coverage/default/33.sram_ctrl_mem_walk.3838214602 Dec 31 12:28:32 PM PST 23 Dec 31 12:28:48 PM PST 23 141164653 ps
T555 /workspace/coverage/default/16.sram_ctrl_ram_cfg.2256936143 Dec 31 12:28:44 PM PST 23 Dec 31 12:28:51 PM PST 23 29768901 ps
T556 /workspace/coverage/default/7.sram_ctrl_max_throughput.2716438244 Dec 31 12:28:04 PM PST 23 Dec 31 12:28:14 PM PST 23 233986900 ps
T557 /workspace/coverage/default/29.sram_ctrl_bijection.1010117945 Dec 31 12:30:32 PM PST 23 Dec 31 12:31:51 PM PST 23 3671220358 ps
T558 /workspace/coverage/default/2.sram_ctrl_partial_access.3332122351 Dec 31 12:28:11 PM PST 23 Dec 31 12:28:28 PM PST 23 456502094 ps
T559 /workspace/coverage/default/3.sram_ctrl_bijection.2811347034 Dec 31 12:27:53 PM PST 23 Dec 31 12:28:32 PM PST 23 5506353095 ps
T560 /workspace/coverage/default/48.sram_ctrl_mem_partial_access.2487045553 Dec 31 12:29:26 PM PST 23 Dec 31 12:29:33 PM PST 23 239821754 ps
T561 /workspace/coverage/default/11.sram_ctrl_lc_escalation.2781139131 Dec 31 12:28:47 PM PST 23 Dec 31 12:28:59 PM PST 23 999499250 ps
T562 /workspace/coverage/default/7.sram_ctrl_mem_walk.3506500710 Dec 31 12:28:22 PM PST 23 Dec 31 12:28:32 PM PST 23 140630993 ps
T563 /workspace/coverage/default/27.sram_ctrl_bijection.2052621745 Dec 31 12:28:47 PM PST 23 Dec 31 12:30:21 PM PST 23 13296923280 ps
T564 /workspace/coverage/default/41.sram_ctrl_lc_escalation.359650451 Dec 31 12:30:21 PM PST 23 Dec 31 12:30:35 PM PST 23 819286942 ps
T565 /workspace/coverage/default/21.sram_ctrl_multiple_keys.3472291356 Dec 31 12:28:39 PM PST 23 Dec 31 12:29:26 PM PST 23 3890961091 ps
T566 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.4117639285 Dec 31 12:28:44 PM PST 23 Dec 31 12:28:54 PM PST 23 256892588 ps
T567 /workspace/coverage/default/5.sram_ctrl_mem_partial_access.2983475375 Dec 31 12:28:00 PM PST 23 Dec 31 12:28:11 PM PST 23 68514621 ps
T568 /workspace/coverage/default/26.sram_ctrl_regwen.2503125131 Dec 31 12:30:28 PM PST 23 Dec 31 12:44:37 PM PST 23 57234010020 ps
T569 /workspace/coverage/default/8.sram_ctrl_max_throughput.423573520 Dec 31 12:28:24 PM PST 23 Dec 31 12:28:34 PM PST 23 210857693 ps
T570 /workspace/coverage/default/45.sram_ctrl_regwen.1797033757 Dec 31 12:30:31 PM PST 23 Dec 31 12:39:54 PM PST 23 70417725372 ps
T571 /workspace/coverage/default/4.sram_ctrl_lc_escalation.2713886140 Dec 31 12:28:05 PM PST 23 Dec 31 12:28:12 PM PST 23 445437264 ps
T572 /workspace/coverage/default/24.sram_ctrl_multiple_keys.2364727479 Dec 31 12:30:49 PM PST 23 Dec 31 12:46:51 PM PST 23 126740180705 ps
T573 /workspace/coverage/default/32.sram_ctrl_lc_escalation.59901690 Dec 31 12:30:19 PM PST 23 Dec 31 12:30:33 PM PST 23 1948963914 ps
T574 /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1920184125 Dec 31 12:30:30 PM PST 23 Dec 31 01:00:15 PM PST 23 1273499842 ps
T575 /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.454147250 Dec 31 12:28:44 PM PST 23 Dec 31 01:13:45 PM PST 23 478950927 ps
T576 /workspace/coverage/default/26.sram_ctrl_mem_walk.1327661458 Dec 31 12:30:19 PM PST 23 Dec 31 12:30:34 PM PST 23 1307681345 ps
T577 /workspace/coverage/default/5.sram_ctrl_access_during_key_req.339370896 Dec 31 12:30:04 PM PST 23 Dec 31 12:46:38 PM PST 23 7381829001 ps
T578 /workspace/coverage/default/14.sram_ctrl_executable.3312798871 Dec 31 12:28:31 PM PST 23 Dec 31 12:36:04 PM PST 23 15072014174 ps
T579 /workspace/coverage/default/39.sram_ctrl_smoke.2269932351 Dec 31 12:28:58 PM PST 23 Dec 31 12:29:12 PM PST 23 1203140168 ps
T580 /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2675621759 Dec 31 12:29:35 PM PST 23 Dec 31 12:33:08 PM PST 23 12448243501 ps
T581 /workspace/coverage/default/12.sram_ctrl_mem_walk.616306602 Dec 31 12:28:34 PM PST 23 Dec 31 12:28:51 PM PST 23 586271566 ps
T582 /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.1077801759 Dec 31 12:28:29 PM PST 23 Dec 31 12:28:43 PM PST 23 190782982 ps
T583 /workspace/coverage/default/11.sram_ctrl_ram_cfg.1822090634 Dec 31 12:28:27 PM PST 23 Dec 31 12:28:34 PM PST 23 61795935 ps
T584 /workspace/coverage/default/2.sram_ctrl_alert_test.2444656611 Dec 31 12:28:01 PM PST 23 Dec 31 12:28:08 PM PST 23 25711258 ps
T585 /workspace/coverage/default/12.sram_ctrl_access_during_key_req.4257666568 Dec 31 12:27:55 PM PST 23 Dec 31 12:43:09 PM PST 23 3658501644 ps
T586 /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.2762758639 Dec 31 12:30:16 PM PST 23 Dec 31 12:32:13 PM PST 23 583698779 ps
T587 /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1481002209 Dec 31 12:28:45 PM PST 23 Dec 31 01:01:32 PM PST 23 6874428757 ps
T588 /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1209566323 Dec 31 12:28:32 PM PST 23 Dec 31 12:36:45 PM PST 23 67437096469 ps
T589 /workspace/coverage/default/6.sram_ctrl_partial_access.2666510666 Dec 31 12:27:49 PM PST 23 Dec 31 12:28:53 PM PST 23 2295736423 ps
T590 /workspace/coverage/default/21.sram_ctrl_lc_escalation.428668780 Dec 31 12:28:20 PM PST 23 Dec 31 12:28:31 PM PST 23 2441493845 ps
T591 /workspace/coverage/default/1.sram_ctrl_mem_walk.3651384864 Dec 31 12:27:52 PM PST 23 Dec 31 12:28:03 PM PST 23 168841335 ps
T592 /workspace/coverage/default/39.sram_ctrl_access_during_key_req.3369358345 Dec 31 12:29:21 PM PST 23 Dec 31 12:44:37 PM PST 23 8115351878 ps
T593 /workspace/coverage/default/47.sram_ctrl_mem_partial_access.4006768045 Dec 31 12:29:24 PM PST 23 Dec 31 12:29:29 PM PST 23 85604036 ps
T594 /workspace/coverage/default/16.sram_ctrl_regwen.1021924947 Dec 31 12:28:36 PM PST 23 Dec 31 12:49:29 PM PST 23 21340567064 ps
T595 /workspace/coverage/default/13.sram_ctrl_stress_all.3165027604 Dec 31 12:28:51 PM PST 23 Dec 31 01:01:01 PM PST 23 43292541511 ps
T596 /workspace/coverage/default/43.sram_ctrl_access_during_key_req.2559744595 Dec 31 12:29:22 PM PST 23 Dec 31 12:39:18 PM PST 23 10057640922 ps
T597 /workspace/coverage/default/42.sram_ctrl_alert_test.1211965199 Dec 31 12:29:16 PM PST 23 Dec 31 12:29:21 PM PST 23 41966608 ps
T598 /workspace/coverage/default/34.sram_ctrl_access_during_key_req.1520800396 Dec 31 12:29:08 PM PST 23 Dec 31 12:41:41 PM PST 23 19705967791 ps
T599 /workspace/coverage/default/47.sram_ctrl_mem_walk.3950496028 Dec 31 12:29:04 PM PST 23 Dec 31 12:29:16 PM PST 23 332676002 ps
T600 /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.4011504344 Dec 31 12:28:01 PM PST 23 Dec 31 12:28:10 PM PST 23 201536887 ps
T601 /workspace/coverage/default/30.sram_ctrl_max_throughput.3382864579 Dec 31 12:28:50 PM PST 23 Dec 31 12:29:35 PM PST 23 402898893 ps
T602 /workspace/coverage/default/0.sram_ctrl_multiple_keys.3308990880 Dec 31 12:28:34 PM PST 23 Dec 31 12:46:14 PM PST 23 3951628426 ps
T603 /workspace/coverage/default/38.sram_ctrl_partial_access.4187157946 Dec 31 12:28:53 PM PST 23 Dec 31 12:29:12 PM PST 23 98136687 ps
T604 /workspace/coverage/default/13.sram_ctrl_stress_pipeline.2333877719 Dec 31 12:28:18 PM PST 23 Dec 31 12:33:08 PM PST 23 13376384390 ps
T605 /workspace/coverage/default/41.sram_ctrl_access_during_key_req.3233224831 Dec 31 12:29:24 PM PST 23 Dec 31 12:42:33 PM PST 23 1403901365 ps
T606 /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.3175362089 Dec 31 12:30:29 PM PST 23 Dec 31 12:35:20 PM PST 23 12318419324 ps
T607 /workspace/coverage/default/13.sram_ctrl_access_during_key_req.2676662817 Dec 31 12:29:33 PM PST 23 Dec 31 12:36:31 PM PST 23 2561494361 ps
T608 /workspace/coverage/default/45.sram_ctrl_executable.4096656406 Dec 31 12:30:56 PM PST 23 Dec 31 12:35:27 PM PST 23 706781420 ps
T609 /workspace/coverage/default/4.sram_ctrl_mem_partial_access.740457271 Dec 31 12:28:12 PM PST 23 Dec 31 12:28:17 PM PST 23 189356888 ps
T610 /workspace/coverage/default/20.sram_ctrl_access_during_key_req.3496378034 Dec 31 12:29:59 PM PST 23 Dec 31 12:34:13 PM PST 23 30370520341 ps
T611 /workspace/coverage/default/12.sram_ctrl_smoke.2980836137 Dec 31 12:29:34 PM PST 23 Dec 31 12:30:54 PM PST 23 4549138904 ps
T612 /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2349099864 Dec 31 12:29:28 PM PST 23 Dec 31 12:33:18 PM PST 23 13525558700 ps
T613 /workspace/coverage/default/47.sram_ctrl_smoke.4266157053 Dec 31 12:29:08 PM PST 23 Dec 31 12:29:17 PM PST 23 204890509 ps
T614 /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2816058229 Dec 31 12:28:59 PM PST 23 Dec 31 12:37:32 PM PST 23 24515003543 ps
T615 /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.397685163 Dec 31 12:28:42 PM PST 23 Dec 31 12:29:42 PM PST 23 494958550 ps
T616 /workspace/coverage/default/21.sram_ctrl_bijection.2935272503 Dec 31 12:28:38 PM PST 23 Dec 31 12:30:15 PM PST 23 22407516110 ps
T617 /workspace/coverage/default/31.sram_ctrl_mem_partial_access.3625835620 Dec 31 12:28:50 PM PST 23 Dec 31 12:29:00 PM PST 23 257731236 ps
T618 /workspace/coverage/default/14.sram_ctrl_multiple_keys.2115098130 Dec 31 12:29:46 PM PST 23 Dec 31 12:44:51 PM PST 23 2960075774 ps
T619 /workspace/coverage/default/43.sram_ctrl_ram_cfg.137474831 Dec 31 12:30:45 PM PST 23 Dec 31 12:30:50 PM PST 23 112189773 ps
T620 /workspace/coverage/default/46.sram_ctrl_stress_pipeline.2890767878 Dec 31 12:29:31 PM PST 23 Dec 31 12:34:03 PM PST 23 5510304830 ps
T621 /workspace/coverage/default/7.sram_ctrl_access_during_key_req.1879118014 Dec 31 12:27:36 PM PST 23 Dec 31 12:36:12 PM PST 23 1664327113 ps
T622 /workspace/coverage/default/6.sram_ctrl_multiple_keys.678336059 Dec 31 12:30:02 PM PST 23 Dec 31 12:42:37 PM PST 23 15702131646 ps
T623 /workspace/coverage/default/6.sram_ctrl_alert_test.1846135336 Dec 31 12:27:48 PM PST 23 Dec 31 12:27:50 PM PST 23 29349858 ps
T624 /workspace/coverage/default/43.sram_ctrl_alert_test.339337888 Dec 31 12:29:12 PM PST 23 Dec 31 12:29:18 PM PST 23 46541851 ps
T625 /workspace/coverage/default/32.sram_ctrl_smoke.1139980062 Dec 31 12:29:32 PM PST 23 Dec 31 12:29:44 PM PST 23 313321173 ps
T626 /workspace/coverage/default/37.sram_ctrl_stress_pipeline.2630292757 Dec 31 12:29:01 PM PST 23 Dec 31 12:33:42 PM PST 23 5779579334 ps
T627 /workspace/coverage/default/24.sram_ctrl_smoke.2825360555 Dec 31 12:28:20 PM PST 23 Dec 31 12:28:25 PM PST 23 98668150 ps
T628 /workspace/coverage/default/15.sram_ctrl_smoke.2570663538 Dec 31 12:28:36 PM PST 23 Dec 31 12:28:47 PM PST 23 468923313 ps
T629 /workspace/coverage/default/26.sram_ctrl_bijection.3469620623 Dec 31 12:28:41 PM PST 23 Dec 31 12:29:15 PM PST 23 5542886064 ps
T630 /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2390935272 Dec 31 12:28:07 PM PST 23 Dec 31 01:35:40 PM PST 23 380583332 ps
T631 /workspace/coverage/default/0.sram_ctrl_access_during_key_req.936163962 Dec 31 12:27:28 PM PST 23 Dec 31 12:41:42 PM PST 23 13807141209 ps
T22 /workspace/coverage/default/4.sram_ctrl_sec_cm.1699819750 Dec 31 12:30:39 PM PST 23 Dec 31 12:30:46 PM PST 23 163835861 ps
T34 /workspace/coverage/default/13.sram_ctrl_max_throughput.3112955496 Dec 31 12:29:50 PM PST 23 Dec 31 12:30:51 PM PST 23 115040796 ps
T35 /workspace/coverage/default/12.sram_ctrl_executable.3399172295 Dec 31 12:28:03 PM PST 23 Dec 31 12:29:29 PM PST 23 5603351171 ps
T36 /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3446131346 Dec 31 12:29:25 PM PST 23 Dec 31 12:30:44 PM PST 23 133596867 ps
T37 /workspace/coverage/default/29.sram_ctrl_multiple_keys.3933902409 Dec 31 12:29:11 PM PST 23 Dec 31 12:40:34 PM PST 23 36835592613 ps
T38 /workspace/coverage/default/11.sram_ctrl_multiple_keys.3545857433 Dec 31 12:27:58 PM PST 23 Dec 31 12:31:36 PM PST 23 2222401952 ps
T39 /workspace/coverage/default/4.sram_ctrl_stress_all.2984572562 Dec 31 12:27:38 PM PST 23 Dec 31 01:16:57 PM PST 23 21744791251 ps
T40 /workspace/coverage/default/28.sram_ctrl_mem_walk.303849363 Dec 31 12:28:50 PM PST 23 Dec 31 12:29:10 PM PST 23 1340110047 ps
T41 /workspace/coverage/default/31.sram_ctrl_lc_escalation.396133714 Dec 31 12:29:47 PM PST 23 Dec 31 12:29:57 PM PST 23 670978847 ps
T42 /workspace/coverage/default/16.sram_ctrl_mem_walk.524245911 Dec 31 12:27:46 PM PST 23 Dec 31 12:27:57 PM PST 23 456998584 ps
T632 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2222943145 Dec 31 12:30:29 PM PST 23 Dec 31 01:40:02 PM PST 23 6902049333 ps
T633 /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.434842036 Dec 31 12:28:45 PM PST 23 Dec 31 12:51:52 PM PST 23 5244332982 ps
T634 /workspace/coverage/default/1.sram_ctrl_regwen.2696662594 Dec 31 12:27:26 PM PST 23 Dec 31 12:41:06 PM PST 23 2142567365 ps
T635 /workspace/coverage/default/5.sram_ctrl_multiple_keys.2225613150 Dec 31 12:27:42 PM PST 23 Dec 31 12:34:08 PM PST 23 1386543142 ps
T636 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.1797845201 Dec 31 12:28:20 PM PST 23 Dec 31 12:28:32 PM PST 23 125765494 ps
T637 /workspace/coverage/default/41.sram_ctrl_ram_cfg.1191463100 Dec 31 12:28:52 PM PST 23 Dec 31 12:28:58 PM PST 23 46631498 ps
T638 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.62563808 Dec 31 12:30:04 PM PST 23 Dec 31 12:37:51 PM PST 23 36898070190 ps
T639 /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2470308514 Dec 31 12:28:22 PM PST 23 Dec 31 01:22:13 PM PST 23 3705053555 ps
T640 /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3857605942 Dec 31 12:31:02 PM PST 23 Dec 31 01:32:50 PM PST 23 1776315724 ps
T641 /workspace/coverage/default/36.sram_ctrl_ram_cfg.998588830 Dec 31 12:28:30 PM PST 23 Dec 31 12:28:41 PM PST 23 51349091 ps
T642 /workspace/coverage/default/45.sram_ctrl_mem_partial_access.2416137025 Dec 31 12:30:48 PM PST 23 Dec 31 12:30:55 PM PST 23 116603371 ps
T643 /workspace/coverage/default/19.sram_ctrl_alert_test.2525183462 Dec 31 12:28:05 PM PST 23 Dec 31 12:28:10 PM PST 23 20070909 ps
T644 /workspace/coverage/default/7.sram_ctrl_executable.654899037 Dec 31 12:27:37 PM PST 23 Dec 31 12:32:01 PM PST 23 40795577232 ps
T645 /workspace/coverage/default/33.sram_ctrl_smoke.2468963374 Dec 31 12:28:49 PM PST 23 Dec 31 12:29:04 PM PST 23 437740981 ps
T646 /workspace/coverage/default/48.sram_ctrl_partial_access.321241934 Dec 31 12:29:34 PM PST 23 Dec 31 12:29:49 PM PST 23 3880173199 ps
T647 /workspace/coverage/default/36.sram_ctrl_access_during_key_req.4258156718 Dec 31 12:28:52 PM PST 23 Dec 31 12:41:19 PM PST 23 9702191750 ps
T648 /workspace/coverage/default/34.sram_ctrl_mem_walk.3922288892 Dec 31 12:29:19 PM PST 23 Dec 31 12:29:27 PM PST 23 77140985 ps
T649 /workspace/coverage/default/49.sram_ctrl_stress_all.3169690468 Dec 31 12:30:08 PM PST 23 Dec 31 01:25:42 PM PST 23 99787150818 ps
T650 /workspace/coverage/default/8.sram_ctrl_access_during_key_req.3430831105 Dec 31 12:29:08 PM PST 23 Dec 31 12:44:31 PM PST 23 15384739192 ps
T651 /workspace/coverage/default/46.sram_ctrl_max_throughput.2481632712 Dec 31 12:29:23 PM PST 23 Dec 31 12:29:55 PM PST 23 113897875 ps
T652 /workspace/coverage/default/6.sram_ctrl_lc_escalation.3362202770 Dec 31 12:29:51 PM PST 23 Dec 31 12:30:01 PM PST 23 776434955 ps
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T728 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1791387148 Dec 31 12:28:05 PM PST 23 Dec 31 01:13:47 PM PST 23 270051185 ps
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T730 /workspace/coverage/default/44.sram_ctrl_smoke.3501669853 Dec 31 12:30:45 PM PST 23 Dec 31 12:32:10 PM PST 23 289100402 ps
T731 /workspace/coverage/default/20.sram_ctrl_ram_cfg.2519483291 Dec 31 12:28:41 PM PST 23 Dec 31 12:28:50 PM PST 23 79610384 ps
T732 /workspace/coverage/default/1.sram_ctrl_partial_access.1776364689 Dec 31 12:29:55 PM PST 23 Dec 31 12:30:16 PM PST 23 1058692059 ps
T733 /workspace/coverage/default/37.sram_ctrl_regwen.2706607158 Dec 31 12:29:08 PM PST 23 Dec 31 12:43:50 PM PST 23 33311226871 ps
T734 /workspace/coverage/default/8.sram_ctrl_smoke.2889524041 Dec 31 12:28:28 PM PST 23 Dec 31 12:30:10 PM PST 23 275714616 ps
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T739 /workspace/coverage/default/17.sram_ctrl_access_during_key_req.1359186408 Dec 31 12:28:29 PM PST 23 Dec 31 12:48:57 PM PST 23 16901473782 ps
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T741 /workspace/coverage/default/6.sram_ctrl_access_during_key_req.92222487 Dec 31 12:27:47 PM PST 23 Dec 31 12:31:22 PM PST 23 5730932187 ps
T742 /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.4284068437 Dec 31 12:28:00 PM PST 23 Dec 31 12:32:34 PM PST 23 7809564632 ps
T743 /workspace/coverage/default/42.sram_ctrl_stress_pipeline.1323475775 Dec 31 12:30:27 PM PST 23 Dec 31 12:34:18 PM PST 23 2498425436 ps
T744 /workspace/coverage/default/45.sram_ctrl_mem_walk.701452525 Dec 31 12:29:16 PM PST 23 Dec 31 12:29:25 PM PST 23 699791969 ps
T745 /workspace/coverage/default/42.sram_ctrl_mem_partial_access.1043973489 Dec 31 12:28:56 PM PST 23 Dec 31 12:29:03 PM PST 23 251192339 ps
T746 /workspace/coverage/default/36.sram_ctrl_stress_pipeline.1306043020 Dec 31 12:28:53 PM PST 23 Dec 31 12:32:15 PM PST 23 8602073841 ps
T747 /workspace/coverage/default/43.sram_ctrl_bijection.3099507578 Dec 31 12:29:04 PM PST 23 Dec 31 12:30:00 PM PST 23 15195540026 ps
T748 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.968002079 Dec 31 12:27:53 PM PST 23 Dec 31 12:28:04 PM PST 23 249577463 ps
T749 /workspace/coverage/default/40.sram_ctrl_smoke.3595417872 Dec 31 12:29:40 PM PST 23 Dec 31 12:29:59 PM PST 23 4771287311 ps
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T752 /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.268919503 Dec 31 12:27:45 PM PST 23 Dec 31 01:39:37 PM PST 23 1811853093 ps
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T754 /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1207229887 Dec 31 12:28:57 PM PST 23 Dec 31 12:31:00 PM PST 23 577596607 ps
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