| T755 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.582429080 |
|
|
Dec 31 12:29:18 PM PST 23 |
Dec 31 12:29:23 PM PST 23 |
41642450 ps |
| T756 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.1621051469 |
|
|
Dec 31 12:29:01 PM PST 23 |
Dec 31 12:30:00 PM PST 23 |
139284002 ps |
| T24 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.515066242 |
|
|
Dec 31 12:27:45 PM PST 23 |
Dec 31 12:27:49 PM PST 23 |
965916263 ps |
| T757 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.402400255 |
|
|
Dec 31 12:29:10 PM PST 23 |
Dec 31 12:29:25 PM PST 23 |
920548383 ps |
| T758 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.953946279 |
|
|
Dec 31 12:29:18 PM PST 23 |
Dec 31 12:32:30 PM PST 23 |
2739114282 ps |
| T759 |
/workspace/coverage/default/45.sram_ctrl_partial_access.2814584152 |
|
|
Dec 31 12:29:30 PM PST 23 |
Dec 31 12:29:36 PM PST 23 |
755965500 ps |
| T760 |
/workspace/coverage/default/38.sram_ctrl_smoke.4033627308 |
|
|
Dec 31 12:29:01 PM PST 23 |
Dec 31 12:29:23 PM PST 23 |
454718419 ps |
| T761 |
/workspace/coverage/default/13.sram_ctrl_alert_test.2279873017 |
|
|
Dec 31 12:31:02 PM PST 23 |
Dec 31 12:31:10 PM PST 23 |
17437807 ps |
| T762 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.251193205 |
|
|
Dec 31 12:29:34 PM PST 23 |
Dec 31 12:36:55 PM PST 23 |
2062543400 ps |
| T763 |
/workspace/coverage/default/28.sram_ctrl_alert_test.3377488800 |
|
|
Dec 31 12:30:30 PM PST 23 |
Dec 31 12:30:36 PM PST 23 |
17144022 ps |
| T764 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3578346345 |
|
|
Dec 31 12:30:22 PM PST 23 |
Dec 31 12:32:02 PM PST 23 |
579834204 ps |
| T765 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.3454817785 |
|
|
Dec 31 12:28:49 PM PST 23 |
Dec 31 12:33:29 PM PST 23 |
22159404152 ps |
| T766 |
/workspace/coverage/default/26.sram_ctrl_partial_access.3986030031 |
|
|
Dec 31 12:30:26 PM PST 23 |
Dec 31 12:30:35 PM PST 23 |
125718047 ps |
| T767 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.699219427 |
|
|
Dec 31 12:29:25 PM PST 23 |
Dec 31 12:42:25 PM PST 23 |
12087386592 ps |
| T768 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.2592328328 |
|
|
Dec 31 12:30:26 PM PST 23 |
Dec 31 12:30:41 PM PST 23 |
67132839 ps |
| T769 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.1291316558 |
|
|
Dec 31 12:28:40 PM PST 23 |
Dec 31 12:28:51 PM PST 23 |
79823975 ps |
| T770 |
/workspace/coverage/default/19.sram_ctrl_regwen.567419006 |
|
|
Dec 31 12:29:12 PM PST 23 |
Dec 31 12:40:10 PM PST 23 |
9894528480 ps |
| T771 |
/workspace/coverage/default/20.sram_ctrl_bijection.162320786 |
|
|
Dec 31 12:30:06 PM PST 23 |
Dec 31 12:30:33 PM PST 23 |
1581004612 ps |
| T772 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1257296399 |
|
|
Dec 31 12:29:23 PM PST 23 |
Dec 31 12:36:00 PM PST 23 |
18805113933 ps |
| T773 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.2181521313 |
|
|
Dec 31 12:28:39 PM PST 23 |
Dec 31 12:28:56 PM PST 23 |
2279013321 ps |
| T774 |
/workspace/coverage/default/11.sram_ctrl_alert_test.2848340661 |
|
|
Dec 31 12:28:12 PM PST 23 |
Dec 31 12:28:14 PM PST 23 |
39676506 ps |
| T775 |
/workspace/coverage/default/37.sram_ctrl_alert_test.1511932946 |
|
|
Dec 31 12:31:01 PM PST 23 |
Dec 31 12:31:09 PM PST 23 |
13328114 ps |
| T776 |
/workspace/coverage/default/24.sram_ctrl_alert_test.3906725215 |
|
|
Dec 31 12:28:53 PM PST 23 |
Dec 31 12:28:59 PM PST 23 |
22195867 ps |
| T777 |
/workspace/coverage/default/36.sram_ctrl_stress_all.3931923480 |
|
|
Dec 31 12:28:47 PM PST 23 |
Dec 31 12:50:24 PM PST 23 |
143622802621 ps |
| T778 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.3469549761 |
|
|
Dec 31 12:29:03 PM PST 23 |
Dec 31 12:29:15 PM PST 23 |
235217970 ps |
| T779 |
/workspace/coverage/default/4.sram_ctrl_partial_access.1257135101 |
|
|
Dec 31 12:28:43 PM PST 23 |
Dec 31 12:28:51 PM PST 23 |
82755091 ps |
| T780 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.1705673410 |
|
|
Dec 31 12:28:57 PM PST 23 |
Dec 31 12:29:06 PM PST 23 |
250681515 ps |
| T781 |
/workspace/coverage/default/31.sram_ctrl_bijection.3973047310 |
|
|
Dec 31 12:28:54 PM PST 23 |
Dec 31 12:29:27 PM PST 23 |
1506602276 ps |
| T782 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.864800308 |
|
|
Dec 31 12:31:03 PM PST 23 |
Dec 31 12:44:17 PM PST 23 |
20238977297 ps |
| T783 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.1998902523 |
|
|
Dec 31 12:28:59 PM PST 23 |
Dec 31 12:46:07 PM PST 23 |
17975942684 ps |
| T784 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.2808303313 |
|
|
Dec 31 12:29:10 PM PST 23 |
Dec 31 12:29:18 PM PST 23 |
48717654 ps |
| T785 |
/workspace/coverage/default/7.sram_ctrl_regwen.2018872090 |
|
|
Dec 31 12:28:01 PM PST 23 |
Dec 31 12:28:34 PM PST 23 |
1474751612 ps |
| T786 |
/workspace/coverage/default/44.sram_ctrl_bijection.2843056693 |
|
|
Dec 31 12:31:02 PM PST 23 |
Dec 31 12:31:45 PM PST 23 |
30061620393 ps |
| T787 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.1190354142 |
|
|
Dec 31 12:28:06 PM PST 23 |
Dec 31 12:28:15 PM PST 23 |
290928753 ps |
| T788 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.1836717644 |
|
|
Dec 31 12:29:26 PM PST 23 |
Dec 31 12:29:29 PM PST 23 |
32126875 ps |
| T789 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.1901090290 |
|
|
Dec 31 12:28:46 PM PST 23 |
Dec 31 12:28:56 PM PST 23 |
229086828 ps |
| T790 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.1036425481 |
|
|
Dec 31 12:29:07 PM PST 23 |
Dec 31 12:30:02 PM PST 23 |
501746195 ps |
| T791 |
/workspace/coverage/default/0.sram_ctrl_partial_access.3776061651 |
|
|
Dec 31 12:28:13 PM PST 23 |
Dec 31 12:28:28 PM PST 23 |
145622412 ps |
| T792 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.1076195254 |
|
|
Dec 31 12:27:52 PM PST 23 |
Dec 31 12:28:00 PM PST 23 |
105126325 ps |
| T793 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.1209548039 |
|
|
Dec 31 12:29:35 PM PST 23 |
Dec 31 12:34:51 PM PST 23 |
13199226237 ps |
| T794 |
/workspace/coverage/default/5.sram_ctrl_stress_all.3431174919 |
|
|
Dec 31 12:27:57 PM PST 23 |
Dec 31 01:14:53 PM PST 23 |
50330461486 ps |
| T795 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.2707958417 |
|
|
Dec 31 12:30:01 PM PST 23 |
Dec 31 12:30:09 PM PST 23 |
224814801 ps |
| T796 |
/workspace/coverage/default/46.sram_ctrl_alert_test.60510833 |
|
|
Dec 31 12:29:13 PM PST 23 |
Dec 31 12:29:18 PM PST 23 |
15491179 ps |
| T797 |
/workspace/coverage/default/16.sram_ctrl_smoke.3949009068 |
|
|
Dec 31 12:29:48 PM PST 23 |
Dec 31 12:30:05 PM PST 23 |
2858285852 ps |
| T798 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.858169813 |
|
|
Dec 31 12:28:41 PM PST 23 |
Dec 31 12:31:17 PM PST 23 |
1621687974 ps |
| T799 |
/workspace/coverage/default/40.sram_ctrl_executable.1201256109 |
|
|
Dec 31 12:31:14 PM PST 23 |
Dec 31 12:49:04 PM PST 23 |
6699149272 ps |
| T800 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1316481549 |
|
|
Dec 31 12:28:32 PM PST 23 |
Dec 31 12:41:52 PM PST 23 |
373605988 ps |
| T801 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.1705557464 |
|
|
Dec 31 12:28:50 PM PST 23 |
Dec 31 12:29:06 PM PST 23 |
2734880095 ps |
| T802 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.1476528834 |
|
|
Dec 31 12:28:48 PM PST 23 |
Dec 31 12:31:25 PM PST 23 |
11719228979 ps |
| T803 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.207692636 |
|
|
Dec 31 12:27:44 PM PST 23 |
Dec 31 12:35:23 PM PST 23 |
6827921880 ps |
| T804 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.3560339492 |
|
|
Dec 31 12:28:50 PM PST 23 |
Dec 31 12:30:20 PM PST 23 |
450265195 ps |
| T805 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.777216863 |
|
|
Dec 31 12:27:34 PM PST 23 |
Dec 31 12:30:17 PM PST 23 |
1808687640 ps |
| T806 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.695103158 |
|
|
Dec 31 12:29:00 PM PST 23 |
Dec 31 12:29:15 PM PST 23 |
156056371 ps |
| T807 |
/workspace/coverage/default/37.sram_ctrl_executable.3402770442 |
|
|
Dec 31 12:29:01 PM PST 23 |
Dec 31 12:40:29 PM PST 23 |
67954597612 ps |
| T808 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.1159814461 |
|
|
Dec 31 12:28:01 PM PST 23 |
Dec 31 12:28:11 PM PST 23 |
166788321 ps |
| T809 |
/workspace/coverage/default/35.sram_ctrl_regwen.39816553 |
|
|
Dec 31 12:30:46 PM PST 23 |
Dec 31 01:02:24 PM PST 23 |
19165972429 ps |
| T810 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.3196022982 |
|
|
Dec 31 12:30:52 PM PST 23 |
Dec 31 12:32:40 PM PST 23 |
1849632729 ps |
| T811 |
/workspace/coverage/default/26.sram_ctrl_smoke.4098962903 |
|
|
Dec 31 12:28:33 PM PST 23 |
Dec 31 12:28:53 PM PST 23 |
263009473 ps |
| T812 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.448987782 |
|
|
Dec 31 12:30:16 PM PST 23 |
Dec 31 12:30:23 PM PST 23 |
31114331 ps |
| T813 |
/workspace/coverage/default/8.sram_ctrl_regwen.187660970 |
|
|
Dec 31 12:29:58 PM PST 23 |
Dec 31 12:37:26 PM PST 23 |
10133011416 ps |
| T814 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1425577545 |
|
|
Dec 31 12:29:04 PM PST 23 |
Dec 31 12:34:33 PM PST 23 |
66975587380 ps |
| T815 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.3505002675 |
|
|
Dec 31 12:29:16 PM PST 23 |
Dec 31 12:29:21 PM PST 23 |
77247124 ps |
| T816 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.1623481626 |
|
|
Dec 31 12:29:41 PM PST 23 |
Dec 31 12:43:41 PM PST 23 |
4084627799 ps |
| T817 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.544737296 |
|
|
Dec 31 12:28:47 PM PST 23 |
Dec 31 12:28:57 PM PST 23 |
242488872 ps |
| T818 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.1462340121 |
|
|
Dec 31 12:28:48 PM PST 23 |
Dec 31 12:28:55 PM PST 23 |
544353160 ps |
| T819 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.514889280 |
|
|
Dec 31 12:29:15 PM PST 23 |
Dec 31 01:13:43 PM PST 23 |
1323335231 ps |
| T820 |
/workspace/coverage/default/8.sram_ctrl_alert_test.4178181634 |
|
|
Dec 31 12:29:55 PM PST 23 |
Dec 31 12:29:57 PM PST 23 |
22313416 ps |
| T821 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3833283705 |
|
|
Dec 31 12:30:54 PM PST 23 |
Dec 31 12:33:58 PM PST 23 |
8019360884 ps |
| T822 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.3703111567 |
|
|
Dec 31 12:28:52 PM PST 23 |
Dec 31 12:28:58 PM PST 23 |
139811216 ps |
| T823 |
/workspace/coverage/default/10.sram_ctrl_smoke.4115228680 |
|
|
Dec 31 12:28:16 PM PST 23 |
Dec 31 12:29:22 PM PST 23 |
132630707 ps |
| T824 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.2663967333 |
|
|
Dec 31 12:28:34 PM PST 23 |
Dec 31 12:28:47 PM PST 23 |
360680995 ps |
| T825 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.3739732016 |
|
|
Dec 31 12:30:31 PM PST 23 |
Dec 31 12:30:38 PM PST 23 |
62867407 ps |
| T826 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.859153059 |
|
|
Dec 31 12:30:57 PM PST 23 |
Dec 31 12:50:03 PM PST 23 |
436357618 ps |
| T827 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.104871047 |
|
|
Dec 31 12:28:54 PM PST 23 |
Dec 31 12:50:31 PM PST 23 |
8967655690 ps |
| T828 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2344557900 |
|
|
Dec 31 12:28:35 PM PST 23 |
Dec 31 12:29:47 PM PST 23 |
522454225 ps |
| T829 |
/workspace/coverage/default/14.sram_ctrl_stress_all.3163249887 |
|
|
Dec 31 12:28:49 PM PST 23 |
Dec 31 01:44:26 PM PST 23 |
52024736816 ps |
| T830 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.940020481 |
|
|
Dec 31 12:28:07 PM PST 23 |
Dec 31 12:28:20 PM PST 23 |
670414086 ps |
| T831 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1115597760 |
|
|
Dec 31 12:27:52 PM PST 23 |
Dec 31 12:28:01 PM PST 23 |
77238562 ps |
| T832 |
/workspace/coverage/default/19.sram_ctrl_bijection.246716022 |
|
|
Dec 31 12:28:20 PM PST 23 |
Dec 31 12:29:26 PM PST 23 |
9313068715 ps |
| T833 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.155813290 |
|
|
Dec 31 12:29:15 PM PST 23 |
Dec 31 12:30:03 PM PST 23 |
998334861 ps |
| T834 |
/workspace/coverage/default/25.sram_ctrl_stress_all.427621604 |
|
|
Dec 31 12:29:07 PM PST 23 |
Dec 31 12:59:59 PM PST 23 |
27333823470 ps |
| T835 |
/workspace/coverage/default/44.sram_ctrl_alert_test.1141953817 |
|
|
Dec 31 12:29:18 PM PST 23 |
Dec 31 12:29:23 PM PST 23 |
36482869 ps |
| T836 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.2401048854 |
|
|
Dec 31 12:29:08 PM PST 23 |
Dec 31 12:40:38 PM PST 23 |
9003899633 ps |
| T837 |
/workspace/coverage/default/42.sram_ctrl_smoke.3639554112 |
|
|
Dec 31 12:29:30 PM PST 23 |
Dec 31 12:30:19 PM PST 23 |
119914462 ps |
| T838 |
/workspace/coverage/default/47.sram_ctrl_bijection.2056911676 |
|
|
Dec 31 12:29:39 PM PST 23 |
Dec 31 12:30:17 PM PST 23 |
3683461886 ps |
| T839 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.526263520 |
|
|
Dec 31 12:28:46 PM PST 23 |
Dec 31 12:29:00 PM PST 23 |
138251401 ps |
| T840 |
/workspace/coverage/default/30.sram_ctrl_partial_access.3632140154 |
|
|
Dec 31 12:30:42 PM PST 23 |
Dec 31 12:31:44 PM PST 23 |
4492408212 ps |
| T841 |
/workspace/coverage/default/6.sram_ctrl_executable.1160147602 |
|
|
Dec 31 12:29:36 PM PST 23 |
Dec 31 12:38:29 PM PST 23 |
8084802322 ps |
| T842 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.3495411181 |
|
|
Dec 31 12:29:10 PM PST 23 |
Dec 31 12:29:21 PM PST 23 |
140639524 ps |
| T843 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.2188798214 |
|
|
Dec 31 12:28:51 PM PST 23 |
Dec 31 12:29:51 PM PST 23 |
110380145 ps |
| T844 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.2970695270 |
|
|
Dec 31 12:30:40 PM PST 23 |
Dec 31 12:30:46 PM PST 23 |
55824376 ps |
| T845 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2984167427 |
|
|
Dec 31 12:29:08 PM PST 23 |
Dec 31 12:33:35 PM PST 23 |
10995008685 ps |
| T846 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.4149915528 |
|
|
Dec 31 12:28:58 PM PST 23 |
Dec 31 12:29:14 PM PST 23 |
994596524 ps |
| T847 |
/workspace/coverage/default/43.sram_ctrl_smoke.276265775 |
|
|
Dec 31 12:29:02 PM PST 23 |
Dec 31 12:29:13 PM PST 23 |
129693094 ps |
| T848 |
/workspace/coverage/default/38.sram_ctrl_regwen.4169268234 |
|
|
Dec 31 12:28:38 PM PST 23 |
Dec 31 12:32:13 PM PST 23 |
903711947 ps |
| T849 |
/workspace/coverage/default/11.sram_ctrl_partial_access.230029231 |
|
|
Dec 31 12:29:03 PM PST 23 |
Dec 31 12:29:22 PM PST 23 |
204620312 ps |
| T850 |
/workspace/coverage/default/46.sram_ctrl_partial_access.3963535039 |
|
|
Dec 31 12:29:30 PM PST 23 |
Dec 31 12:29:42 PM PST 23 |
458174094 ps |
| T851 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.1539324251 |
|
|
Dec 31 12:29:25 PM PST 23 |
Dec 31 12:39:54 PM PST 23 |
3756334248 ps |
| T852 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.3881449930 |
|
|
Dec 31 12:28:35 PM PST 23 |
Dec 31 12:28:44 PM PST 23 |
35344320 ps |
| T853 |
/workspace/coverage/default/41.sram_ctrl_partial_access.508460670 |
|
|
Dec 31 12:29:28 PM PST 23 |
Dec 31 12:29:36 PM PST 23 |
1181953659 ps |
| T854 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.650947510 |
|
|
Dec 31 12:28:54 PM PST 23 |
Dec 31 12:36:15 PM PST 23 |
64342366883 ps |
| T855 |
/workspace/coverage/default/30.sram_ctrl_stress_all.2195254784 |
|
|
Dec 31 12:28:31 PM PST 23 |
Dec 31 01:32:25 PM PST 23 |
126073064044 ps |
| T856 |
/workspace/coverage/default/14.sram_ctrl_alert_test.3644665143 |
|
|
Dec 31 12:28:01 PM PST 23 |
Dec 31 12:28:08 PM PST 23 |
40965612 ps |
| T857 |
/workspace/coverage/default/21.sram_ctrl_executable.2190446274 |
|
|
Dec 31 12:29:53 PM PST 23 |
Dec 31 12:35:02 PM PST 23 |
7031654162 ps |
| T858 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.56055321 |
|
|
Dec 31 12:28:54 PM PST 23 |
Dec 31 12:32:12 PM PST 23 |
9558775080 ps |
| T859 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.658706481 |
|
|
Dec 31 12:28:47 PM PST 23 |
Dec 31 12:28:54 PM PST 23 |
31758446 ps |
| T860 |
/workspace/coverage/default/5.sram_ctrl_partial_access.1289293933 |
|
|
Dec 31 12:28:36 PM PST 23 |
Dec 31 12:29:09 PM PST 23 |
357421420 ps |
| T861 |
/workspace/coverage/default/23.sram_ctrl_executable.320558518 |
|
|
Dec 31 12:29:42 PM PST 23 |
Dec 31 12:33:33 PM PST 23 |
11459126180 ps |
| T862 |
/workspace/coverage/default/16.sram_ctrl_alert_test.3577994674 |
|
|
Dec 31 12:28:47 PM PST 23 |
Dec 31 12:28:53 PM PST 23 |
30928583 ps |
| T863 |
/workspace/coverage/default/30.sram_ctrl_alert_test.2395059665 |
|
|
Dec 31 12:29:17 PM PST 23 |
Dec 31 12:29:22 PM PST 23 |
62631126 ps |
| T864 |
/workspace/coverage/default/38.sram_ctrl_alert_test.1479552060 |
|
|
Dec 31 12:28:59 PM PST 23 |
Dec 31 12:29:07 PM PST 23 |
16219075 ps |
| T865 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3241012927 |
|
|
Dec 31 12:29:15 PM PST 23 |
Dec 31 12:58:38 PM PST 23 |
1219300247 ps |
| T866 |
/workspace/coverage/default/40.sram_ctrl_stress_all.4285481039 |
|
|
Dec 31 12:30:22 PM PST 23 |
Dec 31 01:27:33 PM PST 23 |
11167114885 ps |
| T867 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.740366185 |
|
|
Dec 31 12:29:22 PM PST 23 |
Dec 31 12:30:12 PM PST 23 |
930349701 ps |
| T868 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.723053447 |
|
|
Dec 31 12:28:23 PM PST 23 |
Dec 31 12:29:12 PM PST 23 |
806244419 ps |
| T869 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.3940352610 |
|
|
Dec 31 12:28:52 PM PST 23 |
Dec 31 12:28:58 PM PST 23 |
130479005 ps |
| T870 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.3516900146 |
|
|
Dec 31 12:28:50 PM PST 23 |
Dec 31 12:29:00 PM PST 23 |
334827045 ps |
| T871 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.981129306 |
|
|
Dec 31 12:27:58 PM PST 23 |
Dec 31 12:28:20 PM PST 23 |
338945953 ps |
| T872 |
/workspace/coverage/default/29.sram_ctrl_stress_all.231587324 |
|
|
Dec 31 12:28:54 PM PST 23 |
Dec 31 12:40:28 PM PST 23 |
20387727860 ps |
| T873 |
/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.131022756 |
|
|
Dec 31 12:29:28 PM PST 23 |
Dec 31 12:30:54 PM PST 23 |
2350961798 ps |
| T874 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.1702457253 |
|
|
Dec 31 12:28:59 PM PST 23 |
Dec 31 12:29:10 PM PST 23 |
27639809 ps |
| T875 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.1291772877 |
|
|
Dec 31 12:28:37 PM PST 23 |
Dec 31 12:40:22 PM PST 23 |
2839271341 ps |
| T876 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.3856822296 |
|
|
Dec 31 12:30:13 PM PST 23 |
Dec 31 12:30:18 PM PST 23 |
89496832 ps |
| T877 |
/workspace/coverage/default/4.sram_ctrl_regwen.274036607 |
|
|
Dec 31 12:27:56 PM PST 23 |
Dec 31 12:34:26 PM PST 23 |
6520785549 ps |
| T878 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.658554998 |
|
|
Dec 31 12:29:01 PM PST 23 |
Dec 31 12:29:13 PM PST 23 |
62709304 ps |
| T879 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.2403590787 |
|
|
Dec 31 12:29:59 PM PST 23 |
Dec 31 12:34:24 PM PST 23 |
5486694145 ps |
| T880 |
/workspace/coverage/default/20.sram_ctrl_smoke.3149044472 |
|
|
Dec 31 12:28:21 PM PST 23 |
Dec 31 12:28:25 PM PST 23 |
128532216 ps |
| T881 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.725301305 |
|
|
Dec 31 12:28:19 PM PST 23 |
Dec 31 12:28:24 PM PST 23 |
170095281 ps |
| T882 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.1230272738 |
|
|
Dec 31 12:27:46 PM PST 23 |
Dec 31 12:27:53 PM PST 23 |
186908389 ps |
| T883 |
/workspace/coverage/default/36.sram_ctrl_executable.1363217537 |
|
|
Dec 31 12:28:48 PM PST 23 |
Dec 31 12:44:14 PM PST 23 |
3427672697 ps |
| T884 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.558906144 |
|
|
Dec 31 12:28:01 PM PST 23 |
Dec 31 12:31:16 PM PST 23 |
14388009155 ps |
| T885 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.3040217331 |
|
|
Dec 31 12:28:50 PM PST 23 |
Dec 31 12:29:42 PM PST 23 |
2343949896 ps |
| T886 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1566531667 |
|
|
Dec 31 12:29:41 PM PST 23 |
Dec 31 01:43:48 PM PST 23 |
981487395 ps |
| T887 |
/workspace/coverage/default/23.sram_ctrl_partial_access.2938626700 |
|
|
Dec 31 12:28:59 PM PST 23 |
Dec 31 12:29:14 PM PST 23 |
43458430 ps |
| T888 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.2049767757 |
|
|
Dec 31 12:28:25 PM PST 23 |
Dec 31 12:28:30 PM PST 23 |
226963163 ps |
| T889 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.418756974 |
|
|
Dec 31 12:27:51 PM PST 23 |
Dec 31 12:37:54 PM PST 23 |
707334317 ps |
| T890 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.2172817877 |
|
|
Dec 31 12:27:36 PM PST 23 |
Dec 31 12:28:10 PM PST 23 |
367339786 ps |
| T32 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.2902537319 |
|
|
Dec 31 12:27:11 PM PST 23 |
Dec 31 12:27:15 PM PST 23 |
321295761 ps |
| T891 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.4118310108 |
|
|
Dec 31 12:29:17 PM PST 23 |
Dec 31 12:31:05 PM PST 23 |
2464246768 ps |
| T892 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.3119844530 |
|
|
Dec 31 12:28:09 PM PST 23 |
Dec 31 12:28:14 PM PST 23 |
207799412 ps |
| T893 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.764264722 |
|
|
Dec 31 12:30:33 PM PST 23 |
Dec 31 12:30:49 PM PST 23 |
929411712 ps |
| T894 |
/workspace/coverage/default/28.sram_ctrl_regwen.538398557 |
|
|
Dec 31 12:29:47 PM PST 23 |
Dec 31 12:30:33 PM PST 23 |
13037511214 ps |
| T895 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.2340653207 |
|
|
Dec 31 12:28:05 PM PST 23 |
Dec 31 12:28:36 PM PST 23 |
168653732 ps |
| T896 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.682682547 |
|
|
Dec 31 12:29:15 PM PST 23 |
Dec 31 12:30:41 PM PST 23 |
124415940 ps |
| T897 |
/workspace/coverage/default/30.sram_ctrl_regwen.3646013410 |
|
|
Dec 31 12:31:13 PM PST 23 |
Dec 31 12:50:37 PM PST 23 |
29119813266 ps |
| T898 |
/workspace/coverage/default/34.sram_ctrl_stress_all.1061050750 |
|
|
Dec 31 12:28:32 PM PST 23 |
Dec 31 01:03:41 PM PST 23 |
31393139037 ps |
| T899 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.537723088 |
|
|
Dec 31 12:28:22 PM PST 23 |
Dec 31 12:28:45 PM PST 23 |
92266888 ps |
| T900 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.4259933110 |
|
|
Dec 31 12:29:35 PM PST 23 |
Dec 31 12:32:22 PM PST 23 |
1770743444 ps |
| T901 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2193127383 |
|
|
Dec 31 12:28:28 PM PST 23 |
Dec 31 12:53:33 PM PST 23 |
1575995759 ps |
| T902 |
/workspace/coverage/default/35.sram_ctrl_bijection.2710043223 |
|
|
Dec 31 12:29:31 PM PST 23 |
Dec 31 12:30:29 PM PST 23 |
10829229952 ps |
| T903 |
/workspace/coverage/default/49.sram_ctrl_smoke.371979704 |
|
|
Dec 31 12:29:23 PM PST 23 |
Dec 31 12:29:33 PM PST 23 |
642671003 ps |
| T904 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.798197598 |
|
|
Dec 31 12:30:32 PM PST 23 |
Dec 31 12:30:45 PM PST 23 |
253788722 ps |
| T905 |
/workspace/coverage/default/25.sram_ctrl_smoke.4058739964 |
|
|
Dec 31 12:31:08 PM PST 23 |
Dec 31 12:31:25 PM PST 23 |
215640776 ps |
| T906 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.1180749621 |
|
|
Dec 31 12:28:42 PM PST 23 |
Dec 31 12:31:37 PM PST 23 |
7464879438 ps |
| T907 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.3750958891 |
|
|
Dec 31 12:29:01 PM PST 23 |
Dec 31 12:29:09 PM PST 23 |
42561028 ps |
| T908 |
/workspace/coverage/default/49.sram_ctrl_alert_test.241245119 |
|
|
Dec 31 12:29:50 PM PST 23 |
Dec 31 12:29:53 PM PST 23 |
15314289 ps |
| T909 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.3009196701 |
|
|
Dec 31 12:30:43 PM PST 23 |
Dec 31 12:30:58 PM PST 23 |
797909223 ps |
| T910 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2642373204 |
|
|
Dec 31 12:30:18 PM PST 23 |
Dec 31 12:34:39 PM PST 23 |
10970908262 ps |
| T911 |
/workspace/coverage/default/23.sram_ctrl_bijection.3850036824 |
|
|
Dec 31 12:28:47 PM PST 23 |
Dec 31 12:29:32 PM PST 23 |
10425483204 ps |
| T912 |
/workspace/coverage/default/6.sram_ctrl_bijection.2541081489 |
|
|
Dec 31 12:27:42 PM PST 23 |
Dec 31 12:28:09 PM PST 23 |
2421935436 ps |
| T913 |
/workspace/coverage/default/9.sram_ctrl_regwen.2558576877 |
|
|
Dec 31 12:28:08 PM PST 23 |
Dec 31 12:38:13 PM PST 23 |
2021810539 ps |
| T914 |
/workspace/coverage/default/17.sram_ctrl_executable.778922982 |
|
|
Dec 31 12:28:13 PM PST 23 |
Dec 31 12:31:09 PM PST 23 |
6043836139 ps |
| T915 |
/workspace/coverage/default/20.sram_ctrl_partial_access.1080747448 |
|
|
Dec 31 12:28:34 PM PST 23 |
Dec 31 12:28:47 PM PST 23 |
513785362 ps |
| T916 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.1575185664 |
|
|
Dec 31 12:29:21 PM PST 23 |
Dec 31 12:36:09 PM PST 23 |
33420405819 ps |
| T917 |
/workspace/coverage/default/2.sram_ctrl_regwen.562856622 |
|
|
Dec 31 12:29:01 PM PST 23 |
Dec 31 12:36:23 PM PST 23 |
6156484386 ps |
| T918 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3565860021 |
|
|
Dec 31 12:28:57 PM PST 23 |
Dec 31 01:05:26 PM PST 23 |
3331768851 ps |
| T919 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.3379744322 |
|
|
Dec 31 12:29:22 PM PST 23 |
Dec 31 12:37:20 PM PST 23 |
7963894046 ps |
| T920 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1554729260 |
|
|
Dec 31 12:28:32 PM PST 23 |
Dec 31 12:35:47 PM PST 23 |
6186624534 ps |
| T921 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.18941638 |
|
|
Dec 31 12:28:48 PM PST 23 |
Dec 31 12:35:16 PM PST 23 |
3203693413 ps |
| T922 |
/workspace/coverage/default/47.sram_ctrl_regwen.3804139700 |
|
|
Dec 31 12:29:23 PM PST 23 |
Dec 31 12:48:29 PM PST 23 |
45231451842 ps |
| T923 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.875403796 |
|
|
Dec 31 12:28:41 PM PST 23 |
Dec 31 12:28:50 PM PST 23 |
170377741 ps |
| T924 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.387971077 |
|
|
Dec 31 12:28:18 PM PST 23 |
Dec 31 12:33:38 PM PST 23 |
4420143346 ps |
| T925 |
/workspace/coverage/default/48.sram_ctrl_regwen.2096953158 |
|
|
Dec 31 12:30:58 PM PST 23 |
Dec 31 12:34:37 PM PST 23 |
7588173103 ps |
| T926 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.1827203527 |
|
|
Dec 31 12:29:24 PM PST 23 |
Dec 31 12:29:26 PM PST 23 |
46176292 ps |
| T927 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.748054931 |
|
|
Dec 31 12:28:47 PM PST 23 |
Dec 31 12:32:27 PM PST 23 |
2264629479 ps |
| T928 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.1659544696 |
|
|
Dec 31 12:28:35 PM PST 23 |
Dec 31 12:34:06 PM PST 23 |
6316998299 ps |
| T929 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.303598456 |
|
|
Dec 31 12:28:59 PM PST 23 |
Dec 31 12:29:16 PM PST 23 |
149314680 ps |
| T930 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3680010757 |
|
|
Dec 31 12:28:32 PM PST 23 |
Dec 31 12:52:21 PM PST 23 |
881938716 ps |
| T931 |
/workspace/coverage/default/0.sram_ctrl_bijection.3934785309 |
|
|
Dec 31 12:27:52 PM PST 23 |
Dec 31 12:29:24 PM PST 23 |
27040700937 ps |
| T932 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.2851159813 |
|
|
Dec 31 12:28:45 PM PST 23 |
Dec 31 12:29:00 PM PST 23 |
1568825079 ps |
| T933 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.1503211515 |
|
|
Dec 31 12:29:09 PM PST 23 |
Dec 31 12:30:25 PM PST 23 |
596310028 ps |
| T934 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.4145500145 |
|
|
Dec 31 12:28:28 PM PST 23 |
Dec 31 12:31:46 PM PST 23 |
4165447102 ps |
| T935 |
/workspace/coverage/default/23.sram_ctrl_alert_test.3022942683 |
|
|
Dec 31 12:28:52 PM PST 23 |
Dec 31 12:28:57 PM PST 23 |
29041456 ps |
| T936 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3212290655 |
|
|
Dec 31 12:28:01 PM PST 23 |
Dec 31 12:31:11 PM PST 23 |
1965483786 ps |
| T937 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.3102534940 |
|
|
Dec 31 12:29:44 PM PST 23 |
Dec 31 12:33:58 PM PST 23 |
2655690735 ps |
| T938 |
/workspace/coverage/default/21.sram_ctrl_alert_test.809384800 |
|
|
Dec 31 12:28:47 PM PST 23 |
Dec 31 12:28:53 PM PST 23 |
12796276 ps |
| T939 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.2464675239 |
|
|
Dec 31 12:28:44 PM PST 23 |
Dec 31 12:34:04 PM PST 23 |
12684746940 ps |
| T940 |
/workspace/coverage/default/22.sram_ctrl_regwen.1211757665 |
|
|
Dec 31 12:28:21 PM PST 23 |
Dec 31 12:35:43 PM PST 23 |
6820342767 ps |
| T941 |
/workspace/coverage/default/35.sram_ctrl_executable.3797859379 |
|
|
Dec 31 12:29:22 PM PST 23 |
Dec 31 12:42:10 PM PST 23 |
23629255232 ps |
| T942 |
/workspace/coverage/default/17.sram_ctrl_regwen.932538667 |
|
|
Dec 31 12:28:11 PM PST 23 |
Dec 31 12:42:23 PM PST 23 |
56033635909 ps |
| T943 |
/workspace/coverage/default/17.sram_ctrl_bijection.1863304936 |
|
|
Dec 31 12:28:44 PM PST 23 |
Dec 31 12:29:14 PM PST 23 |
1530101284 ps |
| T944 |
/workspace/coverage/default/22.sram_ctrl_smoke.3153250479 |
|
|
Dec 31 12:28:41 PM PST 23 |
Dec 31 12:29:29 PM PST 23 |
126703338 ps |
| T945 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.1758654540 |
|
|
Dec 31 12:28:39 PM PST 23 |
Dec 31 12:30:29 PM PST 23 |
2260119979 ps |
| T946 |
/workspace/coverage/default/36.sram_ctrl_smoke.3802122791 |
|
|
Dec 31 12:28:55 PM PST 23 |
Dec 31 12:29:09 PM PST 23 |
378169197 ps |
| T947 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.101597618 |
|
|
Dec 31 12:30:28 PM PST 23 |
Dec 31 12:39:27 PM PST 23 |
451047894 ps |
| T948 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.4223602777 |
|
|
Dec 31 12:29:13 PM PST 23 |
Dec 31 12:29:22 PM PST 23 |
90133910 ps |
| T949 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1599744895 |
|
|
Dec 31 12:30:37 PM PST 23 |
Dec 31 12:38:54 PM PST 23 |
23658495882 ps |
| T950 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.1270311076 |
|
|
Dec 31 12:29:34 PM PST 23 |
Dec 31 12:29:43 PM PST 23 |
344408124 ps |
| T951 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2720087647 |
|
|
Dec 31 12:30:52 PM PST 23 |
Dec 31 12:42:29 PM PST 23 |
2113767710 ps |
| T952 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.2944554065 |
|
|
Dec 31 12:27:45 PM PST 23 |
Dec 31 12:27:56 PM PST 23 |
667545167 ps |
| T953 |
/workspace/coverage/default/0.sram_ctrl_executable.3777226448 |
|
|
Dec 31 12:28:03 PM PST 23 |
Dec 31 12:30:44 PM PST 23 |
8256672866 ps |
| T954 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.682582894 |
|
|
Dec 31 12:29:31 PM PST 23 |
Dec 31 12:29:38 PM PST 23 |
189239788 ps |
| T955 |
/workspace/coverage/default/19.sram_ctrl_executable.2081084094 |
|
|
Dec 31 12:28:44 PM PST 23 |
Dec 31 12:36:17 PM PST 23 |
55812757321 ps |
| T956 |
/workspace/coverage/default/39.sram_ctrl_partial_access.332602363 |
|
|
Dec 31 12:28:56 PM PST 23 |
Dec 31 12:29:03 PM PST 23 |
163395264 ps |
| T957 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2809866789 |
|
|
Dec 31 12:29:13 PM PST 23 |
Dec 31 12:34:54 PM PST 23 |
20159667872 ps |
| T98 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.4072901100 |
|
|
Dec 31 12:29:08 PM PST 23 |
Dec 31 12:29:19 PM PST 23 |
255400282 ps |
| T958 |
/workspace/coverage/default/44.sram_ctrl_regwen.1805974005 |
|
|
Dec 31 12:30:35 PM PST 23 |
Dec 31 12:42:18 PM PST 23 |
31967348411 ps |
| T959 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.1617586618 |
|
|
Dec 31 12:29:33 PM PST 23 |
Dec 31 12:31:06 PM PST 23 |
138434261 ps |
| T960 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1635885112 |
|
|
Dec 31 12:29:11 PM PST 23 |
Dec 31 01:17:12 PM PST 23 |
1046116066 ps |
| T961 |
/workspace/coverage/default/18.sram_ctrl_regwen.3555283849 |
|
|
Dec 31 12:28:19 PM PST 23 |
Dec 31 12:43:40 PM PST 23 |
10399007375 ps |
| T962 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2703872013 |
|
|
Dec 31 12:28:18 PM PST 23 |
Dec 31 12:46:20 PM PST 23 |
879348948 ps |
| T963 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.3298305732 |
|
|
Dec 31 12:29:02 PM PST 23 |
Dec 31 12:29:21 PM PST 23 |
591690470 ps |
| T964 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.4137902500 |
|
|
Dec 31 12:29:35 PM PST 23 |
Dec 31 12:33:45 PM PST 23 |
3661400203 ps |
| T965 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.3200279102 |
|
|
Dec 31 12:28:01 PM PST 23 |
Dec 31 12:33:41 PM PST 23 |
15155391404 ps |
| T966 |
/workspace/coverage/default/17.sram_ctrl_smoke.860228808 |
|
|
Dec 31 12:28:15 PM PST 23 |
Dec 31 12:28:30 PM PST 23 |
488441404 ps |
| T967 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.733142645 |
|
|
Dec 31 12:27:44 PM PST 23 |
Dec 31 12:29:13 PM PST 23 |
300600550 ps |
| T968 |
/workspace/coverage/default/39.sram_ctrl_alert_test.3439111404 |
|
|
Dec 31 12:28:45 PM PST 23 |
Dec 31 12:28:52 PM PST 23 |
41697797 ps |
| T969 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.1723297607 |
|
|
Dec 31 12:28:49 PM PST 23 |
Dec 31 12:30:37 PM PST 23 |
159168610 ps |
| T970 |
/workspace/coverage/default/43.sram_ctrl_stress_all.466545181 |
|
|
Dec 31 12:29:23 PM PST 23 |
Dec 31 12:54:11 PM PST 23 |
23308203198 ps |
| T971 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.1556745914 |
|
|
Dec 31 12:28:53 PM PST 23 |
Dec 31 12:45:38 PM PST 23 |
37047492873 ps |
| T972 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.42919886 |
|
|
Dec 31 12:28:06 PM PST 23 |
Dec 31 12:30:43 PM PST 23 |
1345026323 ps |
| T973 |
/workspace/coverage/default/21.sram_ctrl_partial_access.3303509833 |
|
|
Dec 31 12:28:36 PM PST 23 |
Dec 31 12:28:51 PM PST 23 |
1409176523 ps |
| T974 |
/workspace/coverage/default/21.sram_ctrl_regwen.2855942881 |
|
|
Dec 31 12:29:17 PM PST 23 |
Dec 31 12:43:47 PM PST 23 |
5976384743 ps |
| T975 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.645867432 |
|
|
Dec 31 12:27:57 PM PST 23 |
Dec 31 12:44:43 PM PST 23 |
13389598907 ps |
| T976 |
/workspace/coverage/default/8.sram_ctrl_partial_access.2488349016 |
|
|
Dec 31 12:30:03 PM PST 23 |
Dec 31 12:31:15 PM PST 23 |
512579165 ps |
| T977 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.1481679503 |
|
|
Dec 31 12:29:53 PM PST 23 |
Dec 31 12:30:04 PM PST 23 |
714705100 ps |
| T978 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.1656625690 |
|
|
Dec 31 12:28:44 PM PST 23 |
Dec 31 12:28:54 PM PST 23 |
55670391 ps |
| T979 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.673923977 |
|
|
Dec 31 12:29:11 PM PST 23 |
Dec 31 12:33:28 PM PST 23 |
12464399085 ps |
| T980 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.546693811 |
|
|
Dec 31 12:28:50 PM PST 23 |
Dec 31 12:29:00 PM PST 23 |
65115676 ps |
| T981 |
/workspace/coverage/default/22.sram_ctrl_bijection.2875517359 |
|
|
Dec 31 12:30:00 PM PST 23 |
Dec 31 12:31:12 PM PST 23 |
4150106820 ps |
| T982 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.2445370291 |
|
|
Dec 31 12:28:30 PM PST 23 |
Dec 31 12:39:13 PM PST 23 |
131982636675 ps |
| T983 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.1365297264 |
|
|
Dec 31 12:29:41 PM PST 23 |
Dec 31 12:29:48 PM PST 23 |
604762488 ps |
| T984 |
/workspace/coverage/default/33.sram_ctrl_alert_test.3624108885 |
|
|
Dec 31 12:28:51 PM PST 23 |
Dec 31 12:28:57 PM PST 23 |
21311871 ps |
| T985 |
/workspace/coverage/default/31.sram_ctrl_smoke.4140805151 |
|
|
Dec 31 12:31:14 PM PST 23 |
Dec 31 12:32:51 PM PST 23 |
257993130 ps |
| T986 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.1885910117 |
|
|
Dec 31 12:28:34 PM PST 23 |
Dec 31 12:30:39 PM PST 23 |
1330630414 ps |
| T987 |
/workspace/coverage/default/12.sram_ctrl_stress_all.4251809105 |
|
|
Dec 31 12:30:27 PM PST 23 |
Dec 31 01:53:03 PM PST 23 |
379690232076 ps |
| T988 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3526205655 |
|
|
Dec 31 12:29:33 PM PST 23 |
Dec 31 12:30:14 PM PST 23 |
432771761 ps |
| T989 |
/workspace/coverage/default/47.sram_ctrl_alert_test.1162573050 |
|
|
Dec 31 12:31:01 PM PST 23 |
Dec 31 12:31:09 PM PST 23 |
100439067 ps |
| T990 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.2792757826 |
|
|
Dec 31 12:28:49 PM PST 23 |
Dec 31 12:41:36 PM PST 23 |
12586486511 ps |
| T991 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.2374976585 |
|
|
Dec 31 12:28:35 PM PST 23 |
Dec 31 12:29:39 PM PST 23 |
113272964 ps |
| T992 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.4020196957 |
|
|
Dec 31 12:28:05 PM PST 23 |
Dec 31 12:31:12 PM PST 23 |
7499018408 ps |
| T993 |
/workspace/coverage/default/39.sram_ctrl_stress_all.4273731767 |
|
|
Dec 31 12:30:12 PM PST 23 |
Dec 31 01:06:49 PM PST 23 |
38664456343 ps |
| T994 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.2927369050 |
|
|
Dec 31 12:29:31 PM PST 23 |
Dec 31 12:29:38 PM PST 23 |
73816466 ps |
| T995 |
/workspace/coverage/default/7.sram_ctrl_stress_all.902585490 |
|
|
Dec 31 12:27:52 PM PST 23 |
Dec 31 01:43:18 PM PST 23 |
168782595991 ps |
| T996 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2619841442 |
|
|
Dec 31 12:28:01 PM PST 23 |
Dec 31 12:33:20 PM PST 23 |
26115263838 ps |
| T997 |
/workspace/coverage/default/27.sram_ctrl_executable.1372430690 |
|
|
Dec 31 12:29:02 PM PST 23 |
Dec 31 12:49:13 PM PST 23 |
51721773135 ps |
| T998 |
/workspace/coverage/default/23.sram_ctrl_stress_all.199697030 |
|
|
Dec 31 12:28:55 PM PST 23 |
Dec 31 01:44:25 PM PST 23 |
26878652596 ps |
| T999 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.4155920272 |
|
|
Dec 31 12:29:56 PM PST 23 |
Dec 31 01:36:17 PM PST 23 |
3716262391 ps |
| T1000 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.1577824979 |
|
|
Dec 31 12:29:19 PM PST 23 |
Dec 31 12:45:21 PM PST 23 |
7030292205 ps |
| T1001 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1901499164 |
|
|
Dec 31 12:28:52 PM PST 23 |
Dec 31 12:36:28 PM PST 23 |
6792654903 ps |