Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13936786	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

57525769

1

T1

102729

T2

9162

T3

6142

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35613907	1			T1	56372		T2	4577		T3	2048
values[0x0]	16527099	1			T1	27348		T2	2293		T3	2064
values[0x1]	19321549	1			T1	29237		T2	2292		T3	2030

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6944675	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

64517880

1

T1

107877

T2

9162

T3

6142

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	270421	1			T1	458		T2	17		T3	20
valid_sources[0x01]	340000	1			T1	394		T2	28		T3	28
valid_sources[0x02]	287750	1			T1	417		T2	74		T3	31
valid_sources[0x03]	407468	1			T1	466		T2	51		T3	27
valid_sources[0x04]	298487	1			T1	410		T2	34		T3	18
valid_sources[0x05]	344937	1			T1	355		T2	43		T3	15
valid_sources[0x06]	307471	1			T1	438		T2	22		T3	25
valid_sources[0x07]	264988	1			T1	473		T2	48		T3	25
valid_sources[0x08]	283979	1			T1	394		T2	29		T3	24
valid_sources[0x09]	364154	1			T1	389		T2	37		T3	23
valid_sources[0x0a]	272577	1			T1	390		T2	38		T3	22
valid_sources[0x0b]	260907	1			T1	373		T2	25		T3	18
valid_sources[0x0c]	240929	1			T1	519		T2	70		T3	26
valid_sources[0x0d]	305961	1			T1	607		T2	25		T3	31
valid_sources[0x0e]	286926	1			T1	446		T2	75		T3	22
valid_sources[0x0f]	286079	1			T1	458		T2	43		T3	27
valid_sources[0x10]	239606	1			T1	499		T2	42		T3	35
valid_sources[0x11]	284421	1			T1	531		T2	20		T3	19
valid_sources[0x12]	252753	1			T1	427		T2	22		T3	41
valid_sources[0x13]	317484	1			T1	578		T2	28		T3	28
valid_sources[0x14]	230145	1			T1	384		T2	82		T3	26
valid_sources[0x15]	243000	1			T1	417		T2	54		T3	22
valid_sources[0x16]	276399	1			T1	438		T2	27		T3	20
valid_sources[0x17]	337442	1			T1	427		T2	33		T3	24
valid_sources[0x18]	238242	1			T1	381		T2	59		T3	23
valid_sources[0x19]	290571	1			T1	471		T2	14		T3	25
valid_sources[0x1a]	257467	1			T1	520		T2	26		T3	33
valid_sources[0x1b]	258998	1			T1	491		T2	19		T3	33
valid_sources[0x1c]	337843	1			T1	579		T2	17		T3	22
valid_sources[0x1d]	271899	1			T1	406		T2	26		T3	17
valid_sources[0x1e]	230907	1			T1	474		T2	26		T3	14
valid_sources[0x1f]	261601	1			T1	435		T2	28		T3	25
valid_sources[0x20]	265227	1			T1	406		T2	34		T3	20
valid_sources[0x21]	278610	1			T1	357		T2	28		T3	25
valid_sources[0x22]	309764	1			T1	482		T2	72		T3	15
valid_sources[0x23]	233974	1			T1	417		T2	42		T3	27
valid_sources[0x24]	247590	1			T1	435		T2	30		T3	18
valid_sources[0x25]	280844	1			T1	381		T2	32		T3	21
valid_sources[0x26]	302336	1			T1	416		T2	24		T3	21
valid_sources[0x27]	350462	1			T1	484		T2	26		T3	20
valid_sources[0x28]	228631	1			T1	408		T2	40		T3	35
valid_sources[0x29]	313492	1			T1	367		T2	29		T3	20
valid_sources[0x2a]	226335	1			T1	332		T2	20		T3	21
valid_sources[0x2b]	290162	1			T1	421		T2	32		T3	16
valid_sources[0x2c]	248450	1			T1	382		T2	26		T3	22
valid_sources[0x2d]	297430	1			T1	453		T2	55		T3	24
valid_sources[0x2e]	277897	1			T1	363		T2	51		T3	19
valid_sources[0x2f]	335836	1			T1	459		T2	32		T3	20
valid_sources[0x30]	249039	1			T1	478		T2	9		T3	22
valid_sources[0x31]	273340	1			T1	379		T2	26		T3	24
valid_sources[0x32]	241968	1			T1	425		T2	60		T3	27
valid_sources[0x33]	295254	1			T1	425		T2	41		T3	30
valid_sources[0x34]	269450	1			T1	471		T2	37		T3	21
valid_sources[0x35]	297166	1			T1	466		T2	40		T3	18
valid_sources[0x36]	229598	1			T1	384		T2	49		T3	27
valid_sources[0x37]	301236	1			T1	496		T2	46		T3	22
valid_sources[0x38]	247745	1			T1	435		T2	19		T3	21
valid_sources[0x39]	290905	1			T1	501		T2	57		T3	19
valid_sources[0x3a]	247424	1			T1	587		T2	64		T3	34
valid_sources[0x3b]	340428	1			T1	506		T2	35		T3	24
valid_sources[0x3c]	288487	1			T1	372		T2	49		T3	30
valid_sources[0x3d]	313275	1			T1	419		T2	50		T3	9
valid_sources[0x3e]	225205	1			T1	379		T2	49		T3	16
valid_sources[0x3f]	301149	1			T1	456		T2	31		T3	23
valid_sources[0x40]	268195	1			T1	375		T2	67		T3	30
valid_sources[0x41]	249262	1			T1	440		T2	25		T3	14
valid_sources[0x42]	251822	1			T1	470		T2	36		T3	26
valid_sources[0x43]	261064	1			T1	411		T2	37		T3	14
valid_sources[0x44]	272992	1			T1	478		T2	10		T3	31
valid_sources[0x45]	283223	1			T1	484		T2	23		T3	22
valid_sources[0x46]	259689	1			T1	482		T2	33		T3	19
valid_sources[0x47]	232341	1			T1	467		T2	33		T3	28
valid_sources[0x48]	289703	1			T1	388		T2	52		T3	22
valid_sources[0x49]	282480	1			T1	461		T2	50		T3	23
valid_sources[0x4a]	289955	1			T1	425		T2	52		T3	27
valid_sources[0x4b]	286818	1			T1	478		T2	52		T3	25
valid_sources[0x4c]	250190	1			T1	459		T2	29		T3	25
valid_sources[0x4d]	280163	1			T1	481		T2	20		T3	25
valid_sources[0x4e]	249251	1			T1	392		T2	53		T3	20
valid_sources[0x4f]	249422	1			T1	453		T2	36		T3	19
valid_sources[0x50]	292317	1			T1	448		T2	67		T3	18
valid_sources[0x51]	237896	1			T1	507		T2	31		T3	37
valid_sources[0x52]	354190	1			T1	464		T2	27		T3	23
valid_sources[0x53]	254347	1			T1	468		T2	70		T3	38
valid_sources[0x54]	267688	1			T1	501		T2	44		T3	22
valid_sources[0x55]	230409	1			T1	325		T2	71		T3	18
valid_sources[0x56]	293748	1			T1	336		T2	31		T3	23
valid_sources[0x57]	235237	1			T1	561		T2	36		T3	25
valid_sources[0x58]	253206	1			T1	454		T2	35		T3	20
valid_sources[0x59]	332096	1			T1	419		T2	31		T3	28
valid_sources[0x5a]	262245	1			T1	511		T2	37		T3	18
valid_sources[0x5b]	296472	1			T1	445		T2	77		T3	29
valid_sources[0x5c]	259327	1			T1	412		T2	17		T3	28
valid_sources[0x5d]	249184	1			T1	412		T2	16		T3	30
valid_sources[0x5e]	241569	1			T1	375		T2	28		T3	25
valid_sources[0x5f]	239170	1			T1	416		T2	24		T3	33
valid_sources[0x60]	280919	1			T1	467		T2	11		T3	16
valid_sources[0x61]	297664	1			T1	418		T2	53		T3	30
valid_sources[0x62]	366067	1			T1	384		T2	27		T3	27
valid_sources[0x63]	256010	1			T1	418		T2	37		T3	28
valid_sources[0x64]	237777	1			T1	487		T2	28		T3	27
valid_sources[0x65]	329893	1			T1	413		T2	64		T3	29
valid_sources[0x66]	239036	1			T1	474		T2	29		T3	26
valid_sources[0x67]	225059	1			T1	360		T2	18		T3	31
valid_sources[0x68]	253746	1			T1	479		T2	27		T3	17
valid_sources[0x69]	295822	1			T1	489		T2	29		T3	25
valid_sources[0x6a]	294029	1			T1	345		T2	37		T3	22
valid_sources[0x6b]	309216	1			T1	447		T2	24		T3	13
valid_sources[0x6c]	242028	1			T1	509		T2	27		T3	23
valid_sources[0x6d]	281129	1			T1	393		T2	16		T3	21
valid_sources[0x6e]	231795	1			T1	418		T2	46		T3	21
valid_sources[0x6f]	298458	1			T1	402		T2	44		T3	31
valid_sources[0x70]	371406	1			T1	512		T2	36		T3	29
valid_sources[0x71]	333024	1			T1	417		T2	20		T3	30
valid_sources[0x72]	310857	1			T1	431		T2	51		T3	24
valid_sources[0x73]	248035	1			T1	417		T2	17		T3	19
valid_sources[0x74]	258828	1			T1	464		T2	42		T3	22
valid_sources[0x75]	250366	1			T1	477		T2	33		T3	22
valid_sources[0x76]	284948	1			T1	395		T2	20		T3	27
valid_sources[0x77]	272269	1			T1	474		T2	10		T3	17
valid_sources[0x78]	264975	1			T1	448		T2	45		T3	21
valid_sources[0x79]	304045	1			T1	474		T2	52		T3	20
valid_sources[0x7a]	278188	1			T1	490		T2	30		T3	23
valid_sources[0x7b]	298694	1			T1	427		T2	20		T3	22
valid_sources[0x7c]	224091	1			T1	516		T2	54		T3	20
valid_sources[0x7d]	262269	1			T1	389		T2	34		T3	19
valid_sources[0x7e]	319660	1			T1	367		T2	27		T3	17
valid_sources[0x7f]	267110	1			T1	396		T2	14		T3	26
valid_sources[0x80]	226637	1			T1	391		T2	57		T3	20

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28654127

1

T1

51236

T2

4577

T3

2048

values[0x0]

all_enables

biggest_size

14434626

1

T1

25772

T2

2293

T3

2064

values[0x1]

all_enables

biggest_size

14437016

1

T1

25721

T2

2292

T3

2030

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2172217	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

139699

1

T1

7

T4

3

T5

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2190236	1			T1	6762		T2	1244		T4	1930
values[0x0]	58900	1			T1	10		T2	1		T4	6
values[0x1]	62780	1			T1	10		T2	1		T4	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1452336	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

859580

1

T1

2267

T2

426

T4

663

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7214	1			T1	38		T2	3		T4	5
valid_sources[0x01]	7054	1			T1	9		T2	7		T4	19
valid_sources[0x02]	7008	1			T1	12		T2	5		T4	1
valid_sources[0x03]	7590	1			T1	40		T2	1		T4	6
valid_sources[0x04]	16224	1			T1	26		T5	10		T14	4
valid_sources[0x05]	11406	1			T1	32		T2	15		T4	11
valid_sources[0x06]	7832	1			T1	31		T2	2		T4	4
valid_sources[0x07]	9212	1			T1	23		T2	4		T4	15
valid_sources[0x08]	7266	1			T1	33		T2	1		T14	1
valid_sources[0x09]	17036	1			T1	29		T4	14		T5	10
valid_sources[0x0a]	9095	1			T1	42		T4	9		T5	3
valid_sources[0x0b]	16482	1			T1	19		T2	3		T4	19
valid_sources[0x0c]	7818	1			T1	18		T2	2		T4	3
valid_sources[0x0d]	14267	1			T1	40		T2	7		T14	4
valid_sources[0x0e]	11527	1			T1	43		T2	9		T4	1
valid_sources[0x0f]	7170	1			T1	21		T2	7		T4	12
valid_sources[0x10]	7193	1			T1	28		T2	5		T4	13
valid_sources[0x11]	7100	1			T1	23		T2	3		T4	4
valid_sources[0x12]	22243	1			T1	24		T2	9		T4	5
valid_sources[0x13]	8460	1			T1	42		T2	11		T4	15
valid_sources[0x14]	7389	1			T1	39		T2	10		T4	4
valid_sources[0x15]	7374	1			T1	12		T2	6		T4	5
valid_sources[0x16]	7168	1			T1	37		T2	4		T4	12
valid_sources[0x17]	10494	1			T1	21		T2	4		T14	3
valid_sources[0x18]	7593	1			T1	36		T2	3		T4	13
valid_sources[0x19]	10452	1			T1	18		T2	3		T4	18
valid_sources[0x1a]	12414	1			T1	30		T2	16		T4	10
valid_sources[0x1b]	9717	1			T1	21		T2	7		T4	7
valid_sources[0x1c]	16093	1			T1	38		T2	6		T4	9
valid_sources[0x1d]	11597	1			T1	22		T2	3		T4	2
valid_sources[0x1e]	15355	1			T1	18		T2	7		T5	10
valid_sources[0x1f]	7921	1			T1	24		T2	5		T14	2
valid_sources[0x20]	7412	1			T1	8		T2	5		T4	27
valid_sources[0x21]	7497	1			T1	44		T2	2		T4	35
valid_sources[0x22]	8595	1			T1	6		T2	9		T4	20
valid_sources[0x23]	15682	1			T1	36		T2	1		T4	11
valid_sources[0x24]	7271	1			T1	40		T2	6		T18	32
valid_sources[0x25]	8504	1			T1	24		T2	30		T4	19
valid_sources[0x26]	6790	1			T1	33		T2	3		T4	9
valid_sources[0x27]	7057	1			T1	15		T2	14		T4	9
valid_sources[0x28]	7977	1			T1	17		T2	1		T5	4
valid_sources[0x29]	14235	1			T1	16		T2	12		T4	4
valid_sources[0x2a]	6770	1			T1	33		T2	2		T4	20
valid_sources[0x2b]	6864	1			T1	30		T2	1		T4	14
valid_sources[0x2c]	7855	1			T1	24		T14	1		T18	28
valid_sources[0x2d]	6963	1			T1	35		T2	2		T4	16
valid_sources[0x2e]	7384	1			T1	27		T2	4		T4	6
valid_sources[0x2f]	6927	1			T1	27		T2	3		T4	15
valid_sources[0x30]	6921	1			T1	12		T2	1		T14	5
valid_sources[0x31]	17663	1			T1	37		T2	6		T4	4
valid_sources[0x32]	10410	1			T1	23		T2	3		T4	17
valid_sources[0x33]	7367	1			T1	20		T2	5		T4	8
valid_sources[0x34]	7131	1			T1	32		T2	3		T4	2
valid_sources[0x35]	10302	1			T1	29		T2	1		T4	15
valid_sources[0x36]	8178	1			T1	46		T2	6		T4	2
valid_sources[0x37]	7110	1			T1	33		T2	9		T4	8
valid_sources[0x38]	6914	1			T1	24		T2	12		T4	2
valid_sources[0x39]	7896	1			T1	20		T2	6		T10	166
valid_sources[0x3a]	10688	1			T1	29		T4	4		T14	8
valid_sources[0x3b]	7709	1			T1	22		T2	2		T4	4
valid_sources[0x3c]	10421	1			T1	13		T2	5		T4	4
valid_sources[0x3d]	7316	1			T1	26		T2	3		T4	20
valid_sources[0x3e]	6846	1			T1	38		T2	3		T4	2
valid_sources[0x3f]	7032	1			T1	25		T2	6		T4	19
valid_sources[0x40]	8879	1			T1	36		T2	10		T4	3
valid_sources[0x41]	7874	1			T1	27		T2	1		T4	7
valid_sources[0x42]	12148	1			T1	33		T2	11		T4	12
valid_sources[0x43]	6994	1			T1	28		T2	2		T4	1
valid_sources[0x44]	7503	1			T1	38		T2	2		T4	8
valid_sources[0x45]	24118	1			T1	29		T2	16		T14	1
valid_sources[0x46]	9451	1			T1	35		T2	6		T4	8
valid_sources[0x47]	17149	1			T1	22		T2	1		T4	10
valid_sources[0x48]	7058	1			T1	14		T2	4		T5	13
valid_sources[0x49]	7105	1			T1	15		T4	11		T14	2
valid_sources[0x4a]	7352	1			T1	25		T2	7		T4	15
valid_sources[0x4b]	8892	1			T1	21		T2	10		T12	1
valid_sources[0x4c]	7042	1			T1	32		T2	2		T4	16
valid_sources[0x4d]	8723	1			T1	13		T2	4		T4	10
valid_sources[0x4e]	6877	1			T1	36		T2	1		T4	7
valid_sources[0x4f]	6957	1			T1	25		T4	1		T5	15
valid_sources[0x50]	7729	1			T1	30		T2	6		T5	9
valid_sources[0x51]	7153	1			T1	33		T2	4		T4	6
valid_sources[0x52]	7299	1			T1	44		T2	1		T4	12
valid_sources[0x53]	10264	1			T1	23		T5	4		T14	3
valid_sources[0x54]	7984	1			T1	30		T2	2		T5	3
valid_sources[0x55]	7104	1			T1	39		T2	6		T4	9
valid_sources[0x56]	6886	1			T1	20		T2	3		T4	11
valid_sources[0x57]	8722	1			T1	10		T2	8		T12	6
valid_sources[0x58]	6714	1			T1	33		T2	3		T4	1
valid_sources[0x59]	6945	1			T1	22		T2	3		T4	5
valid_sources[0x5a]	15027	1			T1	17		T2	4		T5	11
valid_sources[0x5b]	6980	1			T1	26		T2	1		T4	8
valid_sources[0x5c]	7242	1			T1	16		T2	8		T4	14
valid_sources[0x5d]	7279	1			T1	22		T4	10		T14	5
valid_sources[0x5e]	12980	1			T1	31		T2	7		T4	26
valid_sources[0x5f]	7512	1			T1	7		T2	16		T4	13
valid_sources[0x60]	7279	1			T1	37		T2	3		T4	1
valid_sources[0x61]	6959	1			T1	19		T4	3		T5	9
valid_sources[0x62]	7770	1			T1	32		T2	7		T4	27
valid_sources[0x63]	7233	1			T1	32		T2	1		T4	1
valid_sources[0x64]	7170	1			T1	15		T2	2		T4	7
valid_sources[0x65]	7650	1			T1	33		T2	4		T5	11
valid_sources[0x66]	11673	1			T1	22		T2	4		T14	2
valid_sources[0x67]	7494	1			T1	33		T2	6		T4	5
valid_sources[0x68]	7330	1			T1	27		T4	6		T14	1
valid_sources[0x69]	7069	1			T1	20		T2	14		T4	4
valid_sources[0x6a]	8240	1			T1	30		T2	2		T4	9
valid_sources[0x6b]	10922	1			T1	50		T2	5		T4	4
valid_sources[0x6c]	11529	1			T1	22		T2	6		T4	3
valid_sources[0x6d]	7991	1			T1	18		T2	17		T4	7
valid_sources[0x6e]	10692	1			T1	32		T2	2		T5	4
valid_sources[0x6f]	7066	1			T1	22		T2	11		T4	13
valid_sources[0x70]	7452	1			T1	27		T2	10		T4	15
valid_sources[0x71]	7007	1			T1	26		T2	3		T4	7
valid_sources[0x72]	7040	1			T1	28		T2	13		T4	5
valid_sources[0x73]	7493	1			T1	33		T2	5		T4	6
valid_sources[0x74]	7321	1			T1	44		T2	1		T4	4
valid_sources[0x75]	9006	1			T1	22		T2	12		T4	15
valid_sources[0x76]	7994	1			T1	30		T2	10		T4	3
valid_sources[0x77]	7755	1			T1	41		T2	3		T14	1
valid_sources[0x78]	7364	1			T1	27		T2	14		T12	1
valid_sources[0x79]	14464	1			T1	51		T2	6		T4	11
valid_sources[0x7a]	11953	1			T1	21		T2	7		T4	2
valid_sources[0x7b]	6807	1			T1	18		T2	12		T14	2
valid_sources[0x7c]	14721	1			T1	30		T2	12		T5	2
valid_sources[0x7d]	10188	1			T1	27		T2	5		T14	1
valid_sources[0x7e]	18516	1			T1	13		T2	4		T4	12
valid_sources[0x7f]	7216	1			T1	18		T2	6		T4	2
valid_sources[0x80]	7083	1			T1	25		T2	2		T4	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

38340

1

T18

857

T6

31

T7

18

values[0x0]

all_enables

biggest_size

51479

1

T1

4

T4

3

T5

1

values[0x1]

all_enables

biggest_size

49880

1

T1

3

T10

1

T13

1